CN111355481A - Level converter - Google Patents
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- CN111355481A CN111355481A CN202010288907.8A CN202010288907A CN111355481A CN 111355481 A CN111355481 A CN 111355481A CN 202010288907 A CN202010288907 A CN 202010288907A CN 111355481 A CN111355481 A CN 111355481A
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- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 6
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 238000005516 engineering process Methods 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 208000035795 Hypocalcemic vitamin D-dependent rickets Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 208000033584 type 1 vitamin D-dependent rickets Diseases 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
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Abstract
The invention discloses a level shifter. The level shifter includes a Wilson current mirror circuit and an inverter circuit; the Wilson current mirror circuit is connected with the inverter circuit; the inverter circuit includes: a PMOS tube of the phase inverter circuit and an NMOS tube of the phase inverter circuit; the output end of the Wilson current mirror circuit is respectively connected with the grid electrode of a PMOS (P-channel metal oxide semiconductor) tube of the inverter circuit and the grid electrode of an NMOS (N-channel metal oxide semiconductor) tube of the inverter circuit; the source electrode of the PMOS tube of the phase inverter circuit is connected with the power supply of the phase inverter circuit; the drain electrode of the PMOS tube of the phase inverter circuit is connected with the drain electrode of the NMOS tube of the phase inverter circuit; the source electrode of the NMOS tube of the inverter circuit is grounded. The level converter has the advantages of simple circuit structure and capability of effectively reducing the delay time and the power consumption of the circuit.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a level shifter.
Background
The near-threshold technology and the multi-power-domain technology are mainstream technologies for realizing extremely low power consumption design at present, so that a plurality of power domains are often divided during chip design of a plurality of low-power-consumption applications. The circuits with higher performance requirements are divided into a high voltage domain, and the circuits with lower performance requirements work in a low voltage domain. Between different power domains, there are a large number of level shifters to implement signal transfer between different power domains.
The traditional level shifter adopts a cross-coupled structure, has the characteristics of small area, high speed and low static power consumption, but has a limited level shifting range and cannot support the shifting from near-threshold voltage to normal voltage, so that the use of the near-threshold technology is limited. The traditional Wilson current mirror structure can effectively support the level conversion of the voltage in an ultra-wide range from a near threshold voltage to a normal voltage, can meet the requirement of a near threshold technology, but has more transistors and larger electric leakage.
Disclosure of Invention
The invention aims to provide a level converter which has the advantages of simple circuit structure and capability of effectively reducing the delay time and power consumption of a circuit.
In order to achieve the purpose, the invention provides the following scheme:
a level shifter, comprising:
a Wilson current mirror circuit and an inverter circuit; the Wilson current mirror circuit is connected to the inverter circuit;
the inverter circuit specifically includes:
a PMOS tube of the phase inverter circuit and an NMOS tube of the phase inverter circuit;
the output end of the Wilson current mirror circuit is respectively connected with the grid electrode of a PMOS (P-channel metal oxide semiconductor) tube of the inverter circuit and the grid electrode of an NMOS (N-channel metal oxide semiconductor) tube of the inverter circuit; the source electrode of the PMOS tube of the phase inverter circuit is connected with the power supply of the phase inverter circuit; the drain electrode of the PMOS tube of the phase inverter circuit is connected with the drain electrode of the NMOS tube of the phase inverter circuit; the source electrode of the NMOS tube of the inverter circuit is grounded.
Optionally, the wilson current mirror circuit specifically includes:
the PMOS transistor comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor and a second NMOS transistor;
the source electrode of the first PMOS tube is connected with a first power supply of the Wilson current mirror circuit, the drain electrode of the first PMOS tube is respectively connected with the grid electrode of the second PMOS tube and the source electrode of the third PMOS tube, and the grid electrode of the first PMOS tube is also connected with the grid electrode of the second PMOS tube; the source of the second PMOS tube is connected with a second power supply of the Wilson current mirror circuit; the drain electrode of the third PMOS tube is connected with the drain electrode of the first NMOS tube, and the grid electrode of the first NMOS tube is connected with a third power supply of the Wilson current mirror circuit; the source electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, and the source electrode of the second NMOS tube is grounded; and the drain electrode of the second PMOS tube, the grid electrode of the third PMOS tube, the drain electrode of the second NMOS tube and the grid electrode of the PMOS tube of the phase inverter circuit are connected together.
Alternatively to this, the first and second parts may,
the threshold voltage of the first PMOS tube, the threshold voltage of the second PMOS tube and the threshold voltage of the third PMOS tube are all larger than the threshold voltage of the first NMOS tube;
the threshold voltage of the first PMOS tube, the threshold voltage of the second PMOS tube and the threshold voltage of the third PMOS tube are all larger than the threshold voltage of the second NMOS tube.
Alternatively to this, the first and second parts may,
the threshold voltage of a PMOS tube of the phase inverter circuit is greater than the threshold voltage of the first NMOS tube;
the threshold voltage of the PMOS tube of the phase inverter circuit is larger than that of the second NMOS tube.
Alternatively to this, the first and second parts may,
the threshold voltage of an NMOS tube of the inverter circuit is greater than the threshold voltage of the first NMOS tube;
the threshold voltage of the NMOS tube of the phase inverter circuit is larger than that of the second NMOS tube.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides a level shifter which is simple in circuit structure, and greatly reduces circuit delay time and power consumption due to the fact that input signals are saved to pass through a low-voltage phase inverter.
In addition, the first NMOS tube is adopted to replace a low-voltage inverter circuit in the traditional level conversion, the total number of transistors is reduced to 7 from the original 11, and the circuit complexity is greatly reduced. The invention adopts a mixed threshold technology, and adopts a high threshold design for three PMOS tubes in a Wilson current mirror circuit and an NMOS tube of an inverter circuit under a high voltage state. The two NMOS transistors pulled down in the Wilson current mirror circuit are designed by adopting a low threshold value, the structure fully considers the driving capability of the circuit, and the leakage power consumption of the circuit can be effectively reduced while the circuit performance is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a diagram of a level shifter circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a level converter which has the advantages of simple circuit structure and capability of effectively reducing the delay time and power consumption of a circuit.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Examples
As shown in fig. 1, a level shifter includes: a Wilson current mirror circuit and an inverter circuit. The Wilson current mirror circuit is connected to the inverter circuit.
The inverter circuit specifically includes: an inverter circuit PMOS pipe MP4 and an inverter circuit NMOS pipe MN 3. The output end of the Wilson current mirror circuit is respectively connected with the grid of a PMOS transistor MP4 of the inverter circuit and the grid of an NMOS transistor MN3 of the inverter circuit; the source electrode of the PMOS tube MP4 of the inverter circuit is connected with the power supply of the inverter circuit; the drain electrode of the PMOS tube MP4 of the inverter circuit is connected with the drain electrode of the NMOS tube MN3 of the inverter circuit; the source of the NMOS transistor MN3 of the inverter circuit is grounded.
The Wilson current mirror circuit specifically comprises: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, and a second NMOS transistor MN 2.
The source of the first PMOS transistor MP1 is connected to a first power supply VDDH1 of the wilson current mirror circuit, the drain of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2 and the source of the third PMOS transistor MP3, respectively, and the gate of the first PMOS transistor MP1 is also connected to the gate of the second PMOS transistor MP 2; the source of the second PMOS transistor MP2 is connected to the second power supply VDDH2 of the Wilson current mirror circuit; the drain of the third PMOS transistor MP3 is connected to the drain of the first NMOS transistor MN1, and the gate of the first NMOS transistor MN1 is connected to the third power supply VDDI of the wilson current mirror circuit; the source electrode of the first NMOS transistor MN1 is connected with the gate electrode of the second NMOS transistor MN2, and the source electrode of the second NMOS transistor MN2 is grounded; the drain of the second PMOS transistor MP2, the gate of the third PMOS transistor MP3, the drain of the second NMOS transistor MN2 and the gate of the inverter circuit PMOS transistor MP4 are connected together.
The threshold voltage of the first PMOS tube MP1, the threshold voltage of the second PMOS tube MP2 and the threshold voltage of the third PMOS tube MP3 are all larger than the threshold voltage of the first NMOS tube MN 1; the threshold voltage of the first PMOS transistor MP1, the threshold voltage of the second PMOS transistor MP2 and the threshold voltage of the third PMOS transistor MP3 are all larger than the threshold voltage of the second NMOS transistor MN 2.
The threshold voltage of a PMOS transistor MP4 of the inverter circuit is greater than that of a first NMOS transistor MN 1; the threshold voltage of the PMOS transistor MP4 of the inverter circuit is greater than that of the second NMOS transistor MN 2.
The threshold voltage of an NMOS transistor MN3 of the inverter circuit is greater than that of a first NMOS transistor MN 1; the threshold voltage of the NMOS transistor MN3 of the inverter circuit is greater than that of the second NMOS transistor MN 2.
MP1 is a PMOS transistor with high threshold, MP2 is a PMOS transistor with high threshold, MP3 is a PMOS transistor with high threshold, MN1 is an NMOS transistor with low threshold, MN2 is an NMOS transistor with low threshold, MP4 is a PMOS transistor with high threshold, and MN3 is an NMOS transistor with high threshold.
The level shifter provided by the invention is a high-density near-threshold level shifter, is improved on the basis of the traditional Wilson current mirror structure, and adopts pass-tube logic to replace a low-voltage inverter circuit with the original structure. The improvement reduces the total number of transistors from 11 to 7, greatly reduces the circuit complexity of the level converter, and greatly reduces the delay time and power consumption of the circuit due to saving the delay of the low-voltage inverter. In addition, the level shifter adopts a mixed threshold technology, so that the static power consumption of the circuit is further reduced.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In summary, this summary should not be construed to limit the present invention.
Claims (5)
1. A level shifter, comprising:
a Wilson current mirror circuit and an inverter circuit; the Wilson current mirror circuit is connected to the inverter circuit;
the inverter circuit specifically includes:
a PMOS tube of the phase inverter circuit and an NMOS tube of the phase inverter circuit;
the output end of the Wilson current mirror circuit is respectively connected with the grid electrode of a PMOS (P-channel metal oxide semiconductor) tube of the inverter circuit and the grid electrode of an NMOS (N-channel metal oxide semiconductor) tube of the inverter circuit; the source electrode of the PMOS tube of the phase inverter circuit is connected with the power supply of the phase inverter circuit; the drain electrode of the PMOS tube of the phase inverter circuit is connected with the drain electrode of the NMOS tube of the phase inverter circuit; the source electrode of the NMOS tube of the inverter circuit is grounded.
2. The level shifter of claim 1, wherein the Wilson current mirror circuit comprises:
the PMOS transistor comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor and a second NMOS transistor;
the source electrode of the first PMOS tube is connected with a first power supply of the Wilson current mirror circuit, the drain electrode of the first PMOS tube is respectively connected with the grid electrode of the second PMOS tube and the source electrode of the third PMOS tube, and the grid electrode of the first PMOS tube is also connected with the grid electrode of the second PMOS tube; the source of the second PMOS tube is connected with a second power supply of the Wilson current mirror circuit; the drain electrode of the third PMOS tube is connected with the drain electrode of the first NMOS tube, and the grid electrode of the first NMOS tube is connected with a third power supply of the Wilson current mirror circuit; the source electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, and the source electrode of the second NMOS tube is grounded; and the drain electrode of the second PMOS tube, the grid electrode of the third PMOS tube, the drain electrode of the second NMOS tube and the grid electrode of the PMOS tube of the phase inverter circuit are connected together.
3. Level shifter in accordance with claim 2,
the threshold voltage of the first PMOS tube, the threshold voltage of the second PMOS tube and the threshold voltage of the third PMOS tube are all larger than the threshold voltage of the first NMOS tube;
the threshold voltage of the first PMOS tube, the threshold voltage of the second PMOS tube and the threshold voltage of the third PMOS tube are all larger than the threshold voltage of the second NMOS tube.
4. Level shifter in accordance with claim 3,
the threshold voltage of a PMOS tube of the phase inverter circuit is greater than the threshold voltage of the first NMOS tube;
the threshold voltage of the PMOS tube of the phase inverter circuit is larger than that of the second NMOS tube.
5. Level shifter in accordance with claim 4,
the threshold voltage of an NMOS tube of the inverter circuit is greater than the threshold voltage of the first NMOS tube;
the threshold voltage of the NMOS tube of the phase inverter circuit is larger than that of the second NMOS tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010288907.8A CN111355481A (en) | 2020-04-14 | 2020-04-14 | Level converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010288907.8A CN111355481A (en) | 2020-04-14 | 2020-04-14 | Level converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111355481A true CN111355481A (en) | 2020-06-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010288907.8A Pending CN111355481A (en) | 2020-04-14 | 2020-04-14 | Level converter |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111697830A (en) * | 2020-07-08 | 2020-09-22 | 湖南国科微电子股份有限公司 | Voltage conversion circuit for converting low voltage into high voltage and voltage conversion integrated chip |
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| US20070075755A1 (en) * | 2005-09-30 | 2007-04-05 | Sangbeom Park | Smart charge-pump circuit for phase-locked loops |
| US20140320168A1 (en) * | 2013-04-25 | 2014-10-30 | Industrial Technology Research Institute | Level shifter circuit and operation method thereof |
| CN105958994A (en) * | 2016-04-25 | 2016-09-21 | 深圳大学 | Subthreshold level shifter having wide input voltage range |
| CN109713900A (en) * | 2018-12-25 | 2019-05-03 | 广东浪潮大数据研究有限公司 | A kind of electric potential transfer circuit and system low-speed backplane module |
| US10432199B1 (en) * | 2018-11-19 | 2019-10-01 | Nxp Usa, Inc. | Low power, wide range, high noise tolerance level shifter |
-
2020
- 2020-04-14 CN CN202010288907.8A patent/CN111355481A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070075755A1 (en) * | 2005-09-30 | 2007-04-05 | Sangbeom Park | Smart charge-pump circuit for phase-locked loops |
| US20140320168A1 (en) * | 2013-04-25 | 2014-10-30 | Industrial Technology Research Institute | Level shifter circuit and operation method thereof |
| CN105958994A (en) * | 2016-04-25 | 2016-09-21 | 深圳大学 | Subthreshold level shifter having wide input voltage range |
| US10432199B1 (en) * | 2018-11-19 | 2019-10-01 | Nxp Usa, Inc. | Low power, wide range, high noise tolerance level shifter |
| CN109713900A (en) * | 2018-12-25 | 2019-05-03 | 广东浪潮大数据研究有限公司 | A kind of electric potential transfer circuit and system low-speed backplane module |
Non-Patent Citations (1)
| Title |
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| SAEIDEH KABIRPOUR 等, 《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111697830A (en) * | 2020-07-08 | 2020-09-22 | 湖南国科微电子股份有限公司 | Voltage conversion circuit for converting low voltage into high voltage and voltage conversion integrated chip |
| CN111697830B (en) * | 2020-07-08 | 2021-11-12 | 湖南国科微电子股份有限公司 | Voltage conversion circuit for converting low voltage into high voltage and voltage conversion integrated chip |
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Application publication date: 20200630 |