CN111697830B - Voltage conversion circuit for converting low voltage into high voltage and voltage conversion integrated chip - Google Patents
Voltage conversion circuit for converting low voltage into high voltage and voltage conversion integrated chip Download PDFInfo
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- CN111697830B CN111697830B CN202010652635.5A CN202010652635A CN111697830B CN 111697830 B CN111697830 B CN 111697830B CN 202010652635 A CN202010652635 A CN 202010652635A CN 111697830 B CN111697830 B CN 111697830B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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Abstract
The application discloses low pressure changes high voltage conversion circuit and voltage conversion integrated chip, including electric capacity, first NMOS pipe, second NMOS pipe, first PMOS pipe, second PMOS pipe, third NMOS pipe, fourth NMOS pipe, fifth NMOS pipe, sixth NMOS pipe, seventh NMOS pipe, drive circuit. By utilizing the characteristic that the voltage of the capacitor does not suddenly change and the connection relation of the elements, the low voltage of 0-1.8V can be converted into the high voltage of 0-3.3V. In the voltage conversion circuit of the application, the voltage difference of each MOS tube does not exceed 1.8V, elements in an advanced process are applied to the voltage conversion circuit, the problem of withstand voltage is avoided, and the voltage conversion effect of converting 1.8V into 3.3V by using the MOS tube with withstand voltage of 1.8V is achieved.
Description
Technical Field
The invention relates to the field of voltage conversion circuit design, in particular to a low-voltage to high-voltage conversion circuit and a voltage conversion integrated chip.
Background
With the continuous progress of the process, the power supply voltage of the MOS transistor is lower and lower, and in some advanced processes (such as simc14nm), the power supply voltage of the I/O device has been reduced to 1.8V, but in some applications, such as USB (Universal Serial Bus), SDIO (Secure Digital Input and Output Card), EMMC (Embedded multimedia Media Card), etc., the protocol still needs to use 3.3V power supply voltage.
Therefore, how to provide a solution to the above technical problems is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides a low-voltage to high-voltage conversion circuit with low withstand voltage and a voltage conversion integrated chip. The specific scheme is as follows:
the utility model provides a low-voltage changes high voltage conversion circuit, includes electric capacity, first NMOS pipe, second NMOS pipe, first PMOS pipe, second PMOS pipe, third NMOS pipe, fourth NMOS pipe, fifth NMOS pipe, sixth NMOS pipe, seventh NMOS pipe, drive circuit, wherein:
the grid electrode of the first NMOS tube is connected with a first signal, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected with the first end of the capacitor;
the grid electrode of the second NMOS tube is connected with a second signal, the source electrode of the second NMOS tube is connected with the drain electrode of the first NMOS tube, and the drain electrode of the second NMOS tube is connected with the drain electrode of the first PMOS tube;
the grid electrode of the first PMOS tube is connected with the second signal, and the source electrode of the first PMOS tube is connected with a first voltage power supply;
the source electrode of the second PMOS tube is connected with the first voltage power supply, and the drain electrode of the second PMOS tube is connected with the second end of the capacitor;
the grid electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the third PMOS tube is connected with the grid electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is connected with the second end of the capacitor;
the grid electrode of the third NMOS tube is connected with the source electrode of the third PMOS tube, the source electrode is connected with the drain electrode of the first NMOS tube, and the drain electrode is connected with the drain electrode of the second NMOS tube;
the grid electrode and the drain electrode of the fourth NMOS tube are respectively connected with the source electrode of the third PMOS tube;
the grid electrode of the fifth NMOS tube is connected with the first voltage power supply, and the drain electrode of the fifth NMOS tube is connected with the source electrode of the fourth NMOS tube;
the grid electrode of the sixth NMOS tube is connected with the first signal, the source electrode of the sixth NMOS tube is grounded, and the drain electrode of the sixth NMOS tube is connected with the source electrode of the fifth NMOS tube;
the grid electrode of the seventh NMOS tube is connected with the grid electrode of the third NMOS tube, the source electrode of the seventh NMOS tube is connected with the first voltage power supply, and the drain electrode of the seventh NMOS tube is connected with the first end of the capacitor;
a first power supply of the driving circuit is connected with the first voltage power supply, a second power supply of the driving circuit is connected with the second voltage power supply, and a first input end and a second input end of the driving circuit are respectively connected with a first end and a second end of the capacitor;
the first voltage power supply and the second voltage power supply are respectively 1.8V and 3.3V, the first signal and the second signal are mutually opposite in phase, when the first signal is 0V, the driving circuit outputs 0V, and when the first signal is 1.8V, the driving circuit outputs 3.3V.
Preferably, the driving circuit includes a first driving PMOS transistor, a second driving PMOS transistor, a first driving NMOS transistor, and a second driving NMOS transistor, wherein:
the source electrode of the first driving PMOS tube is used as the second power supply end of the driving circuit, the grid electrode of the first driving PMOS tube is used as the second input end of the driving circuit, and the drain electrode of the first driving PMOS tube is connected with the source electrode of the second driving PMOS tube;
the source electrode of the first drive NMOS tube is grounded, the grid electrode is used as the first input end of the drive circuit, and the drain electrode is connected with the source electrode of the second drive NMOS tube;
the grid electrode of the second drive NMOS tube is connected with the grid electrode of the second drive PMOS tube and serves as a first power supply end of the drive circuit, and the drain electrode of the second drive NMOS tube is connected with the drain electrode of the second drive PMOS tube and serves as an output end of the drive circuit.
Preferably, the voltage conversion circuit further includes an inverter that converts the first signal into the second signal.
Preferably, the voltage conversion circuit further includes:
a first inverter converting an initial signal into the first signal;
a second inverter that converts the first signal to the second signal.
Preferably, the first signal and the second signal are both high-speed dynamic signals.
Preferably, the substrates of the second PMOS transistor and the third PMOS transistor are both grounded.
Correspondingly, the invention also discloses a low-voltage to high-voltage conversion integrated chip which comprises the low-voltage to high-voltage conversion circuit.
The application discloses low pressure changes high voltage conversion circuit, including electric capacity, first NMOS pipe, second NMOS pipe, first PMOS pipe, second PMOS pipe, third NMOS pipe, fourth NMOS pipe, fifth NMOS pipe, sixth NMOS pipe, seventh NMOS pipe, drive circuit. By utilizing the characteristic that the voltage of the capacitor does not suddenly change and the connection relation of the elements, the low voltage of 0-1.8V can be converted into the high voltage of 0-3.3V. In the voltage conversion circuit of the application, the voltage difference of each MOS tube does not exceed 1.8V, elements in an advanced process are applied to the voltage conversion circuit, the problem of withstand voltage is avoided, and the voltage conversion effect of converting 1.8V into 3.3V by using the MOS tube with withstand voltage of 1.8V is achieved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a circuit diagram of a voltage converting circuit for converting a low voltage into a high voltage according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a variation process of the voltage level-spreading circuit according to the embodiment of the present invention;
FIG. 3a is a signal generating circuit of an input signal according to an embodiment of the present invention;
FIG. 3b is a diagram of another signal generating circuit for an input signal according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In some applications, such as USB, SDIO, EMMC, etc., the protocol still requires a 3.3V voltage supply. However, there are no 3.3V tolerant devices in advanced processes. The voltage conversion scheme of converting 1.8V into 3.3V is realized through the MOS tube with the voltage resistance of 1.8V.
The embodiment of the invention discloses a voltage conversion circuit for converting low voltage into high voltage, which comprises a capacitor Cc, a first NMOS tube MN1, a second NMOS tube MN2, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7 and a driving circuit Dr-C, wherein the voltage conversion circuit comprises a first NMOS tube MN1, a second NMOS tube MN2, a third PMOS tube MP3, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7 and a driving circuit Dr-C, wherein:
the grid electrode of the first NMOS pipe MN1 is connected with a first signal in-a, the source electrode is grounded, and the drain electrode is connected with the first end of the capacitor Cc;
the grid electrode of the second NMOS transistor MN2 is connected with a second signal in-b, the source electrode is connected with the drain electrode of the first NMOS transistor MN1, and the drain electrode is connected with the drain electrode of the first PMOS transistor MP 1;
the grid electrode of the first PMOS pipe MP1 is connected with the second signal in-b, and the source electrode is connected with a first voltage power supply VDD 18;
the source electrode of the second PMOS tube MP2 is connected with the first voltage power supply VDD18, and the drain electrode is connected with the second end of the capacitor Cc;
the grid electrode of the third PMOS tube MP3 is connected with the drain electrode of the second NMOS tube MN2, the source electrode is connected with the grid electrode of the second PMOS tube MP2, and the drain electrode is connected with the second end of the capacitor Cc;
the grid electrode of the third NMOS transistor MN3 is connected with the source electrode of the third PMOS transistor MP3, the source electrode is connected with the drain electrode of the first NMOS transistor MN1, and the drain electrode is connected with the drain electrode of the second NMOS transistor MN 2;
the grid and the drain of the fourth NMOS transistor MN4 are respectively connected with the source of the third PMOS transistor MP 3;
the grid electrode of the fifth NMOS transistor MN5 is connected with a first voltage power supply VDD18, and the drain electrode of the fifth NMOS transistor MN4 is connected with the source electrode of the fourth NMOS transistor MN 4;
the grid electrode of the sixth NMOS tube MN6 is connected with the first signal in-a, the source electrode is grounded, and the drain electrode is connected with the source electrode of the fifth NMOS tube MN 5;
the grid electrode of the seventh NMOS transistor MN7 is connected with the grid electrode of the third NMOS transistor MN8, the source electrode is connected with a first voltage power supply VDD18, and the drain electrode is connected with the first end of the capacitor Cc;
the first power supply of the driving circuit Dr-C is connected with a first voltage power supply VDD18, the second power supply is connected with a second voltage power supply VDD33, and a first input end A and a second input end B are respectively connected with a first end and a second end of a capacitor Cc;
the first voltage source VDD18 and the second voltage source VDD33 are 1.8V and 3.3V, respectively, the first signal in-a and the second signal in-b are opposite in phase, when the first signal in-a is 0V, the driving circuit Dr-C outputs 0V, and when the first signal in-a is 1.8V, the driving circuit Dr-C outputs 3.3V.
Specifically, the driving circuit Dr-C includes a first driving PMOS transistor MP-d1, a second driving PMOS transistor MP-d2, a first driving NMOS transistor MN-d1, and a second driving NMOS transistor MN-d2, wherein:
the source electrode of the first driving PMOS transistor MP-d1 is used as a second power supply end of the driving circuit Dr-C, the grid electrode is used as a second input end B of the driving circuit Dr-C, and the drain electrode is connected with the source electrode of the second driving PMOS transistor MP-d 2;
the source electrode of the first drive NMOS transistor MN-d1 is grounded, the grid electrode is used as a first input end A of the drive circuit Dr-C, and the drain electrode is connected with the source electrode of the second drive NMOS transistor MN-d 2;
the grid electrode of the second drive NMOS transistor MN-d2 is connected with the grid electrode of the second drive PMOS transistor MP-d2 and serves as a first power supply end of the drive circuit Dr-C, and the drain electrode of the second drive NMOS transistor MN-d2 is connected with the drain electrode of the second drive PMOS transistor MP-d2 and serves as an output end of the drive circuit Dr-C.
In general, to avoid leakage, the substrates of the second PMOS transistor MP2 and the third PMOS transistor MP3 are both grounded.
Specifically, under different levels of the input signal, states of the MOS transistors in the circuit are different, which is specifically as follows:
when the first signal in-a is 1.8V and the second signal in-b with the opposite phase is 0V, the first NMOS transistor MN1 is closed, and the voltage at the first terminal a of the capacitor Cc in fig. 1 is pulled to 0V; the first PMOS tube PM1 and the second NMOS tube MN2 form an inverter with an input signal of a second signal in-b, so that the voltage at the point C in the figure 1 is opposite to the voltage of the second signal in-b, namely the first PMOS tube MP1 is closed at the moment, and the voltage at the point C is 1.8V; the sixth NMOS transistor MN6 is closed; the fifth NMOS transistor MN5 is turned on, the fourth NMOS transistor MN4 is turned on all the time without being interfered by an external input signal, at this time, the voltage at the point D in fig. 1 is Vthn, the second PMOS transistor MP2 is turned on, the third PMOS transistor MP3 is turned off, the potential at the point B of the second end of the capacitor Cc is 1.8V, and simultaneously, the third NMOS transistor MN3 and the seventh NMOS transistor MN7 are both turned off.
When the first signal in-a jumps from 1.8V to 0V, the second signal in-B jumps to 1.8V, the voltage at the point A is temporarily kept at 0V and the voltage at the point B is temporarily kept at 1.8V because the voltage of the capacitor Cc cannot jump suddenly; at this time, the first NMOS transistor MN1 and the sixth NMOS transistor MN6 are both turned off, the second NMOS transistor MN2 is turned on, the first PMOS transistor MP1 is turned off, and at an instant, the voltage of the point D is changed from 1.8V to 0V at the point a, the third PMOS transistor MP3 is instantly turned on, the voltage of the point D is instantly pulled to 1.8V at the point B, the second PMOS transistor MP2 is turned off, the third NMOS transistor MN3 and the seventh NMOS transistor MN7 are both turned on, the voltage at the point a is instantly charged to 1.8V, the voltage at the point C returns to 1.8V, and the voltages at the points B and D are obtained by adding the voltage at the point a and the voltage of the capacitor Cc to 3.6V.
Specifically, in the driving circuit Dr-C, when the first signal in-a is 1.8V, the voltage at the point a is 0V, and the voltage at the point B is 1.8V, both the first driving PMOS transistor MP-d1 and the second driving PMOS transistor MP-d2 are turned on, and the output OUT is 3.3V; when the first signal in-a is 0V, the voltage at the point A is 1.8V, the voltage at the point B is 3.6V, the first driving NMOS transistor MN-d1 and the second driving NMOS transistor MN-d2 are both turned on, and the output OUT is 0V.
The process of all the above potential changes can be seen in fig. 2.
The problem of withstand voltage in the above case is discussed below:
when the first signal in-a is 1.8V, the voltages of the point A, the point B, the point C and the point D are respectively 0V, 1.8V and 0V, the voltages of all MOS tubes in the circuit do not exceed 1.8V, and the withstand voltage of 1.8V can be met;
when the first signal in-a jumps from 1.8V to 0V, the voltage changes at points a and B, and C and D are respectively 0V-1.8V and 1.8V-3.6V, 1.8V-0V-1.8V, and 0V-3.6V, and there are points B, D and E in the circuit of fig. 1 being 3.6V, the discussion will be separately applied to the relevant MOS transistors:
second PMOS transistor MP 2: the grid electrode is 3.6V, the drain electrode is 3.6V, the source electrode is 1.8V, and the problem of 1.8V withstand voltage is solved;
third PMOS transistor MP 3: the grid electrode is 1.8V, the drain electrode is 3.6V, the source electrode is 1.8V, and the problem of 1.8V withstand voltage is solved;
third NMOS transistor MN 3: the grid electrode is 3.6V, the drain electrode is 1.8+ VTHP, the source electrode is 3.3V, and the problem of 1.8V withstand voltage is solved;
fourth NMOS transistor MN 4: the grid electrode is 3.6V, the drain electrode is 3.6V, the source electrode is 3.6-VTHN, and the problem of 1.8V withstand voltage is solved;
fifth NMOS transistor MN 5: the grid electrode 1.8V drain electrode 3.6-VTHN source electrode 1.8-VTTHN, and the problem of 1.8V withstand voltage does not exist.
In summary, the voltage conversion circuit in the embodiment of the present application can use the MOS transistor with withstand voltage of 1.8V to convert 0-1.8V to 0-3.3V.
It will be appreciated that since the first signal in-a and the second signal in-b are inverted with respect to each other, an inverter may be provided to generate the input signal, i.e. referring to fig. 3a, the voltage conversion circuit may further comprise an inverter inv0 for converting the first signal in-a into the second signal in-b. As further shown in fig. 3b, the voltage converting circuit may further include: a first inverter inv1 converting the initial signal in-0 into a first signal in-a; a second inverter inv2 which converts the first signal in-a into a second signal in-b. In fact, in the second scheme, the initial signal in-0 can be directly used as the second signal in-b.
It will be appreciated that the first signal in-a and the second signal in-b are both high speed dynamic signals.
Since the voltage between the two plates of the capacitor Cc does not suddenly change, the point a and the point B change very rapidly, so that the present embodiment can be applied in a very high speed environment. It should be noted that, in the present embodiment, the voltage converting circuit has no quiescent current, and consumes current only when operating, and the circuit must have a capacitor charging/discharging process when operating, so the circuit is not suitable for quiescent applications.
The application discloses low pressure changes high voltage conversion circuit, including electric capacity, first NMOS pipe, second NMOS pipe, first PMOS pipe, second PMOS pipe, third NMOS pipe, fourth NMOS pipe, fifth NMOS pipe, sixth NMOS pipe, seventh NMOS pipe, drive circuit. By utilizing the characteristic that the voltage of the capacitor does not suddenly change and the connection relation of the elements, the low voltage of 0-1.8V can be converted into the high voltage of 0-3.3V. In the voltage conversion circuit of the application, the voltage difference of each MOS tube does not exceed 1.8V, elements in an advanced process are applied to the voltage conversion circuit, the problem of withstand voltage is avoided, and the voltage conversion effect of converting 1.8V into 3.3V by using the MOS tube with withstand voltage of 1.8V is achieved.
Correspondingly, the embodiment of the invention also discloses a low-voltage to high-voltage conversion integrated chip which comprises the low-voltage to high-voltage conversion circuit.
For details of the voltage conversion circuit from low voltage to high voltage, reference may be made to the corresponding description in the above embodiments, which is not repeated herein.
The present embodiment has the same beneficial effects as the voltage converting circuit in the above embodiments, and the description thereof is omitted.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The voltage conversion circuit and the voltage conversion integrated chip for converting low voltage into high voltage provided by the invention are described in detail, a specific example is applied in the text to explain the principle and the implementation mode of the invention, and the description of the above embodiment is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (6)
1. The utility model provides a low-voltage changes high voltage's voltage conversion circuit, its characterized in that includes electric capacity, first NMOS pipe, second NMOS pipe, first PMOS pipe, second PMOS pipe, third NMOS pipe, fourth NMOS pipe, fifth NMOS pipe, sixth NMOS pipe, seventh NMOS pipe, drive circuit, wherein:
the grid electrode of the first NMOS tube is connected with a first signal, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected with the first end of the capacitor;
the grid electrode of the second NMOS tube is connected with a second signal, the source electrode of the second NMOS tube is connected with the drain electrode of the first NMOS tube, and the drain electrode of the second NMOS tube is connected with the drain electrode of the first PMOS tube;
the grid electrode of the first PMOS tube is connected with the second signal, and the source electrode of the first PMOS tube is connected with a first voltage power supply;
the source electrode of the second PMOS tube is connected with the first voltage power supply, and the drain electrode of the second PMOS tube is connected with the second end of the capacitor;
the grid electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the third PMOS tube is connected with the grid electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is connected with the second end of the capacitor;
the grid electrode of the third NMOS tube is connected with the source electrode of the third PMOS tube, the source electrode is connected with the drain electrode of the first NMOS tube, and the drain electrode is connected with the drain electrode of the second NMOS tube;
the grid electrode and the drain electrode of the fourth NMOS tube are respectively connected with the source electrode of the third PMOS tube;
the grid electrode of the fifth NMOS tube is connected with the first voltage power supply, and the drain electrode of the fifth NMOS tube is connected with the source electrode of the fourth NMOS tube;
the grid electrode of the sixth NMOS tube is connected with the first signal, the source electrode of the sixth NMOS tube is grounded, and the drain electrode of the sixth NMOS tube is connected with the source electrode of the fifth NMOS tube;
the grid electrode of the seventh NMOS tube is connected with the grid electrode of the third NMOS tube, the source electrode of the seventh NMOS tube is connected with the first voltage power supply, and the drain electrode of the seventh NMOS tube is connected with the first end of the capacitor;
a first power supply of the driving circuit is connected with the first voltage power supply, a second power supply of the driving circuit is connected with the second voltage power supply, and a first input end and a second input end of the driving circuit are respectively connected with a first end and a second end of the capacitor;
the first voltage power supply and the second voltage power supply are respectively 1.8V and 3.3V, the first signal and the second signal are mutually opposite in phase, when the first signal is 0V, the driving circuit outputs 0V, and when the first signal is 1.8V, the driving circuit outputs 3.3V;
the drive circuit comprises a first drive PMOS tube, a second drive PMOS tube, a first drive NMOS tube and a second drive NMOS tube, wherein:
the source electrode of the first driving PMOS tube is used as the second power supply end of the driving circuit, the grid electrode of the first driving PMOS tube is used as the second input end of the driving circuit, and the drain electrode of the first driving PMOS tube is connected with the source electrode of the second driving PMOS tube;
the source electrode of the first drive NMOS tube is grounded, the grid electrode is used as the first input end of the drive circuit, and the drain electrode is connected with the source electrode of the second drive NMOS tube;
the grid electrode of the second drive NMOS tube is connected with the grid electrode of the second drive PMOS tube and serves as a first power supply end of the drive circuit, and the drain electrode of the second drive NMOS tube is connected with the drain electrode of the second drive PMOS tube and serves as an output end of the drive circuit.
2. The voltage conversion circuit of claim 1, further comprising an inverter that converts the first signal to the second signal.
3. The voltage conversion circuit of claim 1, further comprising:
a first inverter converting an initial signal into the first signal;
a second inverter that converts the first signal to the second signal.
4. The voltage conversion circuit according to any one of claims 1 to 3,
the first signal and the second signal are both high-speed dynamic signals.
5. The voltage conversion circuit of claim 4,
and the substrates of the second PMOS tube and the third PMOS tube are both grounded.
6. A low-to-high voltage conversion integrated chip, comprising the low-to-high voltage conversion circuit of any one of claims 1 to 5.
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