CN210780723U

CN210780723U - Circuit for stably driving grid voltage of tube based on buzzer

Info

Publication number: CN210780723U
Application number: CN201921388861.6U
Authority: CN
Inventors: 张怀东
Original assignee: Wuxi Shiding Electronic Technology Co ltd
Current assignee: Wuxi Shiding Electronic Technology Co ltd
Priority date: 2019-08-26
Filing date: 2019-08-26
Publication date: 2020-06-16
Anticipated expiration: 2029-08-26

Abstract

The utility model provides a circuit based on buzzer stable drive tube grid voltage, including logic control circuit, diode D1, PMOS pipe MP1, PMOS pipe MP2, NMOS pipe MN 1. The grid of the NMOS driving tube of the buzzer is G, the input F of the logic control circuit is a frequency signal, the output P1 of the logic control circuit is connected to the grid of the MP1, the output P2 of the logic control circuit is connected to the grid of the MP2, the output N1 of the logic control circuit is connected to the grid of the MN1, the anode of the diode D1 is connected to a power line, the cathode of the diode D1 is connected to the substrates of the MP1 and the MP2, the source of the MP1 is connected to the power line, the drain of the MP1 is connected to G, the drain of the MP2 is connected to P1, the source of the MP2 is connected to G, the source of the MN1 is connected to the ground line. The utility model discloses a control MP1, MP2, the grid of the three MOS pipe of MN1 to and combine diode D1 to play the effect that prevents buzzer NMOS drive tube grid voltage decline jointly.

Description

Circuit for stably driving grid voltage of tube based on buzzer

Technical Field

The utility model relates to a buzzer circuit field, concretely relates to circuit based on grid voltage of buzzer stable drive tube.

Background

As shown in fig. 4, in the conventional gate driving circuit of the buzzer driving tube, when the voltage of the power line drops, the gate voltage of the buzzer driving tube drops along with the voltage of the power line, so that the driving capability of the buzzer driving tube is insufficient, and even the output frequency of the buzzer is unstable.

SUMMERY OF THE UTILITY MODEL

The utility model provides a circuit based on buzzer stable drive tube grid voltage when power line voltage descends to the grid voltage who solves the buzzer drive tube follows the problem that power line voltage descends together, and when preventing that power line voltage from descending, the driving force of buzzer drive tube is not enough, can arouse buzzer output frequency's unstability even.

In order to solve the technical problem, the utility model provides a circuit based on buzzer stable drive tube grid voltage, including logic control circuit, diode D1, PMOS pipe MP1, PMOS pipe MP2, NMOS pipe MN 1. The input F of the logic control circuit is a frequency signal, the output P1 of the logic control circuit is connected to the grid of a PMOS tube MP1, the output P2 of the logic control circuit is connected to the grid of a PMOS tube MP2, the output N1 of the logic control circuit is connected to the grid of an NMOS tube MN1, the anode of a diode D1 is connected to a power line, the cathode of a diode D1 is connected to the substrates of the PMOS tube MP1 and the PMOS tube MP2, the source of the PMOS tube MP1 is connected to the power line, the drain of the PMOS tube MP1 is connected to the grid G of a buzzer NMOS drive tube, the drain of the PMOS tube MP2 is connected to the grid of a PMOS tube MP1, the source of the PMOS tube MP2 is connected to the grid G of the buzzer NMOS drive tube, the source of the NMOS tube MN1 is connected to the ground line, and the drain of the NMOS tube MN 1.

Preferably, there is at least one diode.

Preferably, the source terminal and the drain terminal of the MOS transistors MP1, MP2 and MN1 are reversed.

The utility model discloses the beneficial effect who brings: the utility model provides a pair of circuit based on buzzer stable drive tube grid voltage through the grid of logic control circuit control MP1, MP2, the three MOS pipe of MN1 to and combine diode D1 to play the effect that prevents buzzer NMOS drive tube grid voltage from following mains voltage and descend together jointly, have the operating voltage low, advantage with low costs when normal use.

Drawings

Fig. 1 is a schematic structural diagram of the circuit for stabilizing the gate voltage of the driving tube based on the buzzer of the present invention.

Fig. 2 is a schematic diagram of a circuit timing sequence based on a buzzer stabilized driving tube gate voltage according to the first embodiment of the present invention.

Fig. 3 is a schematic diagram of a circuit timing sequence for stabilizing the gate voltage of the driving tube based on the buzzer according to the second embodiment of the present invention.

Fig. 4 is a schematic diagram of the background art.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.

As shown in fig. 1, the utility model provides a circuit based on stable drive tube grid voltage of bee calling organ, including logic control circuit, diode D1, PMOS pipe MP1, PMOS pipe MP2, NMOS pipe MN 1. The input F of the logic control circuit is a frequency signal, the output P1 of the logic control circuit is connected to the grid of a PMOS tube MP1, the output P2 of the logic control circuit is connected to the grid of a PMOS tube MP2, the output N1 of the logic control circuit is connected to the grid of an NMOS tube MN1, the anode of a diode D1 is connected to a power line, the cathode of a diode D1 is connected to the substrates of the PMOS tube MP1 and the PMOS tube MP2, the source of the PMOS tube MP1 is connected to the power line, the drain of the PMOS tube MP1 is connected to the grid G of a buzzer NMOS drive tube, the drain of the PMOS tube MP2 is connected to the grid of a PMOS tube MP1, the source of the PMOS tube MP2 is connected to the grid G of the buzzer NMOS drive tube, the source of the NMOS tube MN1 is connected to the ground line, and the drain of the NMOS tube MN 1.

The utility model discloses a first embodiment: as shown in fig. 2, with reference to fig. 1, F is a frequency signal generated inside the chip, when the level of F changes to turn on the buzzer NMOS driving transistor, i.e. the starting time of t1, the outputs P1 and N1 of the logic control circuit change from high level to low level, the output P2 of the logic control circuit is high level, the circuit charges the gate G of the buzzer NMOS driving transistor through the PMOS transistor MP1 by the power supply, the voltage of the gate G of the buzzer NMOS driving transistor rises, the buzzer NMOS driving transistor is turned on, at the ending time of t1, i.e. the starting time of t2, the output P1 port of the logic control circuit is in high-impedance state, as shown by the dashed line of the P1 signal line in fig. 2, the dashed line of the P1 represents that the P1 port of the logic control circuit is in high-impedance state, at the ending time of t2, the output P2 of the logic control circuit changes from high level to low level, because the gate capacitance of the buzzer NMOS driving transistor 1 is much larger than the gate capacitance of the PMOS transistor MP 36, therefore, the grid electrode capacitor of the NMOS driving tube of the buzzer charges the grid electrode of the PMOS tube MP1 through the PMOS tube MP2, the P1 is charged to a high level, when the power voltage drops below the grid electrode voltage of the NMOS driving tube of the buzzer, the output P1 port of the logic control circuit is in a high-resistance state because the PMOS tube MP1 and the NMOS tube MN1 are cut off, and the substrates of the PMOS tube MP1 and the PMOS tube MP2 are connected to a power line through the reverse bias diode D1, so that the grid electrode voltage of the NMOS driving tube of the buzzer cannot drop along with the power voltage.

The utility model discloses a second embodiment: as shown in fig. 3, with reference to fig. 1, F is a frequency signal generated inside the chip, when the level F changes to turn on the buzzer NMOS driving transistor, i.e. the starting time of t1, the outputs P1 and N1 of the logic control circuit change from high level to low level, the output P2 of the logic control circuit is high level, the circuit charges the gate G of the buzzer NMOS driving transistor through the PMOS transistor MP1, the voltage of the gate G of the buzzer NMOS driving transistor rises, the buzzer NMOS driving transistor is turned on, at the end time of t1, the output P1 port of the logic control circuit is in high impedance state, as shown by the dashed line P1 in fig. 2, the dashed line P1 represents that the output P1 port of the logic control circuit is in high impedance state, the output P2 of the logic control circuit changes from high level to low level, because the gate capacitance of the buzzer NMOS driving transistor is much larger than the gate capacitance of the PMOS transistor MP1, therefore, the grid electrode capacitor of the NMOS driving tube of the buzzer charges the grid electrode of the PMOS tube MP1 through the PMOS tube MP2, the P1 is charged to a high level, when the power voltage drops below the grid electrode voltage of the NMOS driving tube of the buzzer, the output P1 port of the logic control circuit is in a high-resistance state because the PMOS tube MP1 and the NMOS tube MN1 are cut off, and the substrates of the PMOS tube MP1 and the PMOS tube MP2 are connected to a power line through the reverse bias diode D1, so that the grid electrode voltage of the NMOS driving tube of the buzzer cannot drop along with the power voltage.

To sum up, the utility model provides a pair of circuit based on buzzer stable drive tube grid voltage through the grid of the three MOS pipe of logic control circuit control MP1, MP2, MN1 to and combine diode D1 to play the effect that prevents that buzzer NMOS drive tube grid voltage from following mains voltage and descend together, have the operating voltage low, advantage with low costs.

The above description is only an example of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A circuit for stabilizing the grid voltage of a driving tube based on a buzzer comprises a logic control circuit, a diode D1, a PMOS tube MP1, a PMOS tube MP2 and an NMOS tube MN1, the input F of the logic control circuit is a frequency signal, the output P1 of the logic control circuit is connected to the grid of a PMOS tube MP1, the output P2 of the logic control circuit is connected to the grid of a PMOS tube MP2, the output N1 of the logic control circuit is connected to the grid of an NMOS tube MN1, the anode of a diode D1 is connected to a power line, the cathode of a diode D1 is connected to the substrates of the PMOS tube MP1 and the PMOS tube MP2, the source of the PMOS tube MP1 is connected to the power line, the drain of the PMOS tube MP1 is connected to the grid G of a buzzer NMOS drive tube, the drain of the PMOS tube MP2 is connected to the grid of a PMOS tube MP1, the source of the PMOS tube MP2 is connected to the grid G of the buzzer NMOS drive tube, the source of the NMOS tube MN1 is connected to the ground line, and the drain of the NMOS tube MN 1.

2. The buzzer-based stable driving tube gate voltage circuit as claimed in claim 1, wherein said number of diodes D1 is at least one.

3. The buzzer-based circuit for stabilizing the grid voltage of the driving tube according to claim 1, wherein the source end and drain end switching positions of the MOS tubes MP1, MP2 and MN1 do not influence the normal operation of the circuit.