CN102709883A - Under-voltage protection circuit of switch power source - Google Patents

Abstract

The invention discloses an under-voltage protection circuit of a switch power source. The under-voltage protection circuit is characterized by comprising a self-starting bias current source, a sampling circuit, a comparator, an amplifier, a waveshaping circuit and a feedback circuit, wherein the output of the self-starting bias current source is connected with the input end of the sampling circuit; the output end of the sampling circuit is connected with the input end of the comparator; the output end of the comparator is connected with the input end of the amplifier; the output end of the amplifier is connected with the input end of the waveshaping circuit; in the output of the waveshaping circuit, one channel is connected with the sampling circuit through the feedback circuit, while the other channel is connected with the protected switch power source; and the self-starting bias current source and the sampling circuit are one circuit module.

Description

A kind of under-voltage protecting circuit of Switching Power Supply

Technical field

The present invention relates to the Switching Power Supply of analog integrated circuit, relate in particular to a kind of under-voltage protecting circuit of Switching Power Supply, be applicable to the startup protection in the various power management chips.

Background technology

The quality index of estimating Switching Power Supply should be to be first principle with fail safe, reliability.Switching Power Supply not only will be worked under the electrical apparatus technology index satisfies the condition of the normal instructions for use of equipment; Also will satisfy also can be safe and reliable under the condition that extraneous, self circuit or load circuit break down work; When supply voltage is lower than the normal range of operation of chip; Some circuit of chip internal can operate as normal, and produces the internal logic mistake, thereby makes the external switch pipe be in nondeterministic statement; Might cause damage to external circuit and chip, therefore must the design under-voltage protecting circuit.Under-voltage protection can improve chip reliability, fail safe, through chip input voltage is detected, when input supply voltage is too small, can chip be turn-offed, chip is not worked, and remains on safe condition.Present under-voltage protecting circuit both domestic and external is divided into two kinds, and a kind of is the under-voltage protecting circuit of external reference voltage, and a kind of is the under-voltage latch cicuit of self-starting.Fig. 1 has provided a kind of under-voltage latch cicuit of power management adhesive integrated circuit; Comprising power supply bleeder circuit, comparator, be used to provide the reference voltage source of band-gap reference reference voltage and the logical circuit of forming by some logical devices; The input termination supply voltage of power supply bleeder circuit; The positive input of power supply bleeder circuit output termination comparator; The reverse input end of the output termination comparator of reference voltage source, the input of the output termination logical circuit of comparator, the under-voltage voltage signal that latchs of output output of logical circuit.This under-voltage latch cicuit mainly is made up of comparator and reference voltage source, and employed components and parts are more, area occupied is big and the response time is slower.

201010508409.6 " the under-voltage latch cicuit that has the band-gap reference structure " proposes a kind of is the under-voltage latch cicuit of core with voltage divider, band-gap reference circuit, comparator and logical circuit; Its basic thought is that the output of band-gap reference comparator constitutes the control output end of under-voltage latch cicuit after the logical circuit shaping with the comparative voltage input of the supply voltage input band gap reference comparator of voltage divider sampling; Be provided with feedback control loop between logical circuit and voltage divider.The deficiency that the under-voltage latch cicuit of this application exists is: it is less that it exports the under-voltage latch signal amplitude of oscillation; Be unfavorable for driving more load; Band-gap reference comparator works instability causes output that the mistake upset takes place easily when supply voltage is low, and can not use CMOS technology to realize.

Summary of the invention

To the deficiency that prior art exists, the present invention proposes a kind of under-voltage protecting circuit of Switching Power Supply, latch based on self-starting is under-voltage; Have very fast response speed and under-voltage latch function, adopted to prevent the mistake reverse circuit, improved the stability of output; Circuit structure is simple and clear, has less power consumption, can be integrated in inside circuit and realize; And can reach the effect of the whole power supply chip of protection startup stage of comprising in all time periods.

For realizing above-mentioned purpose, adopt following technical scheme: a kind of under-voltage protecting circuit of Switching Power Supply is characterized in that; Comprise self-starting bias current sources, sample circuit, comparator, amplifier, shaping circuit and feedback circuit; The output of self-starting bias current sources connects the input of sample circuit, and the output of sample circuit connects the input of comparator, and the output of comparator connects amplifier input terminal; The output of amplifier connects the input of shaping circuit; In the output of shaping circuit, the one tunnel connects sample circuit behind feedback circuit, and another road connects protected Switching Power Supply; Wherein, self-starting bias current sources and sample circuit are a circuit module;

Self-starting bias current sources and sample circuit comprise three resistance R 1, R2 and R3, NMOS pipe M4 and a PNP triode; Resistance R 1, R2 and R3 connect successively; Another termination power vd D of resistance R 1; The other end of resistance R 3 connects grid and the drain electrode of NMOS pipe M4, and the source electrode of NMOS pipe M4 connects the emitter of PNP triode, the collector electrode of PNP triode and base earth;

Comparator comprises two PMOS pipe M5 and M6, three NMOS pipes M7, M8 and M9; The grid of NMOS pipe M7 connects being connected in series a little of resistance R 2 and R3 in self-starting bias current sources and the sample circuit; The drain electrode of the source electrode of the source electrode of NMOS pipe M7, NMOS pipe M8 and NMOS pipe M9 links together; The grid of NMOS pipe M9 connects the source electrode of NMOS pipe M4 in self-starting bias current sources and the sample circuit; The source ground of NMOS pipe M9; The grid of NMOS pipe M8 connects being connected in series a little of resistance R 3 and NMOS pipe M4 grid in self-starting bias current sources and the sample circuit, the drain electrode of NMOS pipe M7 and NMOS pipe M8 drain electrode connect the drain electrode of NMOS pipe M5 and NMOS pipe M6 respectively, the drain electrode that grid that the grid of NMOS pipe M5, NMOS manage M6 and NMOS manage M6 links together; The source electrode of NMOS pipe M5 and NMOS pipe M6 source electrode all meet power vd D, the source electrode of NMOS pipe M6 with drain between be connected capacitor C 2;

Amplifier comprises PMOS pipe M1 and NMOS pipe M2; The source electrode of PMOS pipe M1 meets power vd D; The grid of PMOS pipe M1 connects the drain electrode of NMOS pipe M7 in the comparator, and the drain electrode of PMOS pipe M1 connects the drain electrode of NMOS pipe M2, and the grid of NMOS pipe M2 connects the source electrode of NMOS pipe M4 in self-starting bias current sources and the sample circuit; The source ground of NMOS pipe M2, the source electrode of NMOS pipe M2 with drain between be connected capacitor C 1;

Shaping circuit comprises three inverter INV1, inverter INV2 and the inverter INV3 of serial connection successively; Inverter INV1 input connects the drain electrode of PMOS pipe M1 in the amplifier, and inverter INV2 is connected to protected Switching Power Supply with the point that is connected in series between the inverter INV3;

Feedback circuit is provided with a PMOS pipe M3; The grid of PMOS pipe M3 connects the output of inverter INV3 in the shaping circuit; The source electrode of PMOS pipe M3 meets power vd D, and the drain electrode of PMOS pipe M3 connects being connected in series a little of resistance R 1 and R2 in self-starting bias current sources and the sample circuit.

Advantage of the present invention and remarkable result:

1) circuit of the present invention just can be realized under CMOS technology, to technology require lowly, be widely used.

2) current offset and sample circuit unite two into one in the circuit of the present invention, have simplified the structure of circuit, have reduced the power consumption of whole under-voltage latch cicuit.

3) increase the design of hysteresis circuitry in the circuit of the present invention, can prevent the mistake upset of under-voltage latch cicuit.

What 4) current mirror in the comparator of the present invention used is the current mirror of unsymmetric structure, can make the variation of output voltage bigger like this, makes output voltage accelerate to the response speed of input voltage.

Description of drawings

Fig. 1 is the theory diagram of a kind of under-voltage protecting circuit of prior art;

Fig. 2 is a theory diagram of the present invention;

Fig. 3 is a kind of concrete realization circuit diagram of the present invention.

Embodiment

Referring to Fig. 2, protective circuit of the present invention comprises self-starting bias current sources, sample circuit, comparator, amplifier, shaping circuit and feedback circuit, and wherein bias current sources and sample circuit are that a modular circuit realizes simultaneously.Sample circuit output sampled voltage (comprising two sampled voltages) is sent to comparator and compares; The output of comparator is received amplifier signal is amplified; The signal that amplification is come out is received one group of inverter and is carried out shaping; Wherein one road voltage of shaping output is through a feedback switch management and control system sampled voltage, and V is exported in other one tunnel shaping _OutConnect the port that the DC-DC converter enables; Another input EN1 that enables is the artificial enable signal of opening, and when having only EN1 and under-voltage protecting circuit to enable simultaneously for " 1 ", enables EN just to open; The core circuit of DC-DC converter is just started working, and reaches the under-voltage protection purpose.

Fig. 3 is the physical circuit of Fig. 2.In self-starting bias current sources and the sample circuit 1; Resistance R 1, R2 and R3 connect successively, the last termination power vd D of R1, and the lower end of R3 connects grid and the drain electrode of NMOS pipe M4; The source electrode of NMOS pipe M4 connects the emitter of PNP triode, the collector electrode of PNP triode and base earth.Resistance R 2 and R3 are connected in series o'clock as first sampled voltage, and the grid of M4 and the tie point of R3 are as second sampled voltage.The input of self-starting bias current sources and sample circuit is the circuit power signal, and the PNP triode of resistance R 1 ~ R3 and diode type of attachment and NMOS pipe M4 form the biasing circuit of self-starting, tail current are provided for comparator and amplifier.

Comparator 3 adopts asymmetrical current mirror structure; PMOS pipe M5, M6 and NMOS pipe M7, M8, M9 constitute differential amplifier; M5, M6 are current mirror load, and the drain electrode of M7 is as the output voltage of comparator, and M9 is that comparator provides tail current; The grid of M9 is received the emitter of PNP triode, for M9 provides tail current.Pressure stabilization function is played at leakage, the two poles of the earth, source that capacitor C 2 connects M6.

Resistance R in self-starting bias current sources and the sample circuit about in the of 3 two ends respectively as the reverse input end and the positive input of comparator.When mains voltage variations, resistance R 3 upper and lower side pressure reduction can be followed variation, cause the comparator output switching activity, characterize supply voltage and satisfy the system works condition, and system enables to open.

The input signal of under-voltage protection (latching) circuit is a supply voltage; Whether output characterization supply voltage satisfies condition of work: when supply voltage rises from the electronegative potential to the high potential; Output " 1 " signal when being higher than xV (the forward turnover voltage of x) for setting, otherwise be " 0 "; When supply voltage descends from the high potential to the electronegative potential, output " 0 " signal when being lower than yV (the reverse flip voltage of y) for setting, otherwise be " 1 ".

Through series resistance R1 ~ R3 in self-starting bias current sources and the sample circuit and NMOS pipe a M4 and a PNP triode that is connected with diode who is connected with diode, the electric current of the resistance R of flowing through 3 is:

$I_1=\frac{V_{\mathrm{dd}}-V_{\mathrm{GS}}-V_{\mathrm{BE}}}{R_1+{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HDA00001628474700013.png"\; state="\{\{state\}\}">R</figure-callout>}}_2+{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="HDA00001628474700013.png"\; state="\{\{state\}\}">R</figure-callout>}}_3}$

V wherein _GSBe leakage, the source electrode pressure drop of M4, V _BEFor the collector emitter pressure drop of PNP triode, for electric current I ₁When less range, V _GSAnd V _BEChange slower, i.e. the lower end of resistance R 3, just the positive input of comparator is slower with mains voltage variations; I ₁Along with the rising of supply voltage increases, the pressure reduction up and down of R3 satisfies:

V _R3=I ₁×R ₃

R3 is constant, I ₁Along with the rising of supply voltage increases; Can know so along with supply voltage raises gradually; The pressure reduction up and down of R3 will increase; The voltage at resistance R 3 two ends is input to the two ends of comparator as first, second sampled voltage, and the pressure reduction up and down of R3 has determined to constitute the output signal of the differential amplifier of comparator.Since the differential amplifier input end signal all the time V-greater than V+; The output signal changes slower; Therefore the load of design current mirror is asymmetric, can realize that like this output voltage changes greatly, when the voltage difference at R3 two ends arrives certain voltage value greatly; Output voltage overturns, thereby this asymmetric comparator can be so that the variation of output voltage makes output voltage accelerate to the response of input voltage greatly.

PMOS pipe M1 in the amplifier 4 and NMOS pipe M2 constitute the common-source amplifier that has active load; M1 is an amplifier tube; The grid of M1 connects the output voltage (drain electrode of M7) of comparator; Comparator output signal is amplified, and the grid of active load M2 provides tail current as stable bias voltage by the emitter of PNP triode, and pressure stabilization function is played at leakage, the two poles of the earth, source that capacitor C 1 connects M2.The drain electrode of M1 is the output of amplifier 4, is connected to as the inverter INV1 input in the shaping circuit 5, and after inverter INV1 and INV2 shaping, the output signal V of inverter INV2 _OutBe connected to protected Switching Power Supply, V _OutOutput signal V behind inverter INV3 _rThe PMOS switching tube M3 grid that connects feedback circuit 6; Unlatching, the shutoff of control switch pipe M3; And then the resistance R in self-starting bias current sources and the sample circuit 1 controlled, realize the lag function of comparator, can prevent the mistake upset of under-voltage protection (latching) circuit.Its key is, because switching tube M3 is by output voltage V _rControl, when voltage from low toward High variation, when being lower than the forward turnover voltage, V _rSignal is 1, and M3 closes, and resistance R 1 is switched on, at this moment same current I ₁Under input voltage will be bigger, will under bigger forward voltage, overturn like this, otherwise, when voltage changes from high to low, when being higher than turnover voltage, V _rSignal is 0, the M3 conducting, and at this moment resistance R 1 is by short circuit, at this moment same current I ₁Under input voltage less, will under less reverse voltage, overturn like this, have a sluggish scope between forward turnover voltage and the reverse flip voltage, can prevent effectively that mistake from turn-offing.Switching tube M3 also can adopt N type metal-oxide-semiconductor.

Claims (1)

1. the under-voltage protecting circuit of a Switching Power Supply is characterized in that, comprises self-starting bias current sources, sample circuit, comparator, amplifier, shaping circuit and feedback circuit; The output of self-starting bias current sources connects the input of sample circuit, and the output of sample circuit connects the input of comparator, and the output of comparator connects amplifier input terminal; The output of amplifier connects the input of shaping circuit; In the output of shaping circuit, the one tunnel connects sample circuit behind feedback circuit, and another road connects protected Switching Power Supply; Wherein, self-starting bias current sources and sample circuit are a circuit module;

Self-starting bias current sources and sample circuit comprise three resistance R 1, R2 and R3, NMOS pipe M4 and a PNP triode; Resistance R 1, R2 and R3 connect successively; Another termination power vd D of resistance R 1; The other end of resistance R 3 connects grid and the drain electrode of NMOS pipe M4, and the source electrode of NMOS pipe M4 connects the emitter of PNP triode, the collector electrode of PNP triode and base earth;

Comparator comprises two PMOS pipe M5 and M6, three NMOS pipes M7, M8 and M9; The grid of NMOS pipe M7 connects being connected in series a little of resistance R 2 and R3 in self-starting bias current sources and the sample circuit; The drain electrode of the source electrode of the source electrode of NMOS pipe M7, NMOS pipe M8 and NMOS pipe M9 links together; The grid of NMOS pipe M9 connects the source electrode of NMOS pipe M4 in self-starting bias current sources and the sample circuit; The source ground of NMOS pipe M9; The grid of NMOS pipe M8 connects being connected in series a little of resistance R 3 and NMOS pipe M4 grid in self-starting bias current sources and the sample circuit, the drain electrode of NMOS pipe M7 and NMOS pipe M8 drain electrode connect the drain electrode of NMOS pipe M5 and NMOS pipe M6 respectively, the drain electrode that grid that the grid of NMOS pipe M5, NMOS manage M6 and NMOS manage M6 links together; The source electrode of NMOS pipe M5 and NMOS pipe M6 source electrode all meet power vd D, the source electrode of NMOS pipe M6 with drain between be connected capacitor C 2;

Amplifier comprises PMOS pipe M1 and NMOS pipe M2; The source electrode of PMOS pipe M1 meets power vd D; The grid of PMOS pipe M1 connects the drain electrode of NMOS pipe M7 in the comparator, and the drain electrode of PMOS pipe M1 connects the drain electrode of NMOS pipe M2, and the grid of NMOS pipe M2 connects the source electrode of NMOS pipe M4 in self-starting bias current sources and the sample circuit; The source ground of NMOS pipe M2, the source electrode of NMOS pipe M2 with drain between be connected capacitor C 1;

Shaping circuit comprises three inverter INV1, inverter INV2 and the inverter INV3 of serial connection successively; Inverter INV1 input connects the drain electrode of PMOS pipe M1 in the amplifier, and inverter INV2 is connected to protected Switching Power Supply with the point that is connected in series between the inverter INV3;

Feedback circuit is provided with a PMOS pipe M3; The grid of PMOS pipe M3 connects the output of inverter INV3 in the shaping circuit; The source electrode of PMOS pipe M3 meets power vd D, and the drain electrode of PMOS pipe M3 connects being connected in series a little of resistance R 1 and R2 in self-starting bias current sources and the sample circuit.

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