CN109495095A - Enhanced GaN power device gate drive circuit with defencive function - Google Patents
Enhanced GaN power device gate drive circuit with defencive function Download PDFInfo
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- CN109495095A CN109495095A CN201811424613.2A CN201811424613A CN109495095A CN 109495095 A CN109495095 A CN 109495095A CN 201811424613 A CN201811424613 A CN 201811424613A CN 109495095 A CN109495095 A CN 109495095A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K2017/0806—Modifications for protecting switching circuit against overcurrent or overvoltage against excessive temperature
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0054—Gating switches, e.g. pass gates
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Power Conversion In General (AREA)
- Electronic Switches (AREA)
Abstract
The enhanced GaN power device gate drive circuit with defencive function that the invention discloses a kind of, including interface circuit H, interface circuit L, dead-zone generating circuit, level shift circuit, low side delay match circuit, driving circuit H, driving circuit L, Undervoltage lockout circuit H, Undervoltage lockout circuit L, current foldback circuit and overheating protection circuit；The driving circuit can automatic detection chip overheats, supply voltage is under-voltage or over-current phenomenon avoidance, and closes GaN power device and protected, and guarantees that its working characteristics is in safety zone.
Description
Technical field
The invention belongs to IC design fields, protect more particularly, to a kind of applied to having for GaN power device
The gate driving circuit of protective function.
Technical background
Conventional electric power electronic power components based on silicon materials its theoretical limit of Step wise approximation, it is difficult to meet electric power
The growth requirement of electronic technology high frequency and high power density.Compared with traditional Si device, GaN device presents it and is leading
The advantage being powered on resistance and gate charge can make power converter realize smaller volume, higher frequency and higher efficiency, thus
It has broad application prospects in the fields such as automobile, communication, industry.The raising of switching frequency, can not only effectively reduce and be
The size of capacitor, inductance and transformer in system circuit, but also interference can be inhibited, reduce ripple, improve power-supply system unit
Gain bandwidth is to improve its dynamic response performance.And the gate driving circuit of high speed is used to drive GaN power device, so that whole
A power converter reaches high efficiency and reduces circuit area, saves cost.
Fig. 1 shows most common typical case's GaN half-bridge drive circuit block diagram in power module.As shown in Figure 1, typical
GaN half-bridge drive circuit is divided into high-end and low side two paths, by the way of Bootstrap, two-way low pressure input channel.?
During low side power GaN device is connected, switching node (SW) is pulled down to ground, and VDD gives bootstrapping electricity by bootstrap diode at this time
Capacity charge makes bootstrap capacitor voltage difference of the two ends close to VDD.Instantly when end pipe is closed, high-end input signal opens high-end tubes,
Node voltage rises to VIN, i.e. VSW rises to VIN.Since bootstrap capacitor both end voltage is constant, therefore bootstrap voltage mode rail HB
VSW+VDD is arrived by bootstrapping.High side circuitry remains VHB-VSW ≈ VDD.And HB is by bootstrap capacitor when being booted, bootstrap diode
Cathode voltage be high potential, be higher than anode voltage VDD, therefore the reverse-biased cut-off of bootstrap diode.
It is widely used for GaN FETs at present in GaN power device, mainly there is following spy compared with Si MOSFET
Point: small in same resistance to pressure conducting resistance and device volume；Switching speed is fast；Current density is big, and power density is high.GaN
These features of FETs ensure that GaN FETs has boundless prospect and market in the following power electronics applications field.But
Be that there is also some factors paid particular attention to: threshold voltage is low；Gate source voltage upper limit VGS (MAX) is low；It can reverse-conducting.
It is above-mentioned need to special consideration should be given to factor can bring some problems when driving GaN device, cause to be traditionally used for MOS power device at present
The driving circuit of part is not particularly suited for GaN power device.GaN power device is generally used under HF switch frequency (MHz or more),
After especially switching frequency reaches 10MHz, conventional gate drives biggish delay (tens nanoseconds) that will account for switch periods ratio
Example is excessive, even results in logic error, and then limit switching frequency not increasing.And the superelevation of GaN FETs works frequently
Rate, the frequency converter of GaN FETs will become abnormal important.Therefore it is necessary to provide a kind of grid drive with defencive function
Dynamic circuit.
Summary of the invention
The purpose of the present invention is overcoming the shortcomings of existing gate drive circuit, a kind of tool applied to GaN power device is provided
There is the gate driving circuit of defencive function.
The purpose of the present invention can be achieved through the following technical solutions:
A kind of enhanced GaN power device gate drive circuit with defencive function, it is characterized in that: including interface circuit H, connecing
Mouth circuit L, dead-zone generating circuit, level shift circuit, low side delay match circuit, driving circuit H, driving circuit L, under-voltage envelope
Lock circuit H, Undervoltage lockout circuit L, current foldback circuit and overheating protection circuit；
The connection relationship of the enhanced GaN power device gate drive circuit with defencive function are as follows: interface circuit H is just
Negative logic output terminal is connected to the first and second input terminals of dead-zone generating circuit；The mixed logic output end of interface circuit L connects
It is connected to the third and fourth input terminal of dead-zone generating circuit；The detection output of Undervoltage lockout circuit L is connected to dead zone and generates electricity
5th input terminal on road；The detection output of current foldback circuit is connected to the 6th input terminal of dead-zone generating circuit；Overheat is protected
The detection output of protection circuit is connected to the 7th input terminal of dead-zone generating circuit；The detection output of Undervoltage lockout circuit H connects
It is connected to the 8th input terminal of dead-zone generating circuit；First output end of dead-zone generating circuit is connected to the control of level shift circuit
Signal input part, the second output terminal of dead-zone generating circuit are connected to the control signal input of low side delay match circuit；Electricity
The signal output end of translational shifting circuit is connected to driving circuit H；The signal output end of low side delay match circuit is connected to driving
Circuit L.
The enhanced GaN power device gate drive circuit with defencive function, it is characterized in that: the level shift is electric
The end the H drive module that road, driving circuit H and Undervoltage lockout circuit H are constituted, the end H drive module, which needs to be made in one, has floating
In the high pressure trap of current potential.
The enhanced GaN power device gate drive circuit with defencive function, it is characterized in that: the overcurrent protection is electric
Road, Undervoltage lockout circuit H, Undervoltage lockout circuit L and overheating protection circuit detection output issue OC, UV_HH, UV_ respectively
HL and OH trigger signal；When the enhanced GaN power device gate drive circuit working condition with defencive function is normal, OC, UV_
HH, UV_HL and OH trigger signal are logic low；When the enhanced GaN power device gate drive circuit with defencive function
When overheating, the OH trigger signal that thermal-shutdown circuit issues becomes logic high；As the enhanced GaN with defencive function
When the supply voltage of power device gate drive circuit occurs under-voltage, the UV_HH or Undervoltage lockout that Undervoltage lockout circuit H is issued are electric
The UV_HL trigger signal that road L is issued becomes logic high；When the enhanced GaN power device grid with defencive function drive electricity
When the electric current on road is more than setting value, the OH trigger signal that current foldback circuit issues becomes logic high；When OC, UV_HH,
Any one in UV_HL and OH trigger signal occurs simultaneously from low level to when high level triggering change, and dead zone generates electricity
Road may turn off driving circuit H, driving circuit L, with the enhanced GaN power device gate drive circuit of protection band defencive function；
The logic low is ground level, and logic high is the high level of voltage lower level.
The enhanced GaN power device gate drive circuit with defencive function, it is characterized in that: the Undervoltage lockout is electric
Road H and Undervoltage lockout circuit L uses identical Undervoltage lockout circuit；The Undervoltage lockout circuit include 3 voltage detection resistances,
1 biasing resistor, 1 voltage clamping diode, 1 filter capacitor C1,8 NMOS tubes and 8 PMOS tube；
The connection relationship of the Undervoltage lockout circuit are as follows: the upper termination high side voltage VCC of first voltage detection resistance R1, the
The upper end of lower termination second voltage detection resistance R2, the upper end of filter capacitor C1 and the first NMOS tube of one voltage detection resistances R1
The grid end of M1；The upper end of the lower termination tertiary voltage detection resistance R3 of second voltage detection resistance R2 and the 16th NMOS tube M16
Drain terminal；The lower end of tertiary voltage detection resistance R3 and filter capacitor C1 meet downside voltage COM；The drain terminal of first NMOS tube M1
It is connected to the drain terminal and grid end of third PMOS tube M3, is also connected to the grid end of the M4 of the 4th PMOS tube；The source of first NMOS tube M1
End is connected to the source of the second NMOS tube M2；The grid end of second NMOS tube M2 is connected to the anode and the 6th of clamp diode DZ1
The drain terminal of PMOS tube M6, the drain terminal of the second NMOS tube M2 are connected to the drain terminal of the M4 of the 4th PMOS tube and the grid of the 9th PMOS tube M9
End；The drain terminal of 5th NMOS tube M5 is connected to the source of the first NMOS tube M1 and the source of the second NMOS tube M2, the 5th NMOS tube
The grid end of M5 is connected to the tenth NMOS tube M10 and the 11st NMOS tube M11 grid end, and the grid end of the 5th NMOS tube M5 is also connected with
To the drain terminal of the tenth NMOS tube M10 and the drain terminal of the 8th PMOS tube M8；The grid end of 6th PMOS tube M6 is connected to the 7th PMOS tube
The grid end and drain terminal of M7 and the upper end of biasing resistor R4；The grid end of 6th PMOS tube M6 is also connected to the 8th PMOS tube M8's
Grid end；The drain terminal of 11st NMOS tube M11 is connected to the drain terminal of the 9th PMOS tube M9, be also connected to the 13rd NMOS tube M13 and
The grid end of 12nd PMOS tube M12；The drain terminal of 13rd NMOS tube M13 and the 12nd PMOS tube M12 is connected, and is also connected to the tenth
The grid end of five NMOS tube M15 and the 14th PMOS tube M14；The drain terminal phase of 15th NMOS tube M15 and the 14th PMOS tube M14
Even, it is also connected to the grid end of the 16th NMOS tube M16；Other in addition to the source of the first NMOS tube M1 and the second NMOS tube M2
The source of NMOS tube is all connected to downside voltage COM, and the substrate terminal of all NMOS tubes is all connected to downside voltage COM, owns
The source of PMOS tube is all connected to high side voltage VCC, and the substrate terminal of all PMOS tube is all connected to high side voltage VCC.
The enhanced GaN power device gate drive circuit with defencive function, it is characterized in that: the overheating protection is electric
Road includes 2 temperature detection resistances, 3 biasing resistors, 1 voltage clamping diode Z91,1 filter capacitor C91,4 NMOS
Pipe and 9 PMOS tube；
The connection relationship of the overheating protection circuit are as follows: the upper end of the first temperature detection resistance Rtd is connected to second temperature
The lower end of detection resistance Rd is also connected to the grid end of the 9th 1 PMOS tube M91；The lower end of first temperature detection resistance Rtd connects
To being also connected to ground level；The upper end of second temperature detection resistance Rd is connected to supply voltage；The drain terminal of 9th 1 PMOS tube M91
It is connected to the drain terminal and grid end of the 9th 3 NMOS tube M93, is also connected to the grid end of the 9th 4 NMOS tube M94；9th 1 PMOS tube
The source of M91 is connected to the source of the 9th 2 PMOS tube M92 and the drain terminal of the 9th 5 PMOS tube M95；9th 2 PMOS tube M92's
Grid end connects the upper end of the 9th 2 biasing resistor R92 and the lower end of the 9th 1 biasing resistor R91；9th 2 biasing resistor R92's
Lower end is connected to ground level；The upper end of 9th 1 biasing resistor R91 connects the drain terminal and voltage clamping two of the 9th 6 PMOS tube M96
The anode of pole pipe Z91；The negative terminal of voltage clamping diode Z91 is connected to ground level；The grid end connection the of 9th 5 PMOS tube M95
The grid end of 96 PMOS tube M96 is also connected with the grid end of the 9th 7 PMOS tube M97, the grid end of 9.11 PMOS tube M911 and
The grid end of 98 PMOS tube M98, is also connected with the drain terminal of the 9th 8 PMOS tube M98；The drain terminal connection the 9th of 9th 4 NMOS tube M94
The drain terminal of two PMOS tube M92, is also connected to the drain terminal of 9.11 PMOS tube M911 and the grid end of the 9th 9 NMOS tube M99；The
The drain terminal of 99 NMOS tube M99 connects the drain terminal of the 9th 7 PMOS tube M97 and the grid end of the 9th 10 PMOS tube M910, is also connected with
To the upper end of filter capacitor C1；It is also connected to the grid end of the 9th 13 NMOS tube M913 and the 9th 12 PMOS tube M912；9th
The source of PMOS tube M911 is connected to the drain terminal of the 9th 10 PMOS tube M910 one by one；The lower end earth level of filter capacitor C91；
9th 13 NMOS tube M913's is connected with the 9th 12 PMOS tube M912 drain terminal, and exports and differentiate signal OH；Except the 9th 1
The source of remaining PMOS tube other than PMOS tube M91, the 9th 2 PMOS tube M92 and 9.11 PMOS tube M911 connects power supply electricity
Pressure；The substrate of all PMOS tube connects supply voltage, the equal earth level of source and substrate of all NMOS tubes.
The enhanced GaN power device gate drive circuit with defencive function, it is characterized in that: the overcurrent protection is electric
Road includes 2 current sense resistors, 5 biasing resistors, 1 voltage clamping diode Z101,1 rectifier diode D101,1
Filter capacitor C101,2 triodes, 7 NMOS tubes and 6 PMOS tube；
The current foldback circuit connection relationship are as follows: the upper end of the first current sense resistor Rd1 is connected to the inspection of the second electric current
The upper end of measuring resistance Rd2, be also connected to the first triode Q1 base stage and current input terminal to be detected；First current sense resistor
The lower end of Rd1 is connected to the lower end of the second current sense resistor Rd2, is also connected to ground level；The collector of first triode Q1
It is connected to the source of the one zero six NMOS tube M106, the emitter of the first triode Q1 is connected to the one zero three biasing resistor R103
Upper end and the second triode Q2 emitter；The base stage of second triode Q2 connects the upper end of the one zero two biasing resistor R102
With the lower end of the one zero one biasing resistor R101；The lower end of one zero two biasing resistor R102 is connected to ground level；One zero one
The upper end of biasing resistor R101 connects the lower end of the one zero five biasing resistor R105 and the anode of voltage clamping diode Z101；Electricity
The negative terminal of pressure clamp diode Z101 is connected to ground level；The upper termination supply voltage of one zero five biasing resistor R105；First
The drain terminal of 06 NMOS tube M106 is connected to the drain terminal and grid end of the one zero one PMOS tube M101, is also connected to the one zero two PMOS
The grid end of the grid end of pipe M102 and the one zero four PMOS tube M104；The drain terminal of one zero two PMOS tube M102 is connected to the 1st
The drain terminal of NMOS tube M107 is also connected to the drain terminal and grid end of the one zero three PMOS tube M103, is also connected to the one zero five PMOS
The grid end of pipe M105；The drain terminal of one zero four PMOS tube M104 is connected to the drain terminal of the one zero eight NMOS tube M108；One zero five
The drain terminal of PMOS tube M105 is connected to the drain terminal of the one zero nine NMOS tube M109；The source of one zero eight NMOS tube M8 is connected to
The drain terminal of zero NMOS tube M110 one by one, is also connected to the grid end of the one one three NMOS tube M113 and the one one two PMOS tube M112；
The source of one zero nine NMOS tube M109 is connected to the drain terminal and grid end of the first NMOS tube M111 one by one；One one three NMOS tube
M113's is connected with the one one two PMOS tube M112 drain terminal, and exports and differentiate signal OC；The lower end of filter capacitor C101 is grounded electricity
Flat, the upper end of filter capacitor C101 is connected to the lower end of the one zero four biasing resistor R104 and the anode of rectifier diode D1, filter
The upper end of wave capacitor C101 is also connected to the one zero six NMOS tube M106, the one zero seven NMOS tube M107, the one zero eight NMOS tube
The grid end of M108 and the one zero nine NMOS tube M109, the upper end of filter capacitor C101 are also connected to the one one two PMOS tube M112's
Source；The source of remaining PMOS tube in addition to the one one two PMOS tube M112 connects supply voltage；First NMOS tube one by one
The equal earth level of source of M111, the one zero one NMOS tube M113 and the one one zero NMOS tube M110；The substrate of all PMOS tube
Connect supply voltage, the equal earth level of the substrate of all NMOS tubes.
The invention has the advantages that detection GaN power chip overheats automatically, supply voltage is under-voltage or over-current phenomenon avoidance, and close
The major power consumers of chip interior are closed, guarantee that GaN power device is in work safety area.
Detailed description of the invention
Fig. 1 shows typical GaN half-bridge drive circuit block diagram according to prior art；
Fig. 2 is the enhanced GaN power device gate drive circuit block diagram of the invention with defencive function；
Fig. 3 is the schematic diagram of interface circuit of the present invention；
Fig. 4 is the schematic diagram of dead-zone generating circuit of the present invention；
Fig. 5 is the schematic diagram of level shift circuit of the present invention；
Fig. 6 is the schematic diagram of low side delay match circuit of the present invention；
Fig. 7 is the schematic diagram of present invention driver circuit；
Fig. 8 is the schematic diagram of Undervoltage lockout circuit of the present invention；
Fig. 9 is the schematic diagram of overheating protection circuit of the present invention；
Figure 10 is the schematic diagram of current foldback circuit of the present invention.
Specific embodiment
The present invention is described in more detail with example with reference to the accompanying drawing.
As shown in Fig. 2, a kind of enhanced GaN power device gate drive circuit with defencive function, including interface circuit H,
It is interface circuit L, dead-zone generating circuit, level shift circuit, low side delay match circuit, driving circuit H, driving circuit L, under-voltage
Lockout circuit H, Undervoltage lockout circuit L, current foldback circuit and overheating protection circuit.
The connection relationship of circuit shown in Fig. 2 are as follows: the mixed logic output end of interface circuit H is connected to dead-zone generating circuit
First and second input terminals；The mixed logic output end of interface circuit L is connected to the third and fourth input of dead-zone generating circuit
End；The detection output of Undervoltage lockout circuit L is connected to the 5th input terminal of dead-zone generating circuit；The detection of current foldback circuit
Output end is connected to the 6th input terminal of dead-zone generating circuit；The detection output of overheating protection circuit is connected to dead zone and generates electricity
7th input terminal on road；The detection output of Undervoltage lockout circuit H is connected to the 8th input terminal of dead-zone generating circuit；Is produced from dead zone
First output end of raw circuit is connected to the control signal input of level shift circuit, the second output terminal of dead-zone generating circuit
It is connected to the control signal input of low side delay match circuit；The signal output end of level shift circuit is connected to driving circuit
H；The signal output end of low side delay match circuit is connected to driving circuit L.
The input logic square-wave signal input signal of circuit shown in Fig. 2, two-way 5V generates electricity by interface circuit, dead zone
Road, level displacement circuit and low side delay match circuit.It is reference that driving signal and the end H of 0-5V of the end L, which is converted into, with VS
Amplitude is the driving signal of 5V, and the phase of two paths of signals matches.Driving signal is subsequently into drive module, including two
Identical output stage drive circuit.The difference is that level shift circuit, driving circuit H and Undervoltage lockout circuit H were constituted
The end H drive module, the end H drive module need to be made in the high pressure trap with floating potential, and trap potential highest can float
To super-pressure, such as 600V.Output stage is in parallel using many LDMOS cellulars, and the driving signal of output is made to have certain power
Processing capacity.H end signal produces certain delay compared to L end signal, for medium-high frequency after level displacement circuit
Using having had resulted in the mismatch of both ends signal phase this period, will affect the normal work of system.Therefore, it is necessary in L
Delay matching circuit is added on end signal access, reaches the matching of the phase of two end signals.
Since GaN FETs working frequency is quite high, for the reliability for guaranteeing power device, accident is prevented, the present invention
4 kinds of safeguard measures, including current foldback circuit, Undervoltage lockout circuit H, Undervoltage lockout circuit L and overheating protection circuit are devised,
The detection output of 4 circuits issues OC, UV_HH, UV_HL and OH trigger signal respectively.As the enhanced GaN with defencive function
When power device gate drive circuit working condition is normal, OC, UV_HH, UV_HL and OH trigger signal are logic low；When
When enhanced GaN power device gate drive circuit with defencive function overheats, the OH that thermal-shutdown circuit issues triggers letter
Number become logic high；When the supply voltage generation of the enhanced GaN power device gate drive circuit with defencive function is under-voltage
When, the UV_HL trigger signal that the UV_HH or Undervoltage lockout circuit L that Undervoltage lockout circuit H is issued are issued becomes logically high electricity
It is flat；When the electric current of the enhanced GaN power device gate drive circuit with defencive function is more than setting value, current foldback circuit hair
OH trigger signal out becomes logic high；Go out when any one in OC, UV_HH, UV_HL and OH trigger signal or simultaneously
When now triggering change to high level from low level, dead-zone generating circuit may turn off driving circuit H, driving circuit L, with protection band
The enhanced GaN power device gate drive circuit of defencive function.The logic low is ground level, and logic high is voltage
The high level of lower level.
Fig. 3 is a kind of specific implementation schematic diagram of interface circuit of the present invention.Input port IN is received before chip exterior
The pwm control signal generated in the control circuit of end, the generally square-wave signal of 5V, the control signal are input to the negative of comparator
End, is compared with the reference voltage of comparator anode.When input voltage is greater than reference voltage, comparator exports low potential,
By the filter network of low-pass filtering resistance and low-pass filtering capacitor composition, realizes the elimination of noise signal, finally obtain and compare
The amplitude of pure square-wave signal, the same phase of output signal OUT1 and input signal IN, OUT2 and IN reverse phase, OUT1 and OUT2 is
15V, i.e. interface circuit complete the function of the level shift of 5V -15V.Interface circuit H and interface circuit L of the present invention
It can be realized using circuit shown in Fig. 3.
Fig. 4 is a kind of specific implementation schematic diagram of dead-zone generating circuit of the present invention.Input signal is from the defeated of interface circuit
Out, the wherein same phase of H1 and L2, with the same phase of input signal HIN, H2 and the same phase of L1, with the same phase of input signal LIN.FAULT letter
It number is system control signal, OC is the output of current foldback circuit, and OH is the output of overheating protection circuit, and UV_HH is under-voltage envelope
The output of lock circuit H, UV_HL are the output of Undervoltage lockout circuit L.When FAULT signal is that high or circuit overheat, mistake occurs
When stream or supply voltage occur under-voltage, the low level for keeping the output of dead-zone circuit constant, late-class circuit stops working, until
Circuit is cleared.The universal way for generating dead zone is that the two paths of signals of input is made to generate phase difference using delay circuit, then
Logical operation is carried out to input signal again, just obtains a dead time.The size of the dead time is generated by delay circuit
Delay time determine, therefore when delay circuit dead-zone circuit core.Delay circuit can use phase inverter and RC network.
Fig. 5 is a kind of specific implementation schematic diagram of level shift circuit of the present invention.High voltage level shift circuit is whole grid
The maximum circuit structure of power consumption in driving chip has data to show that its power consumption accounts for about 80% or more of entire chip power-consumption.
It must also include high voltage bearing high-voltage LDMOS device in circuit to realize the level shift of high pressure.The circuit includes that pulse produces
Raw and shaping circuit, high-voltage LDMOS device, comparator A, comparator B, nor gate NOR1, filter circuit and rest-set flip-flop.
The working principle of circuit shown in Fig. 5 is as follows: pulse generation and shaping circuit convert input signal OUT_H to all the way
Narrow pulse signal, pulse correspond respectively to the rising edge and failing edge of square wave, the doubling frequency of signal.OUT_H also controls M51
Open and shut off.When OUT_H is low, M51 pipe shutdown, LDMOS and two resistance forms branch, and LDMOS grid electrode is high electricity
Usually, LDMOS is opened, and LDMOS drain terminal current potential is the VH low compared with VB；LDMOS grid electrode be low level when, LDMOS shutdown, branch without
Electric current, it is VB that LDMOS, which leaks summit potential,.When OUT_H is high, M51 pipe is opened, and resistor network parallel connection accesses the source electrode of LDMOS,
When LDMOS grid electrode is high, LDMOS is opened, and LDMOS leaks summit potential for the VL low compared with VB, and VL < VH；When LDMOS grid electrode current potential
When being low, LDMOS shutdown.Comparator A and comparator B, LDMOS drain potential is compared with reference voltage respectively, output
Two pulse signals obtain the two-way burst pulse of rising edge and failing edge after carrying out logical operation by nor gate.Two-way pulse
Interference and noise in signal are filtered out by filter circuit, then square-wave signal all the way is reduced to by rest-set flip-flop, the square wave
The amplitude of signal is between VB and VS.
Fig. 6 is a kind of specific implementation schematic diagram of low side delay match circuit of the present invention.Structurally, the delay matching
Circuit in level displacement circuit shown in Fig. 5 pulse shaper and filter circuit it is similar, first use cross-coupled circuit, make
The rising edge and failing edge of signal are more precipitous, using RC network, realize the delay of signal.
Since the parasitic gate capacitor of power device is bigger, in order to ensure grid capacitance energy fast charging and discharging, make device
Rapid saturation conduction and reliable turn-off, it is desirable that the output impedance of driving circuit is small, and output electric current is big.Therefore, high low side two-way
Signal increases driving circuit in output stage, to enhance the current capacity of signal, and reduces the output impedance of circuit.Fig. 7 is
A kind of specific implementation schematic diagram of present invention driver circuit.Stage drive circuit is exported by chain of inverters, M71 and M72 composition.M71
The output electric current of driving circuit is determined with branch where M72 pipe, while also determining the output resistance of circuit.It works normally
When, M71 is managed and M72 pipe cross-conduction, and since M71 is PMOS device, M72 is NMOS device, therefore the gate driving of two pipes is believed
It is number identical.
Undervoltage lockout circuit H and Undervoltage lockout circuit L of the present invention use identical Undervoltage lockout circuit structure, and Fig. 8 is deficient
A kind of specific implementation schematic diagram of press seal lock circuit.Including 3 voltage detection resistances, 1 biasing resistor, 1 voltage clamping two
Pole pipe, 1 filter capacitor C1,8 NMOS tubes and 8 PMOS tube.The connection relationship of circuit shown in Fig. 8 are as follows: first voltage detection
The upper end of the lower termination second voltage detection resistance R2 of the upper termination high side voltage VCC of resistance R1, first voltage detection resistance R1,
The grid end of the upper end of filter capacitor C1 and the first NMOS tube M1；The lower termination tertiary voltage of second voltage detection resistance R2 detects electricity
Hinder the upper end of R3 and the drain terminal of the 16th NMOS tube M16；The lower end of tertiary voltage detection resistance R3 and filter capacitor C1 connect low
Side voltage COM；The drain terminal of first NMOS tube M1 is connected to the drain terminal and grid end of third PMOS tube M3, is also connected to the 4th PMOS tube
M4 grid end；The source of first NMOS tube M1 is connected to the source of the second NMOS tube M2；The grid end of second NMOS tube M2 connects
To the anode of clamp diode DZ1 and the drain terminal of the 6th PMOS tube M6, the drain terminal of the second NMOS tube M2 is connected to the 4th PMOS tube
M4 drain terminal and the 9th PMOS tube M9 grid end；The drain terminal of 5th NMOS tube M5 is connected to the source and of the first NMOS tube M1
The source of two NMOS tube M2, the grid end of the 5th NMOS tube M5 are connected to the tenth NMOS tube M10 and the 11st NMOS tube M11 grid
End, the grid end of the 5th NMOS tube M5 are also connected to the drain terminal of the tenth NMOS tube M10 and the drain terminal of the 8th PMOS tube M8；6th PMOS
The grid end of pipe M6 is connected to the grid end of the 7th PMOS tube M7 and the upper end of drain terminal and biasing resistor R4；6th PMOS tube M6's
Grid end is also connected to the grid end of the 8th PMOS tube M8；The drain terminal of 11st NMOS tube M11 is connected to the drain terminal of the 9th PMOS tube M9,
It is also connected to the grid end of the 13rd NMOS tube M13 and the 12nd PMOS tube M12；13rd NMOS tube M13 and the 12nd PMOS tube
The drain terminal of M12 is connected, and is also connected to the grid end of the 15th NMOS tube M15 and the 14th PMOS tube M14；15th NMOS tube M15
It is connected with the drain terminal of the 14th PMOS tube M14, is also connected to the grid end of the 16th NMOS tube M16；Except the source of the first NMOS tube M1
End and the source of other NMOS tubes except the second NMOS tube M2 are all connected to downside voltage COM, the substrate terminal of all NMOS tubes
It is all connected to downside voltage COM, the source of all PMOS tube is all connected to high side voltage VCC, and the substrate terminal of all PMOS tube is equal
It is connected to high side voltage VCC.
The circuit being made of in Fig. 8 R4, DZ1, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10 and M11 is a sluggishness
Voltage comparator, the grid end voltage that the negative terminal of comparator is M1 are variation voltage V_, and the anode voltage of comparator is reference voltage
VREF.The filter capacitor C1 of the grid end connection of M1 is for filtering out the spike burr signal occurred on high side and low side power voltage
Interference.High side and low side power voltage are input to by voltage detection resistances R1, R2 and R3 real-time detection, the voltage value V_ detected
The negative terminal of comparator is compared with the reference voltage VREF of comparator anode.When supply voltage is normal, V_ ratio VREF high,
Comparator exports low level, and UV_L is height, and UV_H is low, M1 pipe shutdown.
Fig. 9 is a kind of specific implementation schematic diagram of overheating protection circuit of the present invention.Including 2 temperature detection resistances, 3 partially
Set resistance, 1 voltage clamping diode Z91,1 filter capacitor C91,4 NMOS tubes and 9 PMOS tube.
The connection relationship of circuit shown in Fig. 9 are as follows: the upper end of the first temperature detection resistance Rtd is connected to second temperature detection electricity
The lower end for hindering Rd, is also connected to the grid end of the 9th 1 PMOS tube M91；The lower end of first temperature detection resistance Rtd, which is connected to, also to be connected
It is connected to ground level；The upper end of second temperature detection resistance Rd is connected to supply voltage；The drain terminal of 9th 1 PMOS tube M91 is connected to
The drain terminal and grid end of 9th 3 NMOS tube M93 is also connected to the grid end of the 9th 4 NMOS tube M94；The source of 9th 1 PMOS tube M91
End is connected to the source of the 9th 2 PMOS tube M92 and the drain terminal of the 9th 5 PMOS tube M95；The grid end of 9th 2 PMOS tube M92 connects
Connect the upper end of the 9th 2 biasing resistor R92 and the lower end of the 9th 1 biasing resistor R91；The lower end of 9th 2 biasing resistor R92 connects
It is connected to ground level；The upper end of 9th 1 biasing resistor R91 connects the drain terminal and voltage clamping diode of the 9th 6 PMOS tube M96
The anode of Z91；The negative terminal of voltage clamping diode Z91 is connected to ground level；The grid end connection the 9th 6 of 9th 5 PMOS tube M95
The grid end of PMOS tube M96 is also connected with the grid end of the 9th 7 PMOS tube M97, the grid end and the 9th 8 of 9.11 PMOS tube M911
The grid end of PMOS tube M98 is also connected with the drain terminal of the 9th 8 PMOS tube M98；The drain terminal connection the 9th 2 of 9th 4 NMOS tube M94
The drain terminal of PMOS tube M92 is also connected to the drain terminal of 9.11 PMOS tube M911 and the grid end of the 9th 9 NMOS tube M99；9th
The drain terminal of nine NMOS tube M99 connects the drain terminal of the 9th 7 PMOS tube M97 and the grid end of the 9th 10 PMOS tube M910, is also connected to
The upper end of filter capacitor C1；It is also connected to the grid end of the 9th 13 NMOS tube M913 and the 9th 12 PMOS tube M912；9th 1
The source of one PMOS tube M911 is connected to the drain terminal of the 9th 10 PMOS tube M910；The lower end earth level of filter capacitor C91；The
913 NMOS tube M913's is connected with the 9th 12 PMOS tube M912 drain terminal, and exports and differentiate signal OH；Except the 9th 1 PMOS
The source of remaining PMOS tube other than pipe M91, the 9th 2 PMOS tube M92 and 9.11 PMOS tube M911 connects supply voltage；
The substrate of all PMOS tube connects supply voltage, the equal earth level of source and substrate of all NMOS tubes.
In Fig. 9 by R91, R92, R93, Z91, C91, M91, M92, M93, M94, M95, M96, M97, M98, M99, M910,
The circuit that M911, M912 and M913 are constituted is a hysteresis voltage comparator.The negative terminal of comparator is detection voltage SD；Comparator
Anode be reference voltage SR.Temperature detection resistance Rtd is thermistor, for detecting temperature level.Temperature detection is by resistance
Detection voltage SD is obtained after Rd and Rtd partial pressure detection.
Figure 10 is a kind of specific implementation schematic diagram of current foldback circuit of the present invention.Including 2 current sense resistors, 5
Biasing resistor, 1 voltage clamping diode Z101,1 rectifier diode D101,1 filter capacitor C101,2 triodes, 7
A NMOS tube and 6 PMOS tube.
Current foldback circuit connection relationship shown in Fig. 10 are as follows: the upper end of the first current sense resistor Rd1 is connected to second
The upper end of current sense resistor Rd2, be also connected to the first triode Q1 base stage and current input terminal to be detected；The inspection of first electric current
The lower end of measuring resistance Rd1 is connected to the lower end of the second current sense resistor Rd2, is also connected to ground level；First triode Q1's
Collector is connected to the source of the one zero six NMOS tube M106, and the emitter of the first triode Q1 is connected to the one zero three biased electrical
Hinder the upper end of R103 and the emitter of the second triode Q2；The base stage of second triode Q2 connects the one zero two biasing resistor R102
Upper end and the one zero one biasing resistor R101 lower end；The lower end of one zero two biasing resistor R102 is connected to ground level；The
The upper end of one zero one biasing resistor R101 connects lower end and the voltage clamping diode Z101 of the one zero five biasing resistor R105
Anode；The negative terminal of voltage clamping diode Z101 is connected to ground level；The upper termination power electricity of one zero five biasing resistor R105
Pressure；The drain terminal of one zero six NMOS tube M106 is connected to the drain terminal and grid end of the one zero one PMOS tube M101, is also connected to first
The grid end of 02 PMOS tube M102 and the grid end of the one zero four PMOS tube M104；The drain terminal of one zero two PMOS tube M102 is connected to
The drain terminal of one zero seven NMOS tube M107 is also connected to the drain terminal and grid end of the one zero three PMOS tube M103, is also connected to first
The grid end of 05 PMOS tube M105；The drain terminal of one zero four PMOS tube M104 is connected to the drain terminal of the one zero eight NMOS tube M108；
The drain terminal of one zero five PMOS tube M105 is connected to the drain terminal of the one zero nine NMOS tube M109；The source of one zero eight NMOS tube M8
It is connected to the drain terminal of the one one zero NMOS tube M110, is also connected to the one one three NMOS tube M113 and the one one two PMOS tube M112
Grid end；The source of one zero nine NMOS tube M109 is connected to the drain terminal and grid end of the first NMOS tube M111 one by one；One one three
NMOS tube M113's is connected with the one one two PMOS tube M112 drain terminal, and exports and differentiate signal OC；The lower end of filter capacitor C101
Earth level, the upper end of filter capacitor C101 are connected to the lower end of the one zero four biasing resistor R104 and the sun of rectifier diode D1
Pole, the upper end of filter capacitor C101 are also connected to the one zero six NMOS tube M106, the one zero seven NMOS tube M107, the 1st
The grid end of NMOS tube M108 and the one zero nine NMOS tube M109, the upper end of filter capacitor C101 are also connected to the one one two PMOS tube
The source of M112；The source of remaining PMOS tube in addition to the one one two PMOS tube M112 connects supply voltage；First one by one
The equal earth level of source of NMOS tube M111, the one zero one NMOS tube M113 and the one one zero NMOS tube M110；All PMOS tube
Substrate connect supply voltage, the equal earth level of the substrate of all NMOS tubes.
In Figure 10 by R101, R102, R103, R104, R105, Q1, Q2, Z101, C101, D101, M101, M102, M103,
The circuit that M104, M105, M106, M107, M108, M109, M110, M111, M112 and M113 are constituted is a hysteresis voltage ratio
Compared with device.After electric current to be detected is by 2 current sense resistor Rd1 and Rd2 in parallel, detection voltage Vt is obtained.Current detecting electricity
Resistance Rd2 is variable resistance, for adjusting current detection range and overcurrent threshold size.The base stage electricity that the negative terminal of comparator is Q1
Pressure, to detect voltage Vt；The anode of comparator is the base voltage of Q2, is reference voltage REF.M106, M107, M108 and M109
The filter capacitor C101 of grid end connection be used to filter out the interference of the spike burr signal occurred on supply voltage.By GaN device
For the electric current to be detected of output by current sense resistor Rd1 and Rd2 real-time detection, the voltage value Vt detected is input to comparator
Negative terminal is compared with the reference voltage REF of comparator anode.When electric current is normal, Vt ratio VREF high, comparator exports low electricity
It is flat.When electric current starts to become larger, Vt is further change in, and after feedback to comparator, the state of lock-in circuit keeps output constant.
When electric current slowly restores, Vt ratio REF high, the overturning of comparator output voltage.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (6)
1. a kind of enhanced GaN power device gate drive circuit with defencive function, it is characterized in that: including interface circuit H, interface
Circuit L, dead-zone generating circuit, level shift circuit, low side delay match circuit, driving circuit H, driving circuit L, Undervoltage lockout
Circuit H, Undervoltage lockout circuit L, current foldback circuit and overheating protection circuit；
The connection relationship of the enhanced GaN power device gate drive circuit with defencive function are as follows: the positive and negative of interface circuit H is patrolled
Collect the first and second input terminals that output end is connected to dead-zone generating circuit；The mixed logic output end of interface circuit L is connected to
Third and fourth input terminal of dead-zone generating circuit；The detection output of Undervoltage lockout circuit L is connected to dead-zone generating circuit
5th input terminal；The detection output of current foldback circuit is connected to the 6th input terminal of dead-zone generating circuit；Overheating protection electricity
The detection output on road is connected to the 7th input terminal of dead-zone generating circuit；The detection output of Undervoltage lockout circuit H is connected to
8th input terminal of dead-zone generating circuit；First output end of dead-zone generating circuit is connected to the control signal of level shift circuit
Input terminal, the second output terminal of dead-zone generating circuit are connected to the control signal input of low side delay match circuit；Level moves
The signal output end of position circuit is connected to driving circuit H；The signal output end of low side delay match circuit is connected to driving circuit
L。
2. the enhanced GaN power device gate drive circuit according to claim 1 with defencive function, it is characterized in that: institute
The end the H drive module that level shift circuit, driving circuit H and Undervoltage lockout circuit H are constituted is stated, drive module needs in the end H are made in
In one high pressure trap with floating potential.
3. the enhanced GaN power device gate drive circuit according to claim 1 with defencive function, it is characterized in that: institute
The detection output for stating current foldback circuit, Undervoltage lockout circuit H, Undervoltage lockout circuit L and overheating protection circuit issues respectively
OC, UV_HH, UV_HL and OH trigger signal；When the enhanced GaN power device gate drive circuit working condition with defencive function
When normal, OC, UV_HH, UV_HL and OH trigger signal are logic low；When the enhanced GaN power device with defencive function
When part gate drive circuit overheats, the OH trigger signal that thermal-shutdown circuit issues becomes logic high；When band protects function
When the supply voltage of the enhanced GaN power device gate drive circuit of energy occurs under-voltage, the UV_HH of Undervoltage lockout circuit H sending
Or the UV_HL trigger signal that Undervoltage lockout circuit L is issued becomes logic high；When the enhanced GaN function with defencive function
When the electric current of rate device gate drive circuit is more than setting value, the OH trigger signal that current foldback circuit issues becomes logically high electricity
It is flat；When any one in OC, UV_HH, UV_HL and OH trigger signal or occur triggering from low level to high level simultaneously and change
When, dead-zone generating circuit may turn off driving circuit H, driving circuit L, with the enhanced GaN power device of protection band defencive function
Part gate drive circuit；The logic low is ground level, and logic high is the high level of voltage lower level.
4. the enhanced GaN power device gate drive circuit according to claim 1 with defencive function, it is characterized in that: institute
It states Undervoltage lockout circuit H and Undervoltage lockout circuit L and uses identical Undervoltage lockout circuit；The Undervoltage lockout circuit includes 3
Voltage detection resistances, 1 biasing resistor, 1 voltage clamping diode, 1 filter capacitor C1,8 NMOS tubes and 8 PMOS
Pipe；
The connection relationship of the Undervoltage lockout circuit are as follows: the upper termination high side voltage VCC of first voltage detection resistance R1, the first electricity
Press the upper end of lower termination second voltage detection resistance R2 of detection resistance R1, the upper end of filter capacitor C1 and the first NMOS tube M1
Grid end；The upper end of the lower termination tertiary voltage detection resistance R3 of second voltage detection resistance R2 and the leakage of the 16th NMOS tube M16
End；The lower end of tertiary voltage detection resistance R3 and filter capacitor C1 meet downside voltage COM；The drain terminal of first NMOS tube M1 connects
To the drain terminal and grid end of third PMOS tube M3, it is also connected to the grid end of the M4 of the 4th PMOS tube；The source of first NMOS tube M1 connects
It is connected to the source of the second NMOS tube M2；The grid end of second NMOS tube M2 is connected to the anode and the 6th PMOS of clamp diode DZ1
The drain terminal of pipe M6, the drain terminal of the second NMOS tube M2 are connected to the drain terminal of the M4 of the 4th PMOS tube and the grid end of the 9th PMOS tube M9；
The drain terminal of 5th NMOS tube M5 is connected to the source of the first NMOS tube M1 and the source of the second NMOS tube M2, the 5th NMOS tube M5's
Grid end is connected to the tenth NMOS tube M10 and the 11st NMOS tube M11 grid end, and the grid end of the 5th NMOS tube M5 is also connected to the
The drain terminal of ten NMOS tube M10 and the drain terminal of the 8th PMOS tube M8；The grid end of 6th PMOS tube M6 is connected to the 7th PMOS tube M7's
The upper end of grid end and drain terminal and biasing resistor R4；The grid end of 6th PMOS tube M6 is also connected to the grid end of the 8th PMOS tube M8；
The drain terminal of 11st NMOS tube M11 is connected to the drain terminal of the 9th PMOS tube M9, is also connected to the 13rd NMOS tube M13 and the 12nd
The grid end of PMOS tube M12；The drain terminal of 13rd NMOS tube M13 and the 12nd PMOS tube M12 is connected, and is also connected to the 15th NMOS
The grid end of pipe M15 and the 14th PMOS tube M14；The drain terminal of 15th NMOS tube M15 and the 14th PMOS tube M14 is connected, and also connects
It is connected to the grid end of the 16th NMOS tube M16；Other NMOS tubes in addition to the source of the first NMOS tube M1 and the second NMOS tube M2
Source be all connected to downside voltage COM, the substrate terminal of all NMOS tubes is all connected to downside voltage COM, all PMOS tube
Source is all connected to high side voltage VCC, and the substrate terminal of all PMOS tube is all connected to high side voltage VCC.
5. the enhanced GaN power device gate drive circuit according to claim 1 with defencive function, it is characterized in that: institute
Stating overheating protection circuit includes 2 temperature detection resistances, 3 biasing resistors, 1 voltage clamping diode Z91,1 filtered electrical
Hold C91,4 NMOS tubes and 9 PMOS tube；
The connection relationship of the overheating protection circuit are as follows: the upper end of the first temperature detection resistance Rtd is connected to second temperature detection
The lower end of resistance Rd is also connected to the grid end of the 9th 1 PMOS tube M91；The lower end of first temperature detection resistance Rtd is connected to also
It is connected to ground level；The upper end of second temperature detection resistance Rd is connected to supply voltage；The drain terminal of 9th 1 PMOS tube M91 connects
To the drain terminal and grid end of the 9th 3 NMOS tube M93, it is also connected to the grid end of the 9th 4 NMOS tube M94；9th 1 PMOS tube M91's
Source is connected to the source of the 9th 2 PMOS tube M92 and the drain terminal of the 9th 5 PMOS tube M95；The grid end of 9th 2 PMOS tube M92
Connect the upper end of the 9th 2 biasing resistor R92 and the lower end of the 9th 1 biasing resistor R91；The lower end of 9th 2 biasing resistor R92
It is connected to ground level；The upper end of 9th 1 biasing resistor R91 connects the drain terminal and voltage clamping diode of the 9th 6 PMOS tube M96
The anode of Z91；The negative terminal of voltage clamping diode Z91 is connected to ground level；The grid end connection the 9th 6 of 9th 5 PMOS tube M95
The grid end of PMOS tube M96 is also connected with the grid end of the 9th 7 PMOS tube M97, the grid end and the 9th 8 of 9.11 PMOS tube M911
The grid end of PMOS tube M98 is also connected with the drain terminal of the 9th 8 PMOS tube M98；The drain terminal connection the 9th 2 of 9th 4 NMOS tube M94
The drain terminal of PMOS tube M92 is also connected to the drain terminal of 9.11 PMOS tube M911 and the grid end of the 9th 9 NMOS tube M99；9th
The drain terminal of nine NMOS tube M99 connects the drain terminal of the 9th 7 PMOS tube M97 and the grid end of the 9th 10 PMOS tube M910, is also connected to
The upper end of filter capacitor C1；It is also connected to the grid end of the 9th 13 NMOS tube M913 and the 9th 12 PMOS tube M912；9th 1
The source of one PMOS tube M911 is connected to the drain terminal of the 9th 10 PMOS tube M910；The lower end earth level of filter capacitor C91；The
913 NMOS tube M913's is connected with the 9th 12 PMOS tube M912 drain terminal, and exports and differentiate signal OH；Except the 9th 1 PMOS
The source of remaining PMOS tube other than pipe M91, the 9th 2 PMOS tube M92 and 9.11 PMOS tube M911 connects supply voltage；
The substrate of all PMOS tube connects supply voltage, the equal earth level of source and substrate of all NMOS tubes.
6. the enhanced GaN power device gate drive circuit according to claim 1 with defencive function, it is characterized in that: institute
Stating current foldback circuit includes 2 current sense resistors, 5 biasing resistors, 1 voltage clamping diode Z101,1 rectification two
Pole pipe D101,1 filter capacitor C101,2 triodes, 7 NMOS tubes and 6 PMOS tube；
The current foldback circuit connection relationship are as follows: the upper end of the first current sense resistor Rd1 is connected to the second current detecting electricity
Hinder Rd2 upper end, be also connected to the first triode Q1 base stage and current input terminal to be detected；First current sense resistor Rd1
Lower end be connected to the lower end of the second current sense resistor Rd2, be also connected to ground level；The collector of first triode Q1 connects
Emitter to the source of the one zero six NMOS tube M106, the first triode Q1 is connected to the upper of the one zero three biasing resistor R103
The emitter at end and the second triode Q2；The base stage of second triode Q2 connects the upper end and the of the one zero two biasing resistor R102
The lower end of one zero one biasing resistor R101；The lower end of one zero two biasing resistor R102 is connected to ground level；One zero one biasing
The upper end of resistance R101 connects the lower end of the one zero five biasing resistor R105 and the anode of voltage clamping diode Z101；Voltage clamp
The negative terminal of position diode Z101 is connected to ground level；The upper termination supply voltage of one zero five biasing resistor R105；One zero six
The drain terminal of NMOS tube M106 is connected to the drain terminal and grid end of the one zero one PMOS tube M101, is also connected to the one zero two PMOS tube
The grid end of the grid end of M102 and the one zero four PMOS tube M104；The drain terminal of one zero two PMOS tube M102 is connected to the 1st
The drain terminal of NMOS tube M107 is also connected to the drain terminal and grid end of the one zero three PMOS tube M103, is also connected to the one zero five PMOS
The grid end of pipe M105；The drain terminal of one zero four PMOS tube M104 is connected to the drain terminal of the one zero eight NMOS tube M108；One zero five
The drain terminal of PMOS tube M105 is connected to the drain terminal of the one zero nine NMOS tube M109；The source of one zero eight NMOS tube M8 is connected to
The drain terminal of zero NMOS tube M110 one by one, is also connected to the grid end of the one one three NMOS tube M113 and the one one two PMOS tube M112；
The source of one zero nine NMOS tube M109 is connected to the drain terminal and grid end of the first NMOS tube M111 one by one；One one three NMOS tube
M113's is connected with the one one two PMOS tube M112 drain terminal, and exports and differentiate signal OC；The lower end of filter capacitor C101 is grounded electricity
Flat, the upper end of filter capacitor C101 is connected to the lower end of the one zero four biasing resistor R104 and the anode of rectifier diode D1, filter
The upper end of wave capacitor C101 is also connected to the one zero six NMOS tube M106, the one zero seven NMOS tube M107, the one zero eight NMOS tube
The grid end of M108 and the one zero nine NMOS tube M109, the upper end of filter capacitor C101 are also connected to the one one two PMOS tube M112's
Source；The source of remaining PMOS tube in addition to the one one two PMOS tube M112 connects supply voltage；First NMOS tube one by one
The equal earth level of source of M111, the one zero one NMOS tube M113 and the one one zero NMOS tube M110；The substrate of all PMOS tube
Connect supply voltage, the equal earth level of the substrate of all NMOS tubes.
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