CN109495095B - Enhanced GaN power device gate drive circuit with protection function - Google Patents
Enhanced GaN power device gate drive circuit with protection function Download PDFInfo
- Publication number
- CN109495095B CN109495095B CN201811424613.2A CN201811424613A CN109495095B CN 109495095 B CN109495095 B CN 109495095B CN 201811424613 A CN201811424613 A CN 201811424613A CN 109495095 B CN109495095 B CN 109495095B
- Authority
- CN
- China
- Prior art keywords
- circuit
- nmos transistor
- ninth
- pmos
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000000903 blocking effect Effects 0.000 claims abstract description 19
- 238000013021 overheating Methods 0.000 claims abstract description 7
- 238000001514 detection method Methods 0.000 claims description 76
- 239000003990 capacitor Substances 0.000 claims description 41
- 239000000758 substrate Substances 0.000 claims description 18
- AZFKQCNGMSSWDS-UHFFFAOYSA-N MCPA-thioethyl Chemical compound CCSC(=O)COC1=CC=C(Cl)C=C1C AZFKQCNGMSSWDS-UHFFFAOYSA-N 0.000 claims description 5
- 238000007667 floating Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 19
- 230000000630 rising effect Effects 0.000 description 3
- 238000007493 shaping process Methods 0.000 description 3
- HCUOEKSZWPGJIM-YBRHCDHNSA-N (e,2e)-2-hydroxyimino-6-methoxy-4-methyl-5-nitrohex-3-enamide Chemical compound COCC([N+]([O-])=O)\C(C)=C\C(=N/O)\C(N)=O HCUOEKSZWPGJIM-YBRHCDHNSA-N 0.000 description 1
- 101001109689 Homo sapiens Nuclear receptor subfamily 4 group A member 3 Proteins 0.000 description 1
- 101000598778 Homo sapiens Protein OSCP1 Proteins 0.000 description 1
- 101001067395 Mus musculus Phospholipid scramblase 1 Proteins 0.000 description 1
- 102100022673 Nuclear receptor subfamily 4 group A member 3 Human genes 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000006880 cross-coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K2017/0806—Modifications for protecting switching circuit against overcurrent or overvoltage against excessive temperature
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0054—Gating switches, e.g. pass gates
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Power Conversion In General (AREA)
- Electronic Switches (AREA)
Abstract
The invention discloses an enhanced GaN power device gate drive circuit with a protection function, which comprises an interface circuit H, an interface circuit L, a dead zone generating circuit, a level shift circuit, a low-end delay matching circuit, a drive circuit H, a drive circuit L, an under-voltage blocking circuit H, an under-voltage blocking circuit L, an overcurrent protection circuit and an overheat protection circuit, wherein the dead zone generating circuit is connected with the level shift circuit; the driving circuit can automatically detect the phenomena of chip overheating, power supply voltage undervoltage or overcurrent, and close the GaN power device for protection, so that the working characteristic of the GaN power device is ensured to be in a safe area.
Description
Technical Field
The invention belongs to the field of integrated circuit design, and particularly relates to a grid driving circuit with a protection function, which is applied to a GaN power device.
Technical Field
The traditional power electronic power device based on silicon material has gradually approached its theoretical limit, and it is difficult to meet the development requirements of high frequency and high power density of power electronic technology. Compared with the traditional Si device, the GaN device shows the advantages of the GaN device in on-resistance and grid charge, and can enable the power converter to achieve smaller volume, higher frequency and higher efficiency, thereby having wide application prospects in the fields of automobiles, communication, industry and the like. The increase of the switching frequency not only can effectively reduce the sizes of a capacitor, an inductor and a transformer in a system circuit, but also can inhibit interference, reduce ripples and improve the unit gain bandwidth of a power supply system so as to improve the dynamic response performance of the power supply system. And the high-speed grid driving circuit is used for driving the GaN power device, so that the whole power converter achieves high efficiency, the circuit area is reduced, and the cost is saved.
Fig. 1 shows a block diagram of a typical GaN half-bridge drive circuit most commonly used in power modules. As shown in fig. 1, a typical GaN half-bridge driving circuit is divided into two high-side and low-side channels, and two low-voltage input channels are connected in a bootstrap boosting manner. During the conduction period of the low-side power GaN device, the switch node (SW) is pulled down to the ground, and VDD charges the bootstrap capacitor through the bootstrap diode so that the voltage difference between the two ends of the bootstrap capacitor approaches VDD. When the lower-end transistor is turned off, the high-end input signal turns on the high-end transistor, and the voltage of the switch node rises to VIN, that is, VSW rises to VIN. Since the voltage across the bootstrap capacitor is constant, the bootstrap voltage rail HB is bootstrapped to VSW + VDD. The high-side circuit always keeps VHB-VSW ≈ VDD. When HB is bootstrapped by the bootstrap capacitor, the cathode voltage of the bootstrap diode is high and higher than the anode voltage VDD, so that the bootstrap diode is reversely biased off.
The GaN power device is widely applied to GaN FETs at present, and compared with a Si MOSFET, the GaN power device mainly has the following characteristics: the on-resistance and the device volume are small under the same withstand voltage; the switching speed is high; the current density is large and the power density is high. The characteristics of the GaN FETs ensure that the GaN FETs have very wide prospects and markets in the field of future power electronic application. There are, however, some factors that need special attention: the threshold voltage is low; gate-source upper voltage limit vgs (max) low; can be turned on reversely. The above-mentioned factors to be considered in particular cause problems in driving GaN devices, so that the conventional driving circuit for MOS power devices is not suitable for GaN power devices. GaN power devices are generally used at high-frequency switching frequency (above MHz), and especially after the switching frequency reaches 10MHz, the proportion of the traditional gate drive with large delay (tens of nanoseconds) in the switching period is too large, even logic errors are caused, and the switching frequency is limited from increasing. And the ultra-high operating frequency of GaN FETs, the reliability protection of GaN FETs will become exceptionally important. Therefore, it is desirable to provide a gate driving circuit having a protection function.
Disclosure of Invention
The invention aims to overcome the defects of the conventional gate drive circuit and provides a gate drive circuit with a protection function, which is applied to a GaN power device.
The purpose of the invention can be realized by the following technical scheme:
the utility model provides a take protect function's enhancement mode gaN power device bars drive circuit which characterized by: the circuit comprises an interface circuit H, an interface circuit L, a dead zone generating circuit, a level shifting circuit, a low-end delay matching circuit, a driving circuit H, a driving circuit L, an under-voltage blocking circuit H, an under-voltage blocking circuit L, an overcurrent protection circuit and an overheat protection circuit;
the connection relationship of the enhanced GaN power device gate drive circuit with the protection function is as follows: the positive and negative logic output ends of the interface circuit H are connected to the first and second input ends of the dead zone generating circuit; the positive and negative logic output ends of the interface circuit L are connected to the third and fourth input ends of the dead zone generating circuit; the detection output end of the under-voltage lockout circuit L is connected to the fifth input end of the dead zone generating circuit; the detection output end of the overcurrent protection circuit is connected to the sixth input end of the dead zone generation circuit; the detection output end of the overheating protection circuit is connected to the seventh input end of the dead zone generation circuit; the detection output end of the under-voltage lockout circuit H is connected to the eighth input end of the dead zone generating circuit; a first output end of the dead zone generating circuit is connected to a control signal input end of the level shifting circuit, and a second output end of the dead zone generating circuit is connected to a control signal input end of the low-end delay matching circuit; the signal output end of the level shift circuit is connected to the driving circuit H; the signal output terminal of the low-side delay matching circuit is connected to the driving circuit L.
The enhanced GaN power device gate drive circuit with the protection function is characterized in that: and the H-end driving module is formed by the level shift circuit, the driving circuit H and the under-voltage blocking circuit H, and the H-end driving module is required to be arranged in a high-voltage well with floating potential.
The enhanced GaN power device gate drive circuit with the protection function is characterized in that: the detection output ends of the overcurrent protection circuit, the under-voltage blocking circuit H, the under-voltage blocking circuit L and the overheat protection circuit respectively send out OC, UV _ HH, UV _ HL and OH trigger signals; when the working state of the enhanced GaN power device gate drive circuit with the protection function is normal, OC, UV _ HH, UV _ HL and OH trigger signals are all logic low levels; when the enhanced GaN power device gate drive circuit with the protection function is overheated, an OH trigger signal sent by the over-temperature protection circuit is changed into a logic high level; when the power supply voltage of the enhanced GaN power device gate drive circuit with the protection function is under-voltage, a UV _ HH sent by the under-voltage blocking circuit H or a UV _ HL trigger signal sent by the under-voltage blocking circuit L becomes a logic high level; when the current of the gate driving circuit of the enhanced GaN power device with the protection function exceeds a set value, an OH trigger signal sent by the overcurrent protection circuit is changed into a logic high level; when any one of the OC, UV _ HH, UV _ HL and OH trigger signals or the trigger signals simultaneously change from low level to high level, the dead zone generating circuit can close the driving circuit H and the driving circuit L so as to protect the gate driving circuit of the enhanced GaN power device with the function of protecting the belt; the logic low level is a ground level and the logic high level is a level with a lower voltage level and a higher voltage level.
The enhanced GaN power device gate drive circuit with the protection function is characterized in that: the undervoltage lockout circuit H and the undervoltage lockout circuit L use the same undervoltage lockout circuit; the undervoltage lockout circuit comprises 3 voltage detection resistors, 1 bias resistor, 1 voltage clamping diode, 1 filter capacitor C1, 8 NMOS transistors and 8 PMOS transistors;
the connection relation of the undervoltage blocking circuit is as follows: the upper end of the first voltage detection resistor R1 is connected with a high-side voltage VCC, the lower end of the first voltage detection resistor R1 is connected with the upper end of the second voltage detection resistor R2, the upper end of the filter capacitor C1 and the grid end of the first NMOS transistor M1; the lower end of the second voltage detection resistor R2 is connected with the upper end of the third voltage detection resistor R3 and the drain terminal of the sixteenth NMOS transistor M16; the lower ends of the third voltage detection resistor R3 and the filter capacitor C1 are both connected with a low-side voltage COM; the drain terminal of the first NMOS transistor M1 is connected to the drain terminal and the gate terminal of the third PMOS transistor M3, and is also connected to the gate terminal of the fourth PMOS transistor M4; the source end of the first NMOS transistor M1 is connected to the source end of the second NMOS transistor M2; the gate end of the second NMOS transistor M2 is connected to the positive end of the clamp diode DZ1 and the drain end of the sixth PMOS transistor M6, and the drain end of the second NMOS transistor M2 is connected to the drain end of the fourth PMOS transistor M4 and the gate end of the ninth PMOS transistor M9; the drain terminal of the fifth NMOS transistor M5 is connected to the source terminal of the first NMOS transistor M1 and the source terminal of the second NMOS transistor M2, the gate terminal of the fifth NMOS transistor M5 is connected to the gate terminals of the tenth NMOS transistor M10 and the eleventh NMOS transistor M11, and the gate terminal of the fifth NMOS transistor M5 is further connected to the drain terminal of the tenth NMOS transistor M10 and the drain terminal of the eighth PMOS transistor M8; the gate end of the sixth PMOS transistor M6 is connected to the gate end and the drain end of the seventh PMOS transistor M7 and the upper end of a bias resistor R4; the gate end of the sixth PMOS tube M6 is also connected to the gate end of the eighth PMOS tube M8; the drain terminal of the eleventh NMOS transistor M11 is connected to the drain terminal of the ninth PMOS transistor M9, and is also connected to the gate terminals of the thirteenth NMOS transistor M13 and the twelfth PMOS transistor M12; the drain ends of a thirteenth NMOS transistor M13 and a twelfth PMOS transistor M12 are connected, and the drain ends are also connected to the gate ends of a fifteenth NMOS transistor M15 and a fourteenth PMOS transistor M14; the drain terminal of the fifteenth NMOS transistor M15 is connected to the drain terminal of the fourteenth PMOS transistor M14, and is further connected to the gate terminal of the sixteenth NMOS transistor M16; the source terminals of the other NMOS transistors except the source terminal of the first NMOS transistor M1 and the source terminal of the other NMOS transistor M2 are all connected to the low-side voltage COM, the substrate terminals of all the NMOS transistors are all connected to the low-side voltage COM, the source terminals of all the PMOS transistors are connected to the high-side voltage VCC, and the substrate terminals of all the PMOS transistors are connected to the high-side voltage VCC.
The enhanced GaN power device gate drive circuit with the protection function is characterized in that: the overheating protection circuit comprises 2 temperature detection resistors, 3 bias resistors, 1 voltage clamping diode Z91, 1 filter capacitor C91, 4 NMOS transistors and 9 PMOS transistors;
the connection relationship of the overheat protection circuit is as follows: the upper end of the first temperature detection resistor Rtd is connected to the lower end of the second temperature detection resistor Rd, and is also connected to the gate end of a ninth PMOS transistor M91; the lower end of the first temperature-detecting resistance Rtd is connected to the ground level; the upper end of the second temperature detection resistor Rd is connected to the power supply voltage; the drain terminal of the ninth PMOS transistor M91 is connected to the drain terminal and the gate terminal of the ninth third NMOS transistor M93, and is also connected to the gate terminal of the ninth fourth NMOS transistor M94; the source end of the ninth PMOS transistor M91 is connected to the source end of the ninth second PMOS transistor M92 and the drain end of the ninth fifth PMOS transistor M95; the gate end of the ninth second PMOS transistor M92 is connected to the upper end of the ninth second bias resistor R92 and the lower end of the ninth first bias resistor R91; the lower end of the ninth second bias resistor R92 is connected to the ground level; the upper end of the ninth bias resistor R91 is connected with the drain terminal of the ninth sixth PMOS tube M96 and the anode of the voltage clamping diode Z91; the negative terminal of voltage clamp diode Z91 is connected to ground; the gate end of the ninth fifth PMOS tube M95 is connected with the gate end of the ninth sixth PMOS tube M96, the gate end of the ninth seventh PMOS tube M97, the gate end of the ninth one-to-one PMOS tube M911 and the gate end of the ninth eighth PMOS tube M98, and the drain end of the ninth eighth PMOS tube M98; the drain terminal of the ninth fourth NMOS transistor M94 is connected to the drain terminal of the ninth second PMOS transistor M92, and is further connected to the drain terminal of the ninth one-to-one PMOS transistor M911 and the gate terminal of the ninth NMOS transistor M99; the drain terminal of the ninth NMOS transistor M99 is connected to the drain terminal of the ninth seventh PMOS transistor M97 and the gate terminal of the ninth zero PMOS transistor M910, and is further connected to the upper terminal of the filter capacitor C1; the first NMOS transistor M913 is connected to the first gate terminal of the first PMOS transistor M912; the source end of the ninth one-to-one PMOS transistor M911 is connected to the drain end of the ninth zero PMOS transistor M910; the lower end of the filter capacitor C91 is grounded; the ninth three NMOS transistor M913 is connected with the drain terminal of the ninth two PMOS transistor M912 and outputs a judgment signal OH; the source ends of the other PMOS tubes except the ninth PMOS tube M91, the ninth PMOS tube M92 and the ninth PMOS tube M911 are all connected with power supply voltage; the substrates of all PMOS tubes are connected with power voltage, and the source ends and the substrates of all NMOS tubes are grounded.
The enhanced GaN power device gate drive circuit with the protection function is characterized in that: the overcurrent protection circuit comprises 2 current detection resistors, 5 bias resistors, 1 voltage clamping diode Z101, 1 rectifier diode D101, 1 filter capacitor C101, 2 triodes, 7 NMOS tubes and 6 PMOS tubes;
the overcurrent protection circuit has the following connection relationship: the upper end of the first current detection resistor Rd1 is connected to the upper end of the second current detection resistor Rd2, and is also connected to the base of the first triode Q1 and the current input end to be detected; the lower end of the first current detection resistor Rd1 is connected to the lower end of the second current detection resistor Rd2 and also to the ground level; a collector of the first triode Q1 is connected to a source end of the first zero six NMOS transistor M106, and an emitter of the first triode Q1 is connected to an upper end of the first zero three bias resistor R103 and an emitter of the second triode Q2; the base electrode of the second triode Q2 is connected with the upper end of the first zero-two bias resistor R102 and the lower end of the first zero-one bias resistor R101; the lower end of the first zero-two bias resistor R102 is connected to the ground level; the upper end of the first zero first bias resistor R101 is connected with the lower end of the first zero fifth bias resistor R105 and the anode of the voltage clamping diode Z101; the negative terminal of the voltage clamp diode Z101 is connected to ground; the upper end of the first zero-five bias resistor R105 is connected with a power supply voltage; the drain end of the first zero-six NMOS transistor M106 is connected to the drain end and the gate end of the first zero-first PMOS transistor M101, and is also connected to the gate end of the first zero-two PMOS transistor M102 and the gate end of the first zero-four PMOS transistor M104; the drain end of the first zero two PMOS tube M102 is connected to the drain end of the first zero seven NMOS tube M107, the drain end and the gate end of the first zero three PMOS tube M103, and the gate end of the first zero five PMOS tube M105; the drain terminal of the first zero-four PMOS tube M104 is connected to the drain terminal of the first zero-eight NMOS tube M108; the drain end of the first zero-five PMOS tube M105 is connected to the drain end of the first zero-nine NMOS tube M109; the source end of the first zero eight NMOS transistor M8 is connected to the drain end of the first one-to-one zero NMOS transistor M110, and is also connected to the gate ends of the first one-to-three NMOS transistor M113 and the first one-to-two PMOS transistor M112; the source end of the first zero-nine NMOS transistor M109 is connected to the drain end and the gate end of the first NMOS transistor M111; the drain end of the first one-to-three NMOS tube M113 is connected with the drain end of the first one-to-two PMOS tube M112, and outputs a judgment signal OC; the lower end of the filter capacitor C101 is grounded, the upper end of the filter capacitor C101 is connected to the lower end of the first zero-four bias resistor R104 and the anode of the rectifier diode D1, the upper end of the filter capacitor C101 is also connected to the gate ends of a first zero-six NMOS transistor M106, a first zero-seven NMOS transistor M107, a first zero-eight NMOS transistor M108 and a first zero-nine NMOS transistor M109, and the upper end of the filter capacitor C101 is also connected to the source ends of a first one-to-one second PMOS transistor M112; the source ends of the other PMOS tubes except the first one-to-two PMOS tube M112 are connected with power supply voltage; the source ends of the first one-to-one NMOS transistor M111, the first zero one NMOS transistor M113 and the first one-to-zero NMOS transistor M110 are all grounded; the substrates of all PMOS tubes are connected with power voltage, and the substrates of all NMOS tubes are grounded.
The invention has the advantages that: the method can automatically detect the phenomena of overheating, undervoltage or overcurrent of the GaN power chip, and close main power consumption elements in the chip to ensure that the GaN power device is in a working safety area.
Drawings
FIG. 1 shows a block diagram of a typical GaN half-bridge drive circuit according to the prior art;
FIG. 2 is a block diagram of a gate driving circuit of the enhanced GaN power device with protection function according to the present invention;
FIG. 3 is a schematic diagram of an interface circuit of the present invention;
FIG. 4 is a schematic diagram of a dead band generation circuit of the present invention;
FIG. 5 is a schematic diagram of a level shifting circuit according to the present invention;
FIG. 6 is a schematic diagram of a low-side delay matching circuit according to the present invention;
FIG. 7 is a schematic diagram of a driving circuit of the present invention;
FIG. 8 is a schematic diagram of the under-voltage lockout circuit of the present invention;
FIG. 9 is a schematic diagram of the overheat protection circuit of the present invention;
fig. 10 is a schematic diagram of an overcurrent protection circuit according to the present invention.
Detailed Description
The present invention is described in further detail below with reference to the attached drawings and examples.
As shown in fig. 2, an enhanced GaN power device gate driving circuit with protection function includes an interface circuit H, an interface circuit L, a dead zone generating circuit, a level shifting circuit, a low-end delay matching circuit, a driving circuit H, a driving circuit L, an under-voltage blocking circuit H, an under-voltage blocking circuit L, an over-current protection circuit and an over-temperature protection circuit.
The connection relationship of the circuit shown in fig. 2 is: the positive and negative logic output ends of the interface circuit H are connected to the first and second input ends of the dead zone generating circuit; the positive and negative logic output ends of the interface circuit L are connected to the third and fourth input ends of the dead zone generating circuit; the detection output end of the under-voltage lockout circuit L is connected to the fifth input end of the dead zone generating circuit; the detection output end of the overcurrent protection circuit is connected to the sixth input end of the dead zone generation circuit; the detection output end of the overheating protection circuit is connected to the seventh input end of the dead zone generation circuit; the detection output end of the under-voltage lockout circuit H is connected to the eighth input end of the dead zone generating circuit; a first output end of the dead zone generating circuit is connected to a control signal input end of the level shifting circuit, and a second output end of the dead zone generating circuit is connected to a control signal input end of the low-end delay matching circuit; the signal output end of the level shift circuit is connected to the driving circuit H; the signal output terminal of the low-side delay matching circuit is connected to the driving circuit L.
In the circuit shown in fig. 2, two 5V input logic square wave signal input signals pass through an interface circuit, a dead zone generating circuit, a level shift circuit and a low-end delay matching circuit. The signals are converted into a driving signal with 0-5V at the L terminal and a driving signal with 5V amplitude at the H terminal and with VS as a reference, and the phases of the two signals are matched. The drive signal then enters a drive module, comprising two identical output stage drive circuits. The difference is that the H-side driving module, which is composed of the level shift circuit, the driving circuit H and the under-voltage lockout circuit H, needs to be implemented in a high-voltage well with floating potential, and the potential of the well can be floated to ultra-high voltage, such as 600V. The output stage uses a plurality of LDMOS cells connected in parallel, so that the output driving signal has certain power processing capacity. After the H-end signal passes through the level shift circuit, a certain delay is generated compared with the L-end signal, and for the application of medium and high frequency, the phase mismatch of the signals at two ends is caused in the period of time, so that the normal work of a system can be influenced. Therefore, a delay matching circuit must be added to the L-side signal path to match the phases of the two-side signals.
Because the GaN FETs have quite high working frequency, 4 protective measures are designed to ensure the reliability of the power device and prevent accidents, the GaN FETs comprise an overcurrent protection circuit, an undervoltage lockout circuit H, an undervoltage lockout circuit L and an overheat protection circuit, and the detection output ends of the 4 circuits respectively send out OC, UV _ HH, UV _ HL and OH trigger signals. When the working state of the enhanced GaN power device gate drive circuit with the protection function is normal, OC, UV _ HH, UV _ HL and OH trigger signals are all logic low levels; when the enhanced GaN power device gate drive circuit with the protection function is overheated, an OH trigger signal sent by the over-temperature protection circuit is changed into a logic high level; when the power supply voltage of the enhanced GaN power device gate drive circuit with the protection function is under-voltage, a UV _ HH sent by the under-voltage blocking circuit H or a UV _ HL trigger signal sent by the under-voltage blocking circuit L becomes a logic high level; when the current of the gate driving circuit of the enhanced GaN power device with the protection function exceeds a set value, an OH trigger signal sent by the overcurrent protection circuit is changed into a logic high level; when any one or more of the OC trigger signal, the UV HH trigger signal, the UV HL trigger signal and the OH trigger signal changes from low level to high level, the dead zone generating circuit can close the driving circuit H and the driving circuit L so as to protect the enhanced GaN power device gate driving circuit with the function of protecting the band. The logic low level is a ground level and the logic high level is a level with a lower voltage level and a higher voltage level.
Fig. 3 is a schematic diagram of an embodiment of the interface circuit of the present invention. The input port IN receives a PWM control signal, typically a 5V square wave signal, from a front-end control circuit external to the chip, which is input to the negative terminal of the comparator for comparison with a reference voltage at the positive terminal of the comparator. When the input voltage is greater than the reference voltage, the comparator outputs a low potential, the noise signal is eliminated through a filter network formed by a low-pass filter resistor and a low-pass filter capacitor, and a pure square wave signal is finally obtained, wherein the output signal OUT1 is IN phase with the input signal IN, OUT2 is IN phase opposition with IN, the amplitudes of OUT1 and OUT2 are both 15V, namely the interface circuit completes the function of level displacement of 5V-15V. The interface circuit H and the interface circuit L of the present invention can be implemented by using the circuit shown in fig. 3.
Fig. 4 is a schematic diagram of a specific implementation of the dead zone generation circuit of the present invention. The input signal comes from the output of the interface circuit, where H1 and L2 are in phase, both in phase with the input signal HIN, and H2 and L1 are in phase, both in phase with the input signal LIN. The FAULT signal is a system control signal, OC is an output of the overcurrent protection circuit, OH is an output of the overheat protection circuit, UV _ HH is an output of the under-voltage lockout circuit H, and UV _ HL is an output of the under-voltage lockout circuit L. When the FAULT signal is high, or the circuit is overheated or overcurrent or the power supply voltage is undervoltage, the output of the dead zone circuit is constant low level, and the post-stage circuit stops working until the danger of the circuit is relieved. The common way of generating the dead zone is to use a delay circuit to generate a phase difference between two input signals, and then perform logic operation on the input signals to obtain a dead zone time. The size of the dead time is determined by the delay time generated by the delay circuit, and therefore the delay circuit is the core of the dead time circuit. The delay circuit may employ an inverter and an RC network.
Fig. 5 is a schematic diagram of an embodiment of a level shift circuit according to the present invention. The high-voltage level shift circuit is a circuit structure with the largest power consumption in the whole gate driving chip, and research data show that the power consumption of the high-voltage level shift circuit accounts for more than 80% of the power consumption of the whole chip. In order to realize the level shift of high voltage, a high-voltage LDMOS device which is resistant to high voltage must be included in the circuit. The circuit comprises a pulse generating and shaping circuit, a high-voltage LDMOS device, a comparator A, a comparator B, a NOR gate NOR1, a filter circuit and an RS trigger.
The principle of operation of the circuit shown in fig. 5 is as follows: the pulse generating and shaping circuit converts an input signal OUT _ H into a narrow pulse signal, the pulses respectively correspond to the rising edge and the falling edge of the square wave, and the frequency of the signal is doubled. OUT _ H also controls the turning on and off of M51. When OUT _ H is low, the M51 tube is turned off, the LDMOS and the two resistors form a branch circuit, when the LDMOS gate electrode is at high level, the LDMOS is turned on, and the potential of the LDMOS drain terminal is VH which is lower than VB; when the LDMOS grid electrode is at a low level, the LDMOS is turned off, the branch circuit has no current, and the potential of the LDMOS drain electrode point is VB. When OUT _ H is high, the M51 tube is turned on, the resistor network is connected in parallel to the source electrode of the LDMOS, when the LDMOS gate electrode is high, the LDMOS is turned on, the potential of the LDMOS drain electrode point is VL which is lower than VB, and VL is smaller than VH; when the LDMOS grid electrode potential is low, the LDMOS is turned off. The comparator A and the comparator B respectively compare the potential of the LDMOS drain electrode with a reference voltage, output two paths of pulse signals, and obtain two paths of narrow pulses of a rising edge and a falling edge after logical operation is carried out through a NOR gate. The two paths of pulses are filtered by the filter circuit to remove interference and noise in the signals, and then are reduced into a path of square wave signals through the RS trigger, and the amplitude of the square wave signals is between VB and VS.
Fig. 6 is a schematic diagram of an implementation of the low-side delay matching circuit of the present invention. In terms of structure, the delay matching circuit is similar to the pulse shaping circuit and the filter circuit in the level shift circuit shown in fig. 5, a cross-coupling circuit is adopted firstly to enable rising edges and falling edges of signals to be steeper, and then the signals are delayed through an RC network.
Because the parasitic capacitance of the grid of the power device is large, in order to ensure that the grid capacitance can be charged and discharged quickly, and the device is in rapid saturated conduction and reliable cut-off, the output impedance of the driving circuit is required to be small, and the output current is required to be large. Therefore, the high-low end signals are added with the driving circuit at the output stage so as to enhance the current capability of the signals and reduce the output impedance of the circuit. Fig. 7 is a schematic diagram of an embodiment of the driving circuit of the present invention. The output stage drive circuit consists of a chain of inverters, M71 and M72. The branch where the M71 and M72 tubes are located determines the output current of the driving circuit and also determines the output resistance of the circuit. In normal operation, the M71 transistor and the M72 transistor are crossed and turned on, and since M71 is a PMOS device and M72 is an NMOS device, the gate driving signals of the two transistors are the same.
The undervoltage lockout circuit H and the undervoltage lockout circuit L of the present invention use the same undervoltage lockout circuit structure, and FIG. 8 is a specific implementation schematic diagram of the undervoltage lockout circuit. The voltage detection circuit comprises 3 voltage detection resistors, 1 bias resistor, 1 voltage clamping diode, 1 filter capacitor C1, 8 NMOS transistors and 8 PMOS transistors. The connection relationship of the circuit shown in fig. 8 is: the upper end of the first voltage detection resistor R1 is connected with a high-side voltage VCC, the lower end of the first voltage detection resistor R1 is connected with the upper end of the second voltage detection resistor R2, the upper end of the filter capacitor C1 and the grid end of the first NMOS transistor M1; the lower end of the second voltage detection resistor R2 is connected with the upper end of the third voltage detection resistor R3 and the drain terminal of the sixteenth NMOS transistor M16; the lower ends of the third voltage detection resistor R3 and the filter capacitor C1 are both connected with a low-side voltage COM; the drain terminal of the first NMOS transistor M1 is connected to the drain terminal and gate terminal of the third PMOS transistor M3, and is also connected to the gate terminal of the fourth PMOS transistor M4; the source end of the first NMOS transistor M1 is connected to the source end of the second NMOS transistor M2; the gate end of the second NMOS transistor M2 is connected to the positive end of the clamping diode DZ1 and the drain end of the sixth PMOS transistor M6, and the drain end of the second NMOS transistor M2 is connected to the drain end of the fourth PMOS transistor M4 and the gate end of the ninth PMOS transistor M9; the drain terminal of the fifth NMOS transistor M5 is connected to the source terminal of the first NMOS transistor M1 and the source terminal of the second NMOS transistor M2, the gate terminal of the fifth NMOS transistor M5 is connected to the gate terminals of the tenth NMOS transistor M10 and the eleventh NMOS transistor M11, and the gate terminal of the fifth NMOS transistor M5 is further connected to the drain terminal of the tenth NMOS transistor M10 and the drain terminal of the eighth PMOS transistor M8; the gate end of the sixth PMOS tube M6 is connected to the gate end and the drain end of the seventh PMOS tube M7 and the upper end of a bias resistor R4; the gate end of the sixth PMOS tube M6 is also connected to the gate end of the eighth PMOS tube M8; the drain terminal of the eleventh NMOS transistor M11 is connected to the drain terminal of the ninth PMOS transistor M9, and is also connected to the gate terminals of the thirteenth NMOS transistor M13 and the twelfth PMOS transistor M12; the drain ends of a thirteenth NMOS transistor M13 and a twelfth PMOS transistor M12 are connected, and the drain ends are also connected to the gate ends of a fifteenth NMOS transistor M15 and a fourteenth PMOS transistor M14; the drain terminal of the fifteenth NMOS transistor M15 is connected to the drain terminal of the fourteenth PMOS transistor M14, and is further connected to the gate terminal of the sixteenth NMOS transistor M16; the source terminals of the other NMOS transistors except the source terminal of the first NMOS transistor M1 and the second NMOS transistor M2 are all connected to the low-side voltage COM, the substrate terminals of all the NMOS transistors are connected to the low-side voltage COM, the source terminals of all the PMOS transistors are connected to the high-side voltage VCC, and the substrate terminals of all the PMOS transistors are connected to the high-side voltage VCC.
In fig. 8, a circuit formed by R4, DZ1, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, and M11 is a hysteresis voltage comparator, the negative terminal of the comparator is a gate terminal voltage of M1, and the positive terminal voltage of the comparator is a reference voltage VREF. The filter capacitor C1 connected to the gate terminal of M1 is used to filter out the interference of spike and glitch signals appearing on the high-side and low-side power supply voltages. The high-side and low-side power supply voltages are detected in real time by voltage detection resistors R1, R2, and R3, and the detected voltage value V _ is input to the negative terminal of the comparator and compared with a reference voltage VREF of the positive terminal of the comparator. When the power supply voltage is normal, V _ is higher than VREF, the comparator outputs a low level, UV _ L is high, UV _ H is low, and the M1 tube is turned off.
Fig. 9 is a schematic diagram of an embodiment of the overheat protection circuit according to the present invention. The temperature detection circuit comprises 2 temperature detection resistors, 3 bias resistors, 1 voltage clamping diode Z91, 1 filter capacitor C91, 4 NMOS transistors and 9 PMOS transistors.
The connection relationship of the circuit shown in fig. 9 is: the upper end of the first temperature detection resistor Rtd is connected to the lower end of the second temperature detection resistor Rd, and is also connected to the gate end of a ninth PMOS transistor M91; the lower end of the first temperature-detecting resistance Rtd is connected to the ground level; the upper end of the second temperature detection resistor Rd is connected to the power supply voltage; the drain terminal of the ninth PMOS transistor M91 is connected to the drain terminal and gate terminal of the ninth third NMOS transistor M93, and is also connected to the gate terminal of the ninth fourth NMOS transistor M94; the source end of the ninth PMOS transistor M91 is connected to the source end of the ninth second PMOS transistor M92 and the drain end of the ninth fifth PMOS transistor M95; the gate end of the ninth second PMOS transistor M92 is connected to the upper end of the ninth second bias resistor R92 and the lower end of the ninth first bias resistor R91; the lower end of the ninth second bias resistor R92 is connected to the ground level; the upper end of the ninth bias resistor R91 is connected with the drain terminal of the ninth sixth PMOS tube M96 and the anode of the voltage clamping diode Z91; the negative terminal of voltage clamp diode Z91 is connected to ground; the gate end of the ninth fifth PMOS tube M95 is connected with the gate end of the ninth sixth PMOS tube M96, the gate end of the ninth seventh PMOS tube M97, the gate end of the ninth one-to-one PMOS tube M911 and the gate end of the ninth eighth PMOS tube M98, and the drain end of the ninth eighth PMOS tube M98; the drain terminal of the ninth fourth NMOS transistor M94 is connected to the drain terminal of the ninth second PMOS transistor M92, and is also connected to the drain terminal of the ninth one PMOS transistor M911 and the gate terminal of the ninth NMOS transistor M99; the drain terminal of the ninth NMOS transistor M99 is connected to the drain terminal of the ninth seventh PMOS transistor M97 and the gate terminal of the ninth zero PMOS transistor M910, and is further connected to the upper terminal of the filter capacitor C1; the first NMOS transistor M913 is connected to the first gate terminal of the first PMOS transistor M912; the source end of the ninth one-to-one PMOS transistor M911 is connected to the drain end of the ninth zero PMOS transistor M910; the lower end of the filter capacitor C91 is grounded; the ninth three NMOS transistor M913 is connected with the drain terminal of the ninth two PMOS transistor M912 and outputs a judgment signal OH; the source ends of the other PMOS tubes except the ninth PMOS tube M91, the ninth PMOS tube M92 and the ninth PMOS tube M911 are all connected with power supply voltage; the substrates of all PMOS tubes are connected with power voltage, and the source ends and the substrates of all NMOS tubes are grounded.
In fig. 9, a circuit including R91, R92, R93, Z91, C91, M91, M92, M93, M94, M95, M96, M97, M98, M99, M910, M911, M912, and M913 is a hysteresis voltage comparator. The negative end of the comparator is the detection voltage SD; the positive terminal of the comparator is a reference voltage SR. The temperature detection resistor Rtd is a thermistor and is used for detecting the temperature. The temperature detection is divided by the resistors Rd and Rtd to obtain the detection voltage SD.
Fig. 10 is a schematic diagram of an embodiment of the overcurrent protection circuit of the present invention. The current detection circuit comprises 2 current detection resistors, 5 bias resistors, 1 voltage clamping diode Z101, 1 rectifier diode D101, 1 filter capacitor C101, 2 triodes, 7 NMOS transistors and 6 PMOS transistors.
The connection relationship of the overcurrent protection circuit shown in fig. 10 is: the upper end of the first current detection resistor Rd1 is connected to the upper end of the second current detection resistor Rd2, and is also connected to the base of the first triode Q1 and the current input end to be detected; the lower end of the first current detection resistor Rd1 is connected to the lower end of the second current detection resistor Rd2 and also to the ground level; a collector of the first triode Q1 is connected to a source end of the first zero six NMOS transistor M106, and an emitter of the first triode Q1 is connected to an upper end of the first zero three bias resistor R103 and an emitter of the second triode Q2; the base electrode of the second triode Q2 is connected with the upper end of the first zero-two bias resistor R102 and the lower end of the first zero-one bias resistor R101; the lower end of the first zero-two bias resistor R102 is connected to the ground level; the upper end of the first zero first bias resistor R101 is connected with the lower end of the first zero fifth bias resistor R105 and the anode of the voltage clamping diode Z101; the negative terminal of the voltage clamp diode Z101 is connected to ground; the upper end of the first zero-five bias resistor R105 is connected with a power supply voltage; the drain end of the first zero-six NMOS transistor M106 is connected to the drain end and the gate end of the first zero-first PMOS transistor M101, and is also connected to the gate end of the first zero-two PMOS transistor M102 and the gate end of the first zero-four PMOS transistor M104; the drain end of the first zero two PMOS tube M102 is connected to the drain end of the first zero seven NMOS tube M107, the drain end and the gate end of the first zero three PMOS tube M103, and the gate end of the first zero five PMOS tube M105; the drain terminal of the first zero-four PMOS tube M104 is connected to the drain terminal of the first zero-eight NMOS tube M108; the drain end of the first zero-five PMOS tube M105 is connected to the drain end of the first zero-nine NMOS tube M109; the source end of the first zero eight NMOS transistor M8 is connected to the drain end of the first one-to-one zero NMOS transistor M110, and is also connected to the gate ends of the first one-to-three NMOS transistor M113 and the first one-to-two PMOS transistor M112; the source end of the first zero-nine NMOS transistor M109 is connected to the drain end and the gate end of the first NMOS transistor M111; the drain end of the first one-to-three NMOS tube M113 is connected with the drain end of the first one-to-two PMOS tube M112, and outputs a judgment signal OC; the lower end of the filter capacitor C101 is grounded, the upper end of the filter capacitor C101 is connected to the lower end of the first zero-four bias resistor R104 and the anode of the rectifier diode D1, the upper end of the filter capacitor C101 is also connected to the gate ends of a first zero-six NMOS transistor M106, a first zero-seven NMOS transistor M107, a first zero-eight NMOS transistor M108 and a first zero-nine NMOS transistor M109, and the upper end of the filter capacitor C101 is also connected to the source ends of a first one-to-one second PMOS transistor M112; the source ends of the other PMOS tubes except the first one-to-two PMOS tube M112 are connected with power supply voltage; the source ends of the first one-to-one NMOS transistor M111, the first zero-to-one NMOS transistor M113 and the first one-to-zero NMOS transistor M110 are all grounded; the substrates of all PMOS tubes are connected with power voltage, and the substrates of all NMOS tubes are grounded.
In fig. 10, a circuit including R101, R102, R103, R104, R105, Q1, Q2, Z101, C101, D101, M102, M103, M104, M105, M106, M107, M108, M109, M110, M111, M112, and M113 is a hysteresis voltage comparator. After the current to be detected passes through 2 current detection resistors Rd1 and Rd2 which are connected in parallel, the detection voltage Vt is obtained. The current detection resistor Rd2 is a variable resistor for adjusting the current detection range and the overcurrent threshold. The negative terminal of the comparator is the base voltage of Q1, which is the detection voltage Vt; the positive terminal of the comparator is the base voltage of Q2, which is the reference voltage REF. The filter capacitors C101 connected to the gate terminals of M106, M107, M108 and M109 are used to filter the interference of spike and glitch signals appearing on the power supply voltage. The current to be detected output by the GaN device is detected by the current detection resistors Rd1 and Rd2 in real time, and the detected voltage value Vt is input to the negative terminal of the comparator and compared with the reference voltage REF of the positive terminal of the comparator. When the current is normal, Vt is lower than VREF and the comparator outputs a low level. When the current starts to become large, Vt starts to become high, and after feedback to the comparator, the comparator state changes and Rd2 is controlled to increase, so that Vt further increases, thereby further locking the state of the circuit and keeping the output unchanged. When the current slowly recovers, Vt is lower than REF and the comparator output voltage flips.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (3)
1. The utility model provides a take protect function's enhancement mode gaN power device bars drive circuit which characterized by: the circuit comprises an interface circuit H, an interface circuit L, a dead zone generating circuit, a level shifting circuit, a low-end delay matching circuit, a driving circuit H, a driving circuit L, an under-voltage blocking circuit H, an under-voltage blocking circuit L, an overcurrent protection circuit and an overheat protection circuit;
the connection relationship of the enhanced GaN power device gate drive circuit with the protection function is as follows: the positive and negative logic output ends of the interface circuit H are connected to the first and second input ends of the dead zone generating circuit; the positive and negative logic output ends of the interface circuit L are connected to the third and fourth input ends of the dead zone generating circuit; the detection output end of the under-voltage lockout circuit L is connected to the fifth input end of the dead zone generating circuit; the detection output end of the overcurrent protection circuit is connected to the sixth input end of the dead zone generation circuit; the detection output end of the overheating protection circuit is connected to the seventh input end of the dead zone generation circuit; the detection output end of the under-voltage blocking circuit H is connected to the eighth input end of the dead zone generating circuit; a first output end of the dead zone generating circuit is connected to a control signal input end of the level shifting circuit, and a second output end of the dead zone generating circuit is connected to a control signal input end of the low-end delay matching circuit; the signal output end of the level shift circuit is connected to the driving circuit H; the signal output end of the low-end delay matching circuit is connected to the driving circuit L;
the level shift circuit, the driving circuit H and the under-voltage blocking circuit H form an H-end driving module, and the H-end driving module needs to be arranged in a high-voltage well with floating potential;
the overcurrent protection circuit comprises 2 current detection resistors, 5 bias resistors, 1 voltage clamping diode Z101, 1 rectifier diode D101, 1 filter capacitor C101, 2 triodes, 7 NMOS tubes and 6 PMOS tubes;
the overcurrent protection circuit has the following connection relationship: the upper end of the first current detection resistor Rd1 is connected to the upper end of the second current detection resistor Rd2, and is also connected to the base of the first triode Q1 and the current input end to be detected; the lower end of the first current detection resistor Rd1 is connected to the lower end of the second current detection resistor Rd2 and also to the ground level; a collector of the first triode Q1 is connected to a source end of the first zero six NMOS transistor M106, and an emitter of the first triode Q1 is connected to an upper end of the first zero three bias resistor R103 and an emitter of the second triode Q2; the base electrode of the second triode Q2 is connected with the upper end of the first zero-two bias resistor R102 and the lower end of the first zero-one bias resistor R101; the lower end of the first zero-two bias resistor R102 is connected to the ground level; the upper end of the first zero first bias resistor R101 is connected with the lower end of the first zero fifth bias resistor R105 and the anode of the voltage clamping diode Z101; the negative terminal of the voltage clamp diode Z101 is connected to ground; the upper end of the first zero-five bias resistor R105 is connected with a power supply voltage; the drain end of the first zero-six NMOS transistor M106 is connected to the drain end and the gate end of the first zero-first PMOS transistor M101, and is also connected to the gate end of the first zero-two PMOS transistor M102 and the gate end of the first zero-four PMOS transistor M104; the drain end of the first zero two PMOS tube M102 is connected to the drain end of the first zero seven NMOS tube M107, the drain end and the gate end of the first zero three PMOS tube M103, and the gate end of the first zero five PMOS tube M105; the drain terminal of the first zero-fourth PMOS transistor M104 is connected to the drain terminal of the first zero-eight NMOS transistor M108; the drain end of the first zero-five PMOS tube M105 is connected to the drain end of the first zero-nine NMOS tube M109; the source end of the first zero eight NMOS transistor M8 is connected to the drain end of the first one-to-one zero NMOS transistor M110, and is also connected to the gate ends of the first one-to-three NMOS transistor M113 and the first one-to-two PMOS transistor M112; the source end of the first zero-nine NMOS transistor M109 is connected to the drain end and the gate end of the first NMOS transistor M111; the drain end of the first one-to-three NMOS tube M113 is connected with the drain end of the first one-to-two PMOS tube M112, and outputs a judgment signal OC; the lower end of the filter capacitor C101 is grounded, the upper end of the filter capacitor C101 is connected to the lower end of the first zero-four bias resistor R104 and the anode of the rectifier diode D1, the upper end of the filter capacitor C101 is also connected to the gate ends of a first zero-six NMOS transistor M106, a first zero-seven NMOS transistor M107, a first zero-eight NMOS transistor M108 and a first zero-nine NMOS transistor M109, and the upper end of the filter capacitor C101 is also connected to the source ends of a first one-to-one second PMOS transistor M112; the source ends of the other PMOS tubes except the first one-to-two PMOS tube M112 are connected with power supply voltage; the source ends of the first one-to-one NMOS transistor M111, the first zero one NMOS transistor M113 and the first one-to-zero NMOS transistor M110 are all grounded; the substrates of all PMOS tubes are connected with power supply voltage, and the substrates of all NMOS tubes are grounded.
2. The gate driving circuit of an enhanced GaN power device with protection function of claim 1, wherein: the undervoltage lockout circuit H and the undervoltage lockout circuit L use the same undervoltage lockout circuit; the undervoltage lockout circuit comprises 3 voltage detection resistors, 1 bias resistor, 1 voltage clamping diode, 1 filter capacitor C1, 8 NMOS transistors and 8 PMOS transistors;
the connection relation of the undervoltage blocking circuit is as follows: the upper end of the first voltage detection resistor R1 is connected with a high-side voltage VCC, the lower end of the first voltage detection resistor R1 is connected with the upper end of the second voltage detection resistor R2, the upper end of the filter capacitor C1 and the grid end of the first NMOS transistor M1; the lower end of the second voltage detection resistor R2 is connected with the upper end of the third voltage detection resistor R3 and the drain end of the sixteenth NMOS transistor M16; the lower ends of the third voltage detection resistor R3 and the filter capacitor C1 are both connected with a low-side voltage COM; the drain terminal of the first NMOS transistor M1 is connected to the drain terminal and the gate terminal of the third PMOS transistor M3, and is also connected to the gate terminal of the fourth PMOS transistor M4; the source end of the first NMOS transistor M1 is connected to the source end of the second NMOS transistor M2; the gate end of the second NMOS transistor M2 is connected to the positive end of the clamping diode DZ1 and the drain end of the sixth PMOS transistor M6, and the drain end of the second NMOS transistor M2 is connected to the drain end of the fourth PMOS transistor M4 and the gate end of the ninth PMOS transistor M9; the drain terminal of the fifth NMOS transistor M5 is connected to the source terminal of the first NMOS transistor M1 and the source terminal of the second NMOS transistor M2, the gate terminal of the fifth NMOS transistor M5 is connected to the gate terminals of the tenth NMOS transistor M10 and the eleventh NMOS transistor M11, and the gate terminal of the fifth NMOS transistor M5 is further connected to the drain terminal of the tenth NMOS transistor M10 and the drain terminal of the eighth PMOS transistor M8; the gate end of the sixth PMOS tube M6 is connected to the gate end and the drain end of the seventh PMOS tube M7 and the upper end of a bias resistor R4; the gate end of the sixth PMOS tube M6 is also connected to the gate end of the eighth PMOS tube M8; the drain terminal of the eleventh NMOS transistor M11 is connected to the drain terminal of the ninth PMOS transistor M9, and is also connected to the gate terminals of the thirteenth NMOS transistor M13 and the twelfth PMOS transistor M12; the drain ends of a thirteenth NMOS transistor M13 and a twelfth PMOS transistor M12 are connected, and the drain ends are also connected to the gate ends of a fifteenth NMOS transistor M15 and a fourteenth PMOS transistor M14; the drain terminal of the fifteenth NMOS transistor M15 is connected to the drain terminal of the fourteenth PMOS transistor M14, and is further connected to the gate terminal of the sixteenth NMOS transistor M16; the source terminals of the other NMOS transistors except the source terminal of the first NMOS transistor M1 and the source terminal of the other NMOS transistor M2 are all connected to the low-side voltage COM, the substrate terminals of all the NMOS transistors are all connected to the low-side voltage COM, the source terminals of all the PMOS transistors are connected to the high-side voltage VCC, and the substrate terminals of all the PMOS transistors are connected to the high-side voltage VCC.
3. The gate driving circuit of an enhanced GaN power device with protection function as claimed in claim 1, wherein: the overheating protection circuit comprises 2 temperature detection resistors, 3 bias resistors, 1 voltage clamping diode Z91, 1 filter capacitor C91, 4 NMOS transistors and 9 PMOS transistors;
the connection relationship of the overheat protection circuit is as follows: the upper end of the first temperature detection resistor Rtd is connected to the lower end of the second temperature detection resistor Rd, and is also connected to the gate end of a ninth PMOS transistor M91; the lower end of the first temperature-detecting resistance Rtd is connected to the ground level; the upper end of the second temperature detection resistor Rd is connected to the power supply voltage; the drain terminal of the ninth PMOS transistor M91 is connected to the drain terminal and the gate terminal of the ninth third NMOS transistor M93, and is also connected to the gate terminal of the ninth fourth NMOS transistor M94; the source end of the ninth PMOS transistor M91 is connected to the source end of the ninth second PMOS transistor M92 and the drain end of the ninth fifth PMOS transistor M95; the gate end of the ninth second PMOS transistor M92 is connected to the upper end of the ninth second bias resistor R92 and the lower end of the ninth first bias resistor R91; the lower end of the ninth second bias resistor R92 is connected to the ground level; the upper end of the ninth bias resistor R91 is connected with the drain terminal of the ninth sixth PMOS tube M96 and the anode of the voltage clamping diode Z91; the negative terminal of the voltage clamp diode Z91 is connected to ground; the gate end of the ninth fifth PMOS tube M95 is connected with the gate end of the ninth sixth PMOS tube M96, the gate end of the ninth seventh PMOS tube M97, the gate end of the ninth one-to-one PMOS tube M911 and the gate end of the ninth eighth PMOS tube M98, and the drain end of the ninth eighth PMOS tube M98; the drain terminal of the ninth fourth NMOS transistor M94 is connected to the drain terminal of the ninth second PMOS transistor M92, and is further connected to the drain terminal of the ninth one-to-one PMOS transistor M911 and the gate terminal of the ninth NMOS transistor M99; the drain terminal of the ninth NMOS transistor M99 is connected to the drain terminal of the ninth seventh PMOS transistor M97 and the gate terminal of the ninth zero PMOS transistor M910, and is further connected to the upper terminal of the filter capacitor C1; the first NMOS transistor M913 is connected to the first gate terminal of the first PMOS transistor M912; the source end of the ninth one-to-one PMOS transistor M911 is connected to the drain end of the ninth zero PMOS transistor M910; the lower end of the filter capacitor C91 is grounded; the ninth three NMOS transistor M913 is connected with the drain terminal of the ninth two PMOS transistor M912 and outputs a judgment signal OH; the source ends of the other PMOS tubes except the ninth PMOS tube M91, the ninth PMOS tube M92 and the ninth PMOS tube M911 are all connected with power supply voltage; the substrates of all PMOS tubes are connected with power voltage, and the source ends and the substrates of all NMOS tubes are grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811424613.2A CN109495095B (en) | 2018-11-27 | 2018-11-27 | Enhanced GaN power device gate drive circuit with protection function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811424613.2A CN109495095B (en) | 2018-11-27 | 2018-11-27 | Enhanced GaN power device gate drive circuit with protection function |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109495095A CN109495095A (en) | 2019-03-19 |
| CN109495095B true CN109495095B (en) | 2022-08-30 |
Family
ID=65696750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811424613.2A Active CN109495095B (en) | 2018-11-27 | 2018-11-27 | Enhanced GaN power device gate drive circuit with protection function |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109495095B (en) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109951178B (en) * | 2019-04-03 | 2020-07-31 | 电子科技大学 | System protection method of GaN gate drive circuit |
| CN110138367B (en) * | 2019-05-16 | 2020-12-08 | 东南大学 | Gate drive circuit for reducing reverse recovery current of power device |
| CN110729990B (en) * | 2019-09-29 | 2023-08-22 | 上海艾为电子技术股份有限公司 | Bootstrap circuit supporting rapid charge and discharge and chip |
| WO2021174524A1 (en) * | 2020-03-06 | 2021-09-10 | 香港科技大学深圳研究院 | Overcurrent protection circuit of gallium nitride power device and method for improving response speed |
| CN113541451B (en) * | 2020-04-21 | 2022-07-26 | 复旦大学 | A high-frequency intelligent half-bridge grid drive circuit for enhancement mode gaN HEMT |
| CN111490667B (en) * | 2020-04-21 | 2021-11-16 | 黄山学院 | High-voltage half-bridge gate driving circuit |
| CN111506149B (en) * | 2020-04-24 | 2021-12-07 | 江苏芯力特电子科技有限公司 | High-precision high-reliability under-voltage protection circuit |
| WO2021255729A1 (en) * | 2020-06-15 | 2021-12-23 | Ariel Scientific Innovations Ltd. | Control circuit for ring oscillator-based power controller |
| CN113162373B (en) * | 2021-01-15 | 2022-05-24 | 电子科技大学 | full-GaN integrated gate drive circuit with dead time control |
| CN113067567B (en) * | 2021-03-31 | 2024-04-30 | 江苏中科汉韵半导体有限公司 | Ultra-high voltage insulation isolation SiC MOSFET gate driving circuit |
| CN113098456B (en) * | 2021-03-31 | 2022-05-06 | 无锡英诺赛思科技有限公司 | High-performance chip state monitoring protection circuit for high-voltage integrated circuit |
| CN113078801B (en) * | 2021-03-31 | 2022-04-05 | 无锡英诺赛思科技有限公司 | Ultrahigh-voltage insulated isolation IGBT half-bridge gate driving circuit |
| CN113162378B (en) * | 2021-03-31 | 2022-09-30 | 黄山学院 | Intelligent high-voltage insulation isolation half-bridge gate driving circuit |
| CN113067566B (en) * | 2021-03-31 | 2024-04-30 | 江苏中科汉韵半导体有限公司 | High-voltage insulating isolation SiC MOSFET gate driving circuit with protection function |
| CN113098471B (en) * | 2021-03-31 | 2022-04-05 | 无锡英诺赛思科技有限公司 | Ultra-high-speed insulated isolation GaN half-bridge gate driving circuit |
| CN117498854B (en) * | 2023-09-20 | 2024-06-21 | 北京芯可鉴科技有限公司 | IGBT driving circuit and chip |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102412710A (en) * | 2011-11-14 | 2012-04-11 | 浙江海得新能源有限公司 | IGBT (Insulated Gate Bipolar Transistor) module driving circuit suitable for high-power inverter |
| CN103575964A (en) * | 2012-07-19 | 2014-02-12 | 快捷半导体(苏州)有限公司 | Over-current detection circuit and method for power switch tube |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06109780A (en) * | 1992-09-30 | 1994-04-22 | Nec Ic Microcomput Syst Ltd | Comparator circuit |
| JP3210875B2 (en) * | 1996-12-25 | 2001-09-25 | ニッタン株式会社 | Compensated fire detector |
| JP4797637B2 (en) * | 2006-01-16 | 2011-10-19 | サンケン電気株式会社 | Resonant switching power supply |
| CN101165983B (en) * | 2006-10-16 | 2010-06-09 | 安凯(广州)微电子技术有限公司 | Current limiting short circuit protection circuit |
| CN101237182A (en) * | 2008-02-19 | 2008-08-06 | 北京中星微电子有限公司 | A method for forming the standard voltage of under-voltage lock circuit and its circuit |
| JP5107790B2 (en) * | 2008-04-28 | 2012-12-26 | ラピスセミコンダクタ株式会社 | regulator |
| JP5287261B2 (en) * | 2009-01-07 | 2013-09-11 | 富士電機株式会社 | DC-DC converter |
| CN102427221A (en) * | 2011-12-23 | 2012-04-25 | 中冶南方（武汉）自动化有限公司 | IGBT (insulated gate bipolar transistor) driving integrated protection blocking circuit |
| CN102709883B (en) * | 2012-05-11 | 2014-08-06 | 东南大学 | Under-voltage protection circuit of switch power source |
| CN102904220B (en) * | 2012-11-07 | 2015-05-06 | 东南大学 | Under-voltage protection method of high-voltage half-bridge driving chip and high-voltage half-bridge circuit |
| CN103199846B (en) * | 2013-03-26 | 2016-02-24 | 浙江工业大学 | The sluggish thermal-shutdown circuit of CMOS |
| KR101508428B1 (en) * | 2013-08-05 | 2015-04-07 | 인하대학교 산학협력단 | To Output Ripple Voltage Control the Hysteretic Buck Converter Using Thermister |
| CN103917012B (en) * | 2013-10-22 | 2016-04-20 | 新乡学院 | A kind of white LED driver system with under-voltage locking and overheat protector module |
| US9300199B2 (en) * | 2013-11-18 | 2016-03-29 | System General Corporation | Under-voltage protection circuit for programmable power supplies |
| CN104679092B (en) * | 2015-01-29 | 2016-04-06 | 电子科技大学 | The excess temperature delay protection circuit of wide power voltage |
| CN205160194U (en) * | 2015-11-20 | 2016-04-13 | 苏州太阳都信息科技有限公司 | Power supply system is synthesized to fire control host computer that possesses activestandby electrical detection circuitry |
| CN105827223B (en) * | 2016-02-23 | 2018-10-12 | 东南大学 | A kind of High pressure areas coefficient and its process structure of integrated bootstrapping |
| CN106532629B (en) * | 2016-12-29 | 2018-09-21 | 电子科技大学 | A kind of current foldback circuit with self-recovering function |
| CN207399023U (en) * | 2017-09-13 | 2018-05-22 | 深圳市鹏源电子有限公司 | For the driving device of power switch pipe |
| CN108155903B (en) * | 2017-11-22 | 2020-10-09 | 中山大学 | High-speed high-voltage level conversion circuit applied to GaN grid drive |
| CN208015586U (en) * | 2018-03-12 | 2018-10-26 | 无锡安趋电子有限公司 | A kind of anti-straight-through protection adaptive dead zone circuit and the driving circuit comprising the circuit |
| CN108494234B (en) * | 2018-04-09 | 2020-05-01 | 电子科技大学 | Floating power rail suitable for GaN high-speed gate drive circuit |
-
2018
- 2018-11-27 CN CN201811424613.2A patent/CN109495095B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102412710A (en) * | 2011-11-14 | 2012-04-11 | 浙江海得新能源有限公司 | IGBT (Insulated Gate Bipolar Transistor) module driving circuit suitable for high-power inverter |
| CN103575964A (en) * | 2012-07-19 | 2014-02-12 | 快捷半导体(苏州)有限公司 | Over-current detection circuit and method for power switch tube |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109495095A (en) | 2019-03-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109495095B (en) | Enhanced GaN power device gate drive circuit with protection function | |
| CN211930609U (en) | SiC MOSFET short-circuit protection circuit based on short-circuit current suppression | |
| JP3429937B2 (en) | Semiconductor device | |
| US8537515B2 (en) | Driving circuit and semiconductor device with the driving circuit | |
| US20150035569A1 (en) | Semiconductor element module and gate drive circuit | |
| CN113098240B (en) | Driving circuit of Casode type GaN power device | |
| CN110838787B (en) | SiC MOSFET active driving circuit for improving driving performance | |
| US11652399B2 (en) | Miller clamp protection circuit, driving circuit, driving chip and intelligent IGBT module | |
| AU1946300A (en) | Gate circuit for insulated gate semiconductor device | |
| CN111049100B (en) | Bootstrap circuit with clamping function | |
| US9912331B2 (en) | Gate driver that drives with a sequence of gate resistances | |
| CN108092493B (en) | SiC MOSFET series circuit | |
| CN115173676B (en) | SiC MOSFET driving circuit for inhibiting overshoot peak | |
| CN111725974B (en) | Two-path driving signal generating circuit with adjustable dead time | |
| CN113030554A (en) | Zero current detection circuit and detection method thereof | |
| WO2017016319A1 (en) | Dv/dt detection and protection apparatus and method | |
| KR20050072673A (en) | Semiconductor device and semiconductor device module | |
| CN107947774A (en) | LDMOS level shift dv/dt noise suppression circuits for IGBT grid drive chips | |
| JP2009054639A (en) | Power converting device | |
| US20120229200A1 (en) | Gate drive circuit and power semiconductor module | |
| CN113054622B (en) | High-precision wide-voltage-range over-temperature protection circuit for high-voltage gate driving chip | |
| CN116192109B (en) | Hierarchical turn-off driving circuit, device and safety chip | |
| CN116449249A (en) | Silicon carbide MOSFET short circuit detection circuit and device | |
| Zhou et al. | A low cost gate driver with dynamic turn-off transient control for HEV/EV traction inverter application | |
| Ming et al. | A high-reliability half-bridge GaN FET gate driver with advanced floating bias control techniques |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Enhanced GaN power device gate driver circuit with protection function Granted publication date: 20220830 Pledgee: Qimen County Sub branch of Postal Savings Bank of China Co.,Ltd. Pledgor: HUANGSHAN QIMEN XINFEI ELECTRONIC TECHNOLOGY DEVELOPMENT Co.,Ltd. Registration number: Y2024980040706 |