CN113067567B

CN113067567B - Ultra-high voltage insulation isolation SiC MOSFET gate driving circuit

Info

Publication number: CN113067567B
Application number: CN202110347567.6A
Authority: CN
Inventors: 陈珍海; 袁述; 卢基存; 黎力
Original assignee: Jiangsu Zhongkehanyun Semiconductor Co ltd
Current assignee: Jiangsu Zhongkehanyun Semiconductor Co ltd
Priority date: 2021-03-31
Filing date: 2021-03-31
Publication date: 2024-04-30
Anticipated expiration: 2041-03-31
Also published as: CN113067567A

Abstract

The invention discloses an ultra-high voltage insulation isolation SiC MOSFET gate driving circuit, which comprises: the device comprises an input receiving circuit, a digital control circuit, a modulation transmitting circuit, a high-voltage isolation circuit, a high common mode transient suppression differential signal receiving circuit, an output driving circuit, a transmitting end low voltage generating circuit, a receiving end low voltage generating circuit and a chip state monitoring circuit. The ultra-high voltage insulation isolation SiC MOSFET gate driving circuit provided by the invention adopts a high-voltage insulation isolation technology on one hand, and can realize an ultra-high voltage withstand insulation capacitor; on the other hand, the magnitude of the ground potential common mode transient noise can be automatically detected, and errors generated by the common mode transient noise can be dynamically compensated when the noise exceeds a threshold value. The invention can be widely applied to driving various high-voltage SiC MOSFET and IGBT devices.

Description

Ultra-high voltage insulation isolation SiC MOSFET gate driving circuit

Technical Field

The invention relates to an ultra-high voltage insulation isolation SiC MOSFET gate driving circuit, and belongs to the technical field of integrated circuits.

Background

Under the traction of emerging industries such as smart grids, mobile communication, and new energy automobiles, power electronics application systems require further improvements in efficiency, miniaturization, and increased functionality of the systems, particularly requiring the system to be equipped with micro-inverters that trade-off between size, quality, power, and efficiency, such as server power management, battery chargers, and solar farm. With the advent and popularity of Si-based superjunction MOSFETs and Insulated Gate Bipolar Transistors (IGBTs), silicon devices have begun to be unsuitable for some high voltage, high temperature, high efficiency and high power density applications due to their own physical characteristics limitations. Compared with Si materials, the higher thermal conductivity of the SiC materials determines the characteristic of high current density, and the higher forbidden bandwidth determines the high breakdown field strength and the high working temperature of the SiC devices. Especially in development and application of SiC MOSFET, compared with Si MOSFET with the same power level, the on-resistance and switching loss of the SiC MOSFET are greatly reduced, and the SiC MOSFET is suitable for higher working frequency, and in addition, the high-temperature stability is greatly improved due to the high-temperature working characteristic.

Because the characteristics of the SiC MOSFET device are greatly different from those of the traditional Si MOSFET, the performance of the SiC MOSFET driving circuit plays a vital role on the whole system. The new generation of power electronic complete machine system based on SiC devices brings higher demands to the driving speed and the intellectualization of a high-voltage gate driving chip, thereby further improving the reliability of the complete machine and reducing the design complexity of the complete machine system. Compared with Si MOSFETs, siC MOSFETs have smaller parasitic capacitance, and the difference between the parasitic capacitance and the parasitic capacitance is more than ten times, so that the SiC MOSFETs are more sensitive to parasitic parameters of a driving circuit. On the other hand, the driving voltage range of SiC MOSFETs is typically-5V to +25v, whereas the driving voltage range of conventional Si MOSFETs is-30V to +30v. Therefore, siC MOSFETs have smaller safety thresholds than conventional Si MOSFETs, and a voltage spike in the drive circuit is likely to break down the oxide layer between the gate sources, which is also a careful design of the output control level of the drive circuit.

The high-voltage gate driving chip is used for meeting the requirement of conversion driving between a low-power level signal provided by an output interface of the CPU controller and a high-voltage high-current signal required by gate driving of a high-power output device. The core function of the gate drive IC in the whole system is to convert the low-power level signal (1 mA/3-5V) output by the CPU controller into the high-voltage high-current signal (0.5-5A/5-20V) required by the gate drive of the high-power device, amplify the output current and the output voltage swing, and because the high-voltage and low-voltage area circuits are also in signal connection, an isolation area signal transmission module which is responsible for the signal transmission function between two sides of the isolation area is needed in the chip. Because of the large difference in application scenarios of the power semiconductor device, the voltage difference of VH between the maximum values of the high/low voltage regions can span from 40V to 6500V, the current spans from several amperes to hundreds of amperes, the switching frequency spans from several KHz to several MHz, and the performance and cost requirements of different application scenarios on the gate drive IC are completely different. The VH size directly determines the level of electrical isolation inside the chip, while implementing different levels of electrical isolation constituent circuits inside the chip, there are large differences in the technology and cost quality levels of the circuit devices that need to be employed. The high-voltage electrical isolation technology for the gate drive IC mainly comprises a single-chip integrated isolation technology and a physical insulation isolation technology. The monolithic integration isolation technology is mainly PN junction isolation technology, and the PN junction isolation technology is commonly used for realizing monolithic integration gate drive IC products below 650V; the insulation isolation technology isolates the high-low voltage signal processing circuit in physical space, and can realize ultra-high voltage electrical isolation exceeding 6500V.

Fig. 1 shows a schematic diagram of a capacitive isolation driving circuit architecture in the prior art, in which two signal communication modules: the transmitting-side circuit and the receiving-side circuit are connected to ground voltages Vgnd1 and Vgnd2, respectively, wherein an isolation circuit 20 is provided to isolate the two ground voltages Vgnd1 and Vgnd 2. As is well known, DI is the input of a capacitive isolation drive circuit and RO is the output thereof. In the signal transmission process, firstly, the input DI controls the transmitting end circuit to generate a group of differential signals, the differential signals from the transmitting end are coupled to the receiving end circuit through 2 groups of isolation capacitors arranged between the transmitting end circuit and the receiving end circuit, and the output signals RO are obtained through signal demodulation and output driving. However, since there is typically some degree of common mode transient noise between the two ground voltages Vgnd1 and Vgnd2, errors in the signal will occur during transmission. For example, a spike (spike) between two ground voltages, a power loop, or a loss on any system is one of the common transient noise factors. It is generally defined that the common mode transient noise VGND is equal to the voltage difference of (VGND 1-VGND 2) and will periodically ramp up from 0V to 1200V and then ramp down from 1200V to 0V for a typical application scenario of a 1200V SiC MOSFET. Then under the interference of the common mode transient noise VGND, the voltage of the receiving end Vcm will generate peak error, which inevitably causes data errors of the receiving end circuit, and the influence of the common mode transient noise will further worsen as the switching frequency increases. Therefore, to achieve highly reliable driving of SiC MOSFET devices, effective suppression of common mode transient noise is necessary.

Disclosure of Invention

Aiming at the driving application requirement of a SiC MOSFET device, the invention overcomes the defects existing in the prior art and provides an ultrahigh voltage insulating isolation gate driving circuit which is based on an insulating isolation technology and has high common mode transient noise suppression characteristic.

According to the technical scheme provided by the invention, the ultra-high voltage insulation isolation SiC MOSFET gate driving circuit comprises: the device comprises an input receiving circuit, a digital control circuit, a modulation transmitting circuit, an isolating circuit, a high common mode transient suppression differential signal receiving circuit, an output driving circuit, a transmitting end low voltage generating circuit, a receiving end low voltage generating circuit and a chip state monitoring circuit, wherein the input receiving circuit, the digital control circuit, the modulation transmitting circuit, the transmitting end low voltage generating circuit and the chip state monitoring circuit form a driving circuit transmitting end circuit, and the high common mode transient suppression differential signal receiving circuit, the output driving circuit and the receiving end low voltage generating circuit form a driving circuit receiving end circuit; the ground potentials of all circuits in the driving circuit transmitting end circuit are connected to the transmitting end ground voltage Vgnd1, and the ground potentials of all circuits in the driving circuit receiving end circuit are connected to the receiving end ground voltage Vgnd2; the isolation circuit comprises a positive end transmitting capacitor Ctp, a negative end transmitting capacitor Ctn, a positive end receiving capacitor Crp and a negative end receiving capacitor Crn;

the input receiving circuit receives external low-level logic input data DI, converts the DI into input data Din with a high level VCC, and outputs the input data Din to the digital control circuit; the digital control circuit processes input data Din into a group of differential data DxP and DxN according to the states of an undervoltage protection signal UVLO, an overtemperature protection signal OTP and an overcurrent protection signal OCP provided by the chip state monitoring circuit; the differential data DxP and DxN enter a modulation transmitting circuit to obtain differential transmitting data TxP and TxN; the differential sending data TxP and TxN are respectively connected to the left end of a positive end sending capacitor Ctp and the left end of a negative end sending capacitor Ctn, the right end of the positive end sending capacitor Ctp and the right end of the negative end sending capacitor Ctn are respectively connected to the left end of a positive end receiving capacitor Crp and the left end of a negative end receiving capacitor Crn, the right end of the positive end receiving capacitor Crp and the right end of the negative end receiving capacitor Crn respectively generate differential receiving data RxP and RxN, and the differential receiving data enter a high common mode transient suppression differential signal receiving circuit to obtain receiving output data Dout through processing; receiving output data Dout and finally entering an output driving circuit to generate an output driving signal DG with large driving current;

The transmitting end low voltage generating circuit adopts a transmitting end input power voltage VCCbus to generate a transmitting end power voltage VCC and reference voltage and bias voltage required by each component circuit in the driving circuit transmitting end circuit; the receiving end low voltage generating circuit adopts a receiving end input power voltage VDDbus to generate a receiving end power voltage VDD and reference voltage and bias voltage required by each component circuit in the receiving end circuit of the driving circuit; the transmitting end low voltage generating circuit and the receiving end low voltage generating circuit are realized by adopting the same low voltage generating circuit; the positive end transmitting capacitor Ctp, the negative end transmitting capacitor Ctn, the positive end receiving capacitor Crp and the negative end receiving capacitor Crn are equal in size and are ultrahigh withstand voltage isolation capacitors.

Specifically, the high common mode transient suppression differential signal receiving circuit includes: the differential input receiving circuit, the X-stage tandem common mode adjustable amplifying circuit, the high-sensitivity common mode adjustable amplifying circuit, the output shaping circuit and the common mode self-adaptive adjusting circuit; the differential input receiving circuit firstly receives a differential receiving data positive end receiving signal RxP and a differential receiving data negative end receiving signal RxN, and a positive end input signal Vip and a negative end input signal Vin are obtained through filtering; the positive end input signal Vip and the negative end input signal Vin enter a first-stage common-mode adjustable amplifying circuit in the X-stage tandem common-mode adjustable amplifying circuit, and finally a positive end output signal VoXp and a negative end output signal VoXn of the X-stage common-mode adjustable amplifying circuit are obtained; the positive end output signal VoXp and the negative end output signal VoXn are respectively connected with the positive input end and the negative input end of the high-sensitivity common-mode adjustable amplifying circuit, and the high-sensitivity common-mode adjustable amplifying circuit outputs a group of differential output signals, including a positive end output signal VoXp and a negative end output signal VoXn; the output shaping circuit processes the positive end output signal VoXp and the negative end output signal VoXn to obtain final data output, namely receiving output data Dout; the common mode self-adaptive adjusting circuit adaptively generates common mode adjusting signals C11, C12, C21, C22, …, CX1 and CX2 for each stage of amplifying circuit according to the change of the power supply and ground voltage signals, and the common mode adjusting signals C11 and C12 generated by the common mode self-adaptive adjusting circuit are respectively connected to the common mode adjusting signal input end of the first stage of common mode adjustable amplifying circuit; the common mode adjustment signals C21 and C22 are respectively connected to the common mode adjustment signal input end of the second-stage common mode adjustable amplifying circuit; by analogy, the common mode adjustment signals CX1 and CX2 are respectively connected to the common mode adjustment signal input end of the X-th stage common mode adjustable amplifying circuit; the common mode self-adaptive adjusting circuit also generates common mode adjusting signals CN1 and CN2 which are respectively connected to the common mode adjusting signal input end of the high-sensitivity common mode adjustable amplifying circuit; wherein X is a positive integer greater than 1, and N is a positive integer greater than X.

Specifically, the differential input receiving circuit includes: the device comprises a positive end isolation capacitor C51, a positive end grounding resistor R51, a positive end coupling capacitor C52, a positive end common mode resistor R53, a negative end isolation capacitor C53, a negative end grounding resistor R52, a negative end coupling capacitor C54, a negative end common mode resistor R54 and a receiving common mode generating circuit; the left end of the positive end isolation capacitor C51 and the left end of the negative end isolation capacitor C53 are respectively connected to a positive end receiving signal RXP and a negative end receiving signal RXN; the right end of the positive end isolation capacitor C51 is connected to the lower end of the positive end grounding resistor R51 and the left end of the positive end coupling capacitor C52; the right end of the negative end isolation capacitor C53 is connected to the lower end of the negative end grounding resistor R52 and the left end of the negative end coupling capacitor C54; the right end of the positive end coupling capacitor C52 is connected to the upper end of the positive end common mode resistor R53 and is used as the output end of the positive end input signal Vip; the right end of the negative end coupling capacitor C54 is connected to the lower end of the negative end common mode resistor R54 and is used as the output end of a negative end input signal Vin; the lower end of the positive end common mode resistor R53 is connected with the upper end of the negative end common mode resistor R54 and is simultaneously connected to the common mode output end Vicm of the receiving common mode generating circuit; the receiving common mode generating circuit dynamically tracks and adjusts the size of a common mode output end Vicm according to the change of an input common mode Vcm, and reduces the influence of the input common mode.

Specifically, the reception common mode generation circuit includes: NMOS tube M60, NMOS tube M61, PMOS tube M62, NMOS tube M63, PMOS tube M64, PMOS tube M65, NMOS tube M66, NMOS tube M67, PMOS tube M68, NMOS tube M69, PMOS tube M610, NMOS tube M611, PMOS tube M612, NMOS tube M613, NMOS tube M614, PMOS tube M615 and resistor R61, a first Schmitt trigger;

The grid electrode of the NMOS tube M60 is connected to an input common mode voltage Vcm; the drain electrode of the NMOS tube M60 is connected to the drain electrode and the grid electrode of the PMOS tube M62 and the grid electrode of the NMOS tube M63; the grid electrode of the NMOS tube M61 is connected to an input common mode control signal Vctrl; the drain electrode of the NMOS tube M61 is connected with the drain electrode of the NMOS tube M63 and is connected to the input end of the first Schmitt trigger; the output end of the first Schmitt trigger is simultaneously connected to the grid electrode of the PMOS tube M610, the grid electrode of the NMOS tube M611, the grid electrode of the PMOS tube M612 and the grid electrode of the NMOS tube M613; the drain electrode of the PMOS tube M610 is connected with the drain electrode of the NMOS tube M611 and is also connected to the grid electrode of the NMOS tube M614; the drain electrode of the PMOS tube M612 is connected with the drain electrode of the NMOS tube M613 and is also connected to the grid electrode of the PMOS tube M615; the source electrode of the NMOS tube M614 is connected with the source electrode of the PMOS tube M615 and is also used as an output port of the common mode output end Vicm; the drain of the NMOS tube M614 is connected to the high input common mode level Vcmh, and the drain of the PMOS tube M615 is connected to the low input common mode level Vcml; the source electrode of the NMOS tube M613 is connected to the upper end of the resistor R61; the source electrode of the NMOS tube M60, the source electrode of the NMOS tube M61, the source electrode of the NMOS tube M611 and the lower end of the resistor R61 are simultaneously connected to the ground voltage Vnd 2 of the receiving end; the source of the PMOS transistor M62, the source of the NMOS transistor M63, and the source of the PMOS transistor M610 are simultaneously connected to the receiving end power supply voltage VDD.

Specifically, the high-sensitivity common-mode adjustable amplifying circuit is a front-back two-stage fully-differential amplifying circuit and comprises a front-stage common-mode adjustable amplifying circuit and a rear-stage differential amplifying circuit which are connected with each other; the positive input end of the front-stage common-mode adjustable amplifying circuit is the positive input end of the high-sensitivity common-mode adjustable amplifying circuit, and the negative input end of the front-stage common-mode adjustable amplifying circuit is the negative input end of the high-sensitivity common-mode adjustable amplifying circuit; the positive output end VoNp of the differential amplification circuit is the positive output end of the high-sensitivity common-mode adjustable amplification circuit, and the negative output end VoNn of the differential amplification circuit is the negative output end of the high-sensitivity common-mode adjustable amplification circuit;

The left side of the front-stage common mode adjustable amplifying circuit comprises a PMOS tube M81 and an NMOS tube M83 which are connected in series through drain electrodes; the source electrode of the PMOS tube M81 is connected with the power supply VDD, a capacitor C81 is connected between the grid electrode and the source electrode of the PMOS tube M81, the grid electrode of the PMOS tube M81 is also connected to the upper end of the bias resistor R81, and the drain electrode of the PMOS tube M81 is also connected to the lower end of the bias resistor R82; the lower end of the bias resistor R81 is connected with the upper end of the bias resistor R82 and is also used as a first signal input end of the differential amplifying circuit; the drain electrode of the NMOS tube M83 is connected with the drain electrode of the PMOS tube M81 and is also connected with the third signal input end of the differential amplification circuit; the grid electrode of the NMOS tube M83 is connected with the positive input end of the front-stage common mode adjustable amplifying circuit and receives a positive end output signal VoXp; the right side of the front-stage common mode adjustable amplifying circuit comprises a PMOS tube M82 and an NMOS tube M84 which are connected in series through drain electrodes; the source electrode of the PMOS tube M82 is connected with a power supply VDD, a capacitor C82 is connected between the grid electrode and the source electrode of the PMOS tube M82, the grid electrode of the PMOS tube M82 is also connected to the upper end of a bias resistor R83, and the drain electrode of the PMOS tube M82 is also connected to the lower end of the bias resistor R84; the lower end of the bias resistor R83 is connected with the upper end of the bias resistor R84 and is also used as a second signal input end of the differential amplifying circuit; the drain electrode of the NMOS tube M84 is connected with the drain electrode of the PMOS tube M82 and is also connected to the fourth signal input end of the differential amplification circuit; a grid electrode of the NMOS tube M84 is connected with a negative input end of the front-stage common mode adjustable amplifying circuit and receives a negative end output signal VoXn; the sources of the PMOS tube M81 and the PMOS tube M82 on the left side and the right side of the front-stage common mode adjustable amplifying circuit are connected in parallel, and the sources of the NMOS tube M83 and the NMOS tube M84 are connected in parallel; the sources of the NMOS tube M83 and the NMOS tube M84 are connected with the drains of the NMOS tube M85, the NMOS tube M86 and the NMOS tube M87 which are grounded; the grid electrode of the grounded NMOS tube M85 is connected with bias voltage Vb1 to provide bias current required by normal operation of the amplifier; the gates of the NMOS tube M86 and the NMOS tube M87 are respectively connected to common mode adjustment signals CN1 and CN2;

The differential amplification circuit internally includes: PMOS tube M88, PMOS tube M89, PMOS tube M812, PMOS tube M813, NMOS tube M810, NMOS tube M811, NMOS tube M814, NMOS tube M815 and resistor 85; the grid electrode of the PMOS tube M88 is a first signal input end of the differential amplification circuit, the grid electrode of the PMOS tube M89 is a second signal input end of the differential amplification circuit, the PMOS tube M812 is a third signal input end of the differential amplification circuit, and the PMOS tube M813 is a fourth signal input end of the differential amplification circuit; the drain electrode of the PMOS tube M88 is connected with the drain electrode of the PMOS tube M89 and is connected to the drain electrode of the NMOS tube M810, and is used as the positive output end VoNp of the differential amplifying circuit; the drain electrode of the PMOS tube M812 is connected with the drain electrode of the PMOS tube M813 and is connected to the upper end of the resistor R85; the lower end of the resistor R85 is connected with the drain electrode of the NMOS tube M814 and is used as the negative output end VoNn of the differential amplifying circuit; the NMOS tube M810 and the NMOS tube M811 form a cascode current source structure, the NMOS tube M814 and the NMOS tube M815 form a cascode current source structure, the gates of the NMOS tube M810 and the NMOS tube M814 are connected with the same bias voltage Vb81, and the gates of the NMOS tube M811 and the NMOS tube M815 are connected with the same bias voltage Vb82.

Specifically, the output shaping circuit comprises a three-stage comparator, a buffer with an RC filtering function, a second Schmitt trigger and an output inverter which are sequentially connected, wherein the output end of the output inverter is the final output data, namely the received output data Dout; the connection relation of the internal circuit of the buffer with the RC filter function is as follows: the grid electrode of the PMOS tube M41 and the grid electrode of the NMOS tube M42 are simultaneously connected to the comparison output voltage of the three-stage comparator, the drain electrode of the PMOS tube M41 and the drain electrode of the NMOS tube M42 are simultaneously connected to the grid electrode of the PMOS tube M43 and the grid electrode of the NMOS tube M44, the drain electrode of the PMOS tube M43 is connected to the upper end of the resistor R41, the lower end of the resistor R41 is connected to the upper end of the resistor R42, the upper end of the capacitor C41 and the input end of the second Schmitt trigger, the lower end of the resistor R42 is connected to the drain electrode of the NMOS tube M44, the source electrode of the PMOS tube M41 and the source electrode of the PMOS tube M43 are simultaneously connected to the power supply voltage VCC, and the source electrode of the NMOS tube M44 and the lower end of the capacitor C41 are simultaneously connected to the ground voltage Vgnd2 at the receiving end.

Specifically, the common mode adaptive adjustment circuit includes: the device comprises a common mode detection circuit, a common mode detection signal transmission circuit, an adjustment common mode signal generation circuit and a common mode adjustment signal selection circuit; the common mode detection circuit is used for detecting power supply and substrate noise, changing the magnitude of a common mode detection signal Vcm_det when the noise is larger than a certain threshold value, connecting the common mode detection signal Vcm_det to the common mode detection signal transmission circuit, generating common mode selection switch control signals N11, N12, N21, N22, …, NX1, NX2 and NN1, NN2 through the common mode detection signal transmission circuit, and outputting the common mode selection switch control signals to the common mode adjustment signal selection circuit; the common mode adjustment signal selection circuit generates and adjusts the sizes of the common mode adjustment signals C11, C12, C21, C22, …, CX1, CX2 and CN1, CN2 according to the common mode selection switch control signal and outputs the common mode adjustment signals; the common mode adjustment signal generating circuit is used for generating various common mode bias signals required by the common mode adjustment signal selecting circuit and outputting the common mode bias signals to the common mode adjustment signal selecting circuit.

Specifically, the common mode detection circuit includes: PMOS tube M111, PMOS tube M112 and NMOS tube M113; the grid electrode and the drain electrode of the PMOS tube M111 are connected and connected to the drain electrode of the PMOS tube M112 and the grid electrode of the NMOS tube M113; the grid electrode of the PMOS tube M112 is connected with the drain electrode of the NMOS tube M113 and is used as an output node of the common mode detection signal Vcm_det; the source of the PMOS transistor M111 and the source of the PMOS transistor M112 are connected to the power supply voltage VDD, and the source of the NMOS transistor M113 is connected to the receiving end ground voltage Vgnd2.

Specifically, the transmitting-end low-voltage generating circuit includes: the circuit comprises a starting circuit, an analog circuit module low-voltage power supply circuit, a digital circuit module low-voltage power supply circuit, a self-bias band-gap reference voltage generating circuit, a bias signal generating circuit, a reference voltage generating circuit and n identical reference voltage buffer output circuits; n is a natural number greater than or equal to 2;

The starting circuit, the analog circuit module low-voltage power supply circuit and the digital circuit module low-voltage power supply circuit adopt a transmitting end input power supply voltage VCCbus, the analog circuit module low-voltage power supply circuit generates a low-voltage analog power supply AVCC according to the transmitting end input power supply voltage VCCbus, and the digital circuit module low-voltage power supply circuit generates a low-voltage digital power supply DVCC according to the transmitting end input power supply voltage VCCbus; the self-bias band gap reference voltage generating circuit, the bias signal generating circuit, the reference voltage generating circuit and the n same reference voltage buffer output circuits adopt low-voltage analog power supply AVCC; the bias signal generating circuit generates all bias signals required by the reference voltage generating circuit and n identical reference voltage buffer output circuits; the low-voltage analog power supply AVCC and the low-voltage digital power supply DVCC are equal in voltage and equal to the transmitting end power supply voltage VCC;

The self-bias band-gap reference voltage generating circuit outputs a band-gap reference voltage Vref and is connected to the input end of the reference voltage generating circuit, and the reference voltage generating circuit generates n reference voltages according to the band-gap reference voltage Vref, specifically a first reference voltage V _R1, a second reference voltage V _R2, … … and an nth reference voltage V _Rn which are different in size; the n reference voltages are respectively input to n reference voltage buffer output circuits, and n output reference voltages with larger driving capability are correspondingly obtained, namely, a first reference voltage V _R1 enters the first reference voltage buffer output circuit to obtain a first output reference voltage V _RO1, a second reference voltage V _R2 enters the second reference voltage buffer output circuit to obtain second output reference voltages V _RO2 and … …, and an n reference voltage V _Rn enters the n reference voltage buffer output circuit to obtain an n output reference voltage V _ROn.

The invention has the advantages that: according to the ultra-high voltage insulation isolation SiC MOSFET gate driving circuit, on one hand, an ultra-high voltage insulation isolation technology is adopted, so that an ultra-high voltage insulation capacitor can be realized; on the other hand, the magnitude of the ground potential common mode transient noise can be automatically detected, and errors generated by the common mode transient noise can be dynamically compensated when the noise exceeds a threshold value.

Drawings

FIG. 1 is a schematic diagram of a capacitive isolation driving circuit architecture.

Fig. 2 is a diagram of the gate driving circuit of the ultra-high voltage insulation isolation SiC MOSFET of the present invention.

Fig. 3 is a block diagram of a modulation transmission circuit according to the present invention.

Fig. 4 is a circuit configuration diagram of a refresh module according to the present invention.

Fig. 5 is a circuit configuration diagram of the coding module of the present invention.

Fig. 6 is a block diagram of a high common mode transient suppression differential signal receiving circuit according to the present invention.

Fig. 7 is a schematic diagram of a differential input receiving circuit according to an embodiment of the invention.

Fig. 8 is a schematic diagram of a receiving common mode generating circuit according to an embodiment of the present invention.

Fig. 9 is a schematic diagram of a common mode tunable amplifier circuit according to an embodiment of the present invention.

Fig. 10 is a schematic diagram of an embodiment of a high sensitivity common mode tunable amplifying circuit according to the present invention.

Fig. 11 is an embodiment of an output shaping circuit of the present invention.

Fig. 12 is a schematic diagram of a common mode adaptive adjustment circuit according to an embodiment of the present invention.

Fig. 13 is a schematic diagram of a common mode detection circuit according to an embodiment of the present invention.

Fig. 14 is a waveform diagram of the circuit shown in fig. 13.

Fig. 15 is a cross-section of a semiconductor structure of an embodiment of a high voltage isolation capacitor of the present invention.

Fig. 16 is a diagram of a low voltage generation circuit according to an embodiment of the present invention.

Fig. 17 is an embodiment of the analog circuit module low voltage supply circuit of the present invention.

FIG. 18 is a schematic diagram of an embodiment of the reference voltage generating circuit of FIG. 16.

FIG. 19 is an embodiment of the single reference voltage buffer output circuit of FIG. 16.

Detailed Description

The invention will now be described in further detail with reference to the drawings and examples.

As shown in fig. 2, the ultra-high voltage insulating isolation SiC MOSFET gate driving circuit of the present invention includes an input receiving circuit 1, a digital control circuit 2, a modulation transmitting circuit 5, an isolating circuit 9, a high common mode transient suppression differential signal receiving circuit 6, an output driving circuit 7, a transmitting-side low voltage generating circuit 3, a receiving-side low voltage generating circuit 8, and a chip status monitoring circuit 4. The input receiving circuit 1, the digital control circuit 2, the modulation transmitting circuit 5, the transmitting end low voltage generating circuit 3 and the chip state monitoring circuit 4 form a driving circuit transmitting end circuit, and the high common mode transient suppression differential signal receiving circuit 6, the output driving circuit 7 and the receiving end low voltage generating circuit 8 form a driving circuit receiving end circuit. The ground potential of all circuits inside the transmitting end circuit of the driving circuit is connected to the transmitting end ground voltage Vgnd1, and the ground potential of all circuits inside the receiving end circuit of the driving circuit is connected to the receiving end ground voltage Vgnd2. The isolation circuit 10 comprises a positive end transmitting capacitor Ctp, a negative end transmitting capacitor Ctn, a positive end receiving capacitor Crp and a negative end receiving capacitor Crn.

The input receiving circuit 1 receives external low-level logic input data DI, and the DI is converted into input data Din with a high level VCC through processing; the digital control circuit 2 processes input data Din according to the states of an undervoltage protection signal UVLO, an overtemperature protection signal OTP and an overcurrent protection signal OCP provided by the chip state monitoring circuit 4 to obtain differential data DxP and DxN; the differential data DxP and DxN enter a modulation transmitting circuit 5 to obtain differential transmitting data TxP and TxN; the differential sending data TxP and TxN are respectively connected to the left end of a positive end sending capacitor Ctp and the left end of a negative end sending capacitor Ctn, the right end of the positive end sending capacitor Ctp and the right end of the negative end sending capacitor Ctn are respectively connected to the left end of a positive end receiving capacitor Crp and the left end of a negative end receiving capacitor Crn, and the right end of the positive end receiving capacitor Crp and the right end of the negative end receiving capacitor Crn generate differential receiving data RxP and RxN; the differential receiving data RxP and RxN enter a high common mode transient suppression differential signal receiving circuit 6, and are processed to obtain receiving output data Dout; the received output data Dout finally enters the output driving circuit 7 to generate an output driving signal DG having a large driving current.

The transmitting end low voltage generating circuit 3 adopts a transmitting end input power voltage VCCbus to generate a transmitting end power voltage VCC and various reference voltages and bias voltages required by various constituent circuits in a driving circuit transmitting end circuit. The receiving end low voltage generating circuit 8 adopts a receiving end input power voltage VDDbus to generate a receiving end power voltage VDD and various reference voltages and bias voltages required by various component circuits in the receiving end circuit of the driving circuit. The transmitting-side low voltage generating circuit 3 and the receiving-side low voltage generating circuit 8 are realized by adopting the same low voltage generating circuit. The positive end transmitting capacitor Ctp, the negative end transmitting capacitor Ctn, the positive end receiving capacitor Crp and the negative end receiving capacitor Crn are equal in size and are ultrahigh withstand voltage isolation capacitors.

In the circuit shown in fig. 2, the chip state monitoring circuit 4 can be realized by adopting a conventional temperature protection, under-voltage protection and over-current protection circuit, and the reference voltages required by various protection circuits are generated by the transmitting end low voltage generation circuit 3; the chip state monitoring circuit 4 is used for providing an undervoltage protection signal UVLO, an overtemperature protection signal OTP and an overcurrent protection signal OCP, and judging whether the chip state is correct or not by the digital control circuit 2. When the circuit generates overcurrent (OCP is effective), overtemperature (OTP is effective) or undervoltage of power supply voltage (UVLO is effective), the digital control circuit 2 can block two paths of output DxP and DxN; when the overcurrent and overtemperature alarms are released and the power supply returns to the normal working voltage, the digital control circuit 2 indicates the circuit to work normally. The output driving circuit 7 in the circuit shown in fig. 2 has the function of converting the received output data Dout without driving capability into a large current driving signal DG, which is realized in a number of ways, and the simplest implementation is a well-known inverter chain driving circuit.

In the circuit shown in fig. 2, the input receiving circuit 1 is generally constituted by an input ESD protection circuit and a level discrimination circuit connected in this order. The input receiving circuit 1 not only needs to complete signal transmission, but also needs to complete ESD protection of the internal circuit of the chip, so as to prevent the circuit from being damaged due to impact of ESD on the internal circuit. The level discrimination circuit is used to identify whether the external input level is a logic "0" or "1". Because of the large interference of the external signal, the level discrimination circuit must have sufficient noise margin to resist interference, and a specific circuit implementation typically includes 2 forms, one being a Schmitt trigger and one being a hysteresis comparator. The implementation circuits of the Schmitt trigger and the hysteresis comparator have great difference according to different speeds of the driving chip driving object and the input logic signal. The logic signal output by the level discrimination circuit is Din signal.

The digital control circuit 2 is used for integrating the chip state monitoring signals, judging whether the circuit is normal or not, and switching off the data output when the chip is abnormal. The digital control circuit 2 is composed of a combination logic gate, and when the circuit generates overcurrent (OCP is effective), overtemperature (OTP is effective) or power supply voltage undervoltage (UVLO is effective), the error logic circuit outputs a low-level signal to indicate that the circuit is abnormal and block two paths of outputs DxP and DxN; when the overcurrent and over-temperature alarm is released and the power supply returns to normal working voltage, the error logic circuit immediately outputs a high-level signal to indicate that the circuit works normally.

Fig. 3 is an implementation structure of a one-way modulation transmitting circuit, and a specifically adopted modulation scheme is pulse counting modulation, which uses a method of describing rising edges of an input signal by double pulses and describing falling edges of the input signal by single pulses. The input of the whole system is a signal to be isolated, and the output is an isolated and shaped signal. The modulation transmitting circuit 5 mainly comprises a filter module 503 for processing rising and falling edges of an input signal, a refreshing module 501 and an encoding module 502. Specifically, the filter module 503 is mainly configured to process an interference signal such as a spur on the input signal, so as not to affect the encoding module 502 to generate pulses; the refresh module 501 is configured to supply the refresh signal to the encoding module 502 at a timing according to the timing of the internal timing circuit, so as to avoid the influence of the external interference signal on the pulse in the case of a larger signal period. The encoding module 502 is configured to generate a dual-pulse signal and a single-pulse signal corresponding to the rising edge and the falling edge. In fig. 3, dxP is input data, R1 and R2 are high-frequency refresh signals generated by the refresh module 501, and the output is modulated pulse signal TxP. The modulation transmission circuit 5 of the present invention employs 2 sets of modulation transmission circuits shown in fig. 3.

The filter module 503 in the circuit shown in fig. 3 is used for eliminating the glitch and shaping the signal, and can be realized by adopting a combination of a schmitt trigger and an SR latch, wherein the input signal is connected with the schmitt trigger, and the original input signal with the external interference signal removed is recovered by resetting and shaping the SR latch. Fig. 4 shows an implementation of the refresh module 501 of the present invention. The input signal Fpre enters a simple delay circuit consisting of an inverter and a capacitor, the Fpre signal is subjected to exclusive or with the original signal after delay to obtain a signal PF, and the PF is a pulse corresponding to the jump edge of the Fpre signal. O and O_L are signals with the high and low levels completely opposite. WatchDog is a timing circuit that can be reset via input Fpre and clr_w. After the chip is powered up WatchDog internal current charges the capacitor and eventually brings the output W_D high, forming a state lock, which will remain unchanged unless Fpre or CLR_W is reset. The signals W_D to CLR_W form an oscillation signal OSC through the timing circuit WatchDog, and the oscillation period is WatchDog times plus O and O_L delay times, which are negligible with respect to WatchDog times, so the oscillation period is WatchDog times.

Fig. 5 is a circuit diagram of an encoding module 502 according to the present invention. The modulation scheme adopted by the circuit is pulse counting modulation, and a method for describing the rising edge of an input signal by double pulses and describing the falling edge of the input signal by single pulses is used for separating the rising edge and the falling edge of the input signal to generate corresponding pulse driving signals. The input DxPin of the encoding module 502 is filtered input data, and output is a modulated pulse signal TxP. The refresh signals R1 and R2 respectively correspond to a refresh command signal of a falling edge single pulse and a rising edge double pulse, a circuit normally works when the signals are high, and a refresh operation is executed to refresh the circuit when the signals are low. In addition to logic gates, the circuit also has a delay module TD, which can be composed of an inverter, a capacitor and a Schmitt trigger.

As shown in fig. 6, the structure of the high common mode transient suppression differential signal receiving circuit 6 of the present invention includes: the differential input receiving circuit 1, the common mode adjustable amplifying circuits 602 (CM 1 to CMX) cascaded in tandem of the X stage, the high sensitivity common mode adjustable amplifying circuit 603 (CMN), the output shaping circuit 604, and the common mode adaptive adjusting circuit 605. The differential input receiving circuit 1 firstly receives differential signals (a positive end receiving signal RxP and a negative end receiving signal RxN) coupled by the transmitting end circuit shown in fig. 2 through the isolating circuit 10, and obtains a positive end input signal Vip and a negative end input signal Vin through filtering processing; the Vip and Vin enter a first pole common mode adjustable amplifying circuit CM1 of the X-stage tandem common mode adjustable amplifying circuit 602, and finally a positive end output signal VoXp and a negative end output signal VoXn of the X-stage common mode adjustable amplifying circuit are obtained; voXp and VoXn are respectively connected to the positive input terminal and the negative input terminal of the high-sensitivity common-mode adjustable amplifying circuit 603 (CMN), so as to obtain differential output signals (a positive output signal VoNp and a negative output signal VoNn) of the high-sensitivity common-mode adjustable amplifying circuit 603; the output shaping circuit 604 processes the resulting data output Dout according to the sizes VoNp and VoNn. The common mode adaptive adjustment circuit 605 adaptively generates common mode adjustment signals C11, C12, C21, C22, …, CX1, CX2, CN1, CN2 for each stage of amplifying circuit according to the changes of the power supply and ground voltage signals, and the common mode adjustment signals C11 and C12 generated by the common mode adaptive adjustment circuit 605 are respectively connected to the common mode adjustment signal input terminal of the first stage common mode adjustable amplifying circuit CM 1; the common mode adjustment signal C21 and the common mode adjustment signal C22 are respectively connected to the common mode adjustment signal input end of the second-stage common mode adjustable amplifying circuit CM 2; … … by analogy, the common mode adjustment signal CX1 and the common mode adjustment signal CX2 are respectively connected to the common mode adjustment signal input of the X-th stage common mode adjustable amplifying circuit CMX; the common mode adjustment signal CN1 and the common mode adjustment signal CN2 are connected to the common mode adjustment signal input terminal of the high-sensitivity common mode tunable amplifier circuit 603 (CMN), respectively. Wherein X is a positive integer greater than 1, and N is a positive integer greater than X.

In fig. 6, the common-mode adaptive adjustment circuit 605 automatically detects the magnitude of transient common-mode noise caused by the fluctuation of the power supply voltage VDD and the ground voltage Vgnd2 of the receiving circuit, and adjusts the values of the common-mode adjustment signals C11, C12, C21, C22, …, CX1, CX2, CN1, CN2 and correspondingly outputs the values to the common-mode adjustable amplification circuits CM1 to CMX and the high-sensitivity common-mode adjustable amplification circuit 603 (CMN) of the tandem cascade of the X stages when the transient common-mode noise exceeds a certain threshold value, so as to adjust the common-mode levels of the common-mode adjustable amplification circuits CM1 to CMX and the high-sensitivity common-mode adjustable amplification circuit 3 of the tandem cascade of the X stages to compensate the influence of the transient common-mode noise. In addition to the common mode adaptive adjustment, the present invention also employs a highly reliable output shaping circuit 604, and employs RC low pass filtering and schmitt trigger combination filtering to filter out the effects of high frequency noise, and finally obtains a data output Dout that is not affected by transient common mode noise.

Fig. 7 shows an implementation of a differential input receiving circuit 601 according to the present invention, which is composed of a positive side isolation capacitor C51, a positive side ground resistor R51, a positive side coupling capacitor C52, a positive side common mode resistor R53, a negative side isolation capacitor C53, a negative side ground resistor R52, a negative side coupling capacitor C54, a negative side common mode resistor R54, and a receiving common mode generating circuit 6011. The left end of the positive end isolation capacitor C51 and the left end of the negative end isolation capacitor C53 are respectively connected to a positive end receiving signal RxP and a negative end receiving signal RxN; the right end of the positive end isolation capacitor C51 is connected to the lower end of the positive end grounding resistor R51 and the left end of the positive end coupling capacitor C52; the right end of the negative end isolation capacitor C53 is connected to the lower end of the negative end grounding resistor R52 and the left end of the negative end coupling capacitor C54; the right end of the positive end coupling capacitor C52 is connected to the upper end of the positive end common mode resistor R53 and is used as the output end of the positive end input signal Vip; the right end of the negative end coupling capacitor C54 is connected to the lower end of the negative end common mode resistor R54 and is used as the output end of a negative end input signal Vin; the lower end of the positive-side common-mode resistor R53 and the upper end of the negative-side common-mode resistor R54 are connected, and are simultaneously connected to the common-mode output terminal Vicm of the reception common-mode generating circuit 6011.

In the circuit shown in fig. 7, the positive-side isolation capacitor C51 and the negative-side isolation capacitor C53 are both high-voltage capacitors, and the size of the capacitors is typically several tens of fp; the positive side coupling capacitor C52 and the negative side coupling capacitor C54 are both low-voltage capacitors, and the capacitance values thereof are relatively small. The positive end receiving signal RxP and the negative end receiving signal RxN are input to output, and the positive end input signal Vip and the negative end input signal Vin are obtained through 2-stage direct-isolation coupling filtering. The common mode level of the positive input signal Vip and the negative input signal Vin is provided by the receive common mode generation circuit 6011.

Fig. 8 is a schematic diagram of an implementation of the receive common mode generation circuit 6011 of the present invention. The circuit is composed of an NMOS tube M60, an NMOS tube M61, a PMOS tube M62, an NMOS tube M63, a PMOS tube M64, a PMOS tube M65, an NMOS tube M66, an NMOS tube M67, a PMOS tube M68, an NMOS tube M69, a PMOS tube M610, an NMOS tube M611, a PMOS tube M612, an NMOS tube M613, an NMOS tube M614, a PMOS tube M615 and a resistor R61; the PMOS transistor M64, the PMOS transistor M65, the NMOS transistor M66, the NMOS transistor M67, the PMOS transistor M68, and the NMOS transistor M69 form the schmitt trigger 600.

The grid electrode of the NMOS tube M60 is connected to an input common mode voltage Vcm; the drain electrode of the NMOS tube M60 is connected to the drain electrode and the grid electrode of the PMOS tube M62 and the grid electrode of the NMOS tube M63; the grid electrode of the NMOS tube M61 is connected to an input common mode control signal Vctrl; the drain electrode of the NMOS tube M61 is connected with the drain electrode of the NMOS tube M63 and is connected to the input end of the Schmitt trigger 600; the output end of the schmitt trigger 600 is simultaneously connected to the gates of the PMOS transistor M610, the NMOS transistor M611, the PMOS transistor M612 and the NMOS transistor M613; the drain electrode of the PMOS tube M610 is connected with the drain electrode of the NMOS tube M611 and is also connected to the grid electrode of the NMOS tube M614; the drain electrode of the PMOS tube M612 is connected with the drain electrode of the NMOS tube M613 and is also connected to the grid electrode of the PMOS tube M615; the source electrode of the NMOS tube M614 is connected with the source electrode of the PMOS tube M615 and is also used as an output port of the common mode output end Vicm; the drain of the NMOS tube M614 is connected to the high input common mode level Vcmh, and the drain of the PMOS tube M615 is connected to the low input common mode level Vcml; the source electrode of the NMOS tube M613 is connected to the upper end of the resistor R61; the source of NMOS tube M60, the source of NMOS tube M61, the source of NMOS tube M611 and the lower end of resistor R61 are connected to the ground voltage Vgnd2; the source of the PMOS transistor M62, the source of the NMOS transistor M63, the source of the PMOS transistor M64, and the source of the PMOS transistor M610 are simultaneously connected to the receiving end power supply voltage VDD. The ground terminals of this circuit are each connected to the receiving circuit ground voltage Vgnd2.

The circuit shown in fig. 8 has the function of dynamically tracking and adjusting the magnitude of the common mode output end Vicm according to the change of the input common mode Vcm, so as to reduce the influence of the input common mode. Assuming that the input common mode Vcm decreases, the input terminals of the schmitt trigger 600 will decrease synchronously, and assuming that the fluctuation exceeds the threshold of the schmitt trigger 600, the output of the schmitt trigger 600 will become high level, the PMOS tube M615 will be turned on, the common mode output terminal Vicm will output the low input common mode level Vcml, so that it matches and inputs the common mode variation; assuming that the input common mode Vcm increases and exceeds the threshold of schmitt trigger 600, NMOS transistor M614 turns on and common mode output Vicm will output a high input common mode level Vcmh. It can be seen that the circuit of fig. 8 can achieve dynamic compensation of input common mode variations for different input common mode fluctuations. In the circuit shown in fig. 8, in order to make the common mode output end Vicm better realize the common mode signal output, an NMOS transistor is used to transmit the high input common mode level Vcmh, and a PMOS transistor is used to transmit the low input common mode level Vcml.

Fig. 9 is a schematic diagram of one implementation of a cascode circuit of the present invention. The circuit is a fully differential single-stage amplifying circuit, and the left side of the circuit comprises a PMOS tube M71 and an NMOS tube M73 which are connected in series through drain electrodes; the source electrode of the PMOS tube M71 is connected with a power supply VDD, a capacitor C71 is connected between the grid electrode and the source electrode of the PMOS tube M71, and a bias resistor R71 is connected between the grid electrode and the drain electrode of the PMOS tube; the drain electrode of the NMOS tube M73 outputs a negative end output signal Vo1n connected to the negative input end of the next cascade unit (the second cascade unit outputs a negative end output signal Vo2n to the next cascade unit, and so on), and the gate electrode of the NMOS tube M73 is connected to the positive input end Vip of the common mode adjustable amplifying circuit 602; the right side of the circuit includes: PMOS tube M72 and NMOS tube M74 connected in series through drain electrode; the source electrode of the PMOS tube M72 is connected with a power supply VDD, a capacitor C72 is connected between the grid electrode and the source electrode of the PMOS tube M72, and a bias resistor R72 is connected between the grid electrode and the drain electrode of the PMOS tube M72; the drain electrode of the NMOS tube M74 outputs a positive output signal Vo1p to the positive input end of the next cascade unit (the second cascade unit outputs a positive output signal Vo2p to the next cascade unit, and so on), and the gate electrode of the NMOS tube M74 is connected to the negative input end Vin of the common-mode adjustable amplifying circuit 602; the sources of the PMOS tube M71 and the PMOS tube M72 on two sides of the amplifying circuit are connected in parallel, and the sources of the NMOS tube M73 and the NMOS tube M74 are connected in parallel; the sources of the NMOS tube M73 and the NMOS tube M74 are connected with the drains of the NMOS tube M75, the NMOS tube M76 and the NMOS tube M77 which are grounded; the grid electrode of the grounded NMOS tube M75 is connected with bias voltage Vb1 to provide bias current required by normal operation of the amplifier; the gates of the NMOS transistors M76 and M77 are connected to common mode adjustment signals C11 and C12, respectively.

As can be seen from the circuit shown in fig. 9, by changing the magnitudes of the common-mode adjustment signals C11 and C12, the bias currents flowing through the NMOS transistor M73 and the NMOS transistor M74 are changed, and the output voltages of the negative-side output signal Vo1n and the positive-side output signal Vo1p of the cascade unit are correspondingly changed at the same time, so as to realize adjustment of the output common-mode voltage. The receiving end circuit adopts the same cascade connection of the common mode adjustable amplifying circuits in a plurality of stages as shown in fig. 9, and the X-th stage common mode adjustable amplifying circuit CMX outputs a positive end output signal VoXp and a negative end output signal VoXn, so that the dynamic compensation of common mode noise is finally realized.

Fig. 10 shows an implementation of the high sensitivity common mode tunable amplifying circuit 603 of the present invention. The circuit is a front-back two-stage fully-differential amplifying circuit, the front-stage common-mode adjustable amplifying circuit adopts an amplifying circuit structure similar to that of fig. 9, and the rear-stage amplifying circuit is a differential amplifying circuit (DDA). The positive input end of the front-stage common-mode adjustable amplifying circuit is the positive input end of the high-sensitivity common-mode adjustable amplifying circuit 603, and the negative input end of the front-stage common-mode adjustable amplifying circuit is the negative input end of the high-sensitivity common-mode adjustable amplifying circuit 603; the positive output end VoNp of the differential amplification circuit is the positive output end of the high-sensitivity common-mode adjustable amplification circuit 603, and the negative output end VoNn of the differential amplification circuit is the negative output end of the high-sensitivity common-mode adjustable amplification circuit 603.

The left side of the front-stage common mode adjustable amplifying circuit comprises a PMOS tube M81 and an NMOS tube M83 which are connected in series through drain electrodes; the source electrode of the PMOS tube M81 is connected with the power supply VDD, a capacitor C81 is connected between the grid electrode and the source electrode of the PMOS tube M81, the grid electrode of the PMOS tube M81 is also connected to the upper end of the bias resistor R81, and the drain electrode of the PMOS tube M81 is also connected to the lower end of the bias resistor R82; the lower end of the bias resistor R81 is connected with the upper end of the bias resistor R82 and is also used as a first signal input end of the differential amplifying circuit; the drain electrode of the NMOS tube M83 is connected with the drain electrode of the PMOS tube M81 and is also connected with the third signal input end of the differential amplification circuit; the grid electrode of the NMOS tube M83 is connected with the positive input end VoXp of the front-stage common mode adjustable amplifying circuit; the right side of the circuit comprises a PMOS tube M82 and an NMOS tube M84 which are connected in series through drain electrodes; the source electrode of the PMOS tube M82 is connected with a power supply VDD, a capacitor C82 is connected between the grid electrode and the source electrode of the PMOS tube M82, the grid electrode of the PMOS tube M82 is also connected to the upper end of a bias resistor R83, and the drain electrode of the PMOS tube M82 is also connected to the lower end of the bias resistor R84; the lower end of the bias resistor R83 is connected with the upper end of the bias resistor R84 and is also used as a second signal input end of the differential amplifying circuit; the drain electrode of the NMOS tube M84 is connected with the drain electrode of the PMOS tube M82 and is also connected to the fourth signal input end of the differential amplification circuit; the grid electrode of the NMOS tube M84 is connected with the negative input end VoXn of the front-stage common mode adjustable amplifying circuit; the sources of the PMOS tube M81 and the PMOS tube M82 on two sides of the amplifying circuit are connected in parallel, and the sources of the NMOS tube M83 and the NMOS tube M84 are connected in parallel; the sources of the NMOS tube M83 and the NMOS tube M84 are connected with the drains of the NMOS tube M85, the NMOS tube M86 and the NMOS tube M87 which are grounded; the grid electrode of the grounded NMOS tube M85 is connected with bias voltage Vb1 to provide bias current required by normal operation of the amplifier; the gates of the NMOS transistors M86 and M87 are connected to common mode adjustment signals CN1 and CN2, respectively.

Fig. 11 is an implementation manner of the output shaping circuit 604 of the present invention, which includes a PMOS transistor M401, a PMOS transistor M402, a PMOS transistor M403, a PMOS transistor M404, a PMOS transistor M405, a PMOS transistor M406, a PMOS transistor M409, an NMOS transistor M407, an NMOS transistor M408, an NMOS transistor M4010, a resistor R401, a resistor R402, a PMOS transistor M41, a PMOS transistor M43, a PMOS transistor M45, a PMOS transistor M46, a PMOS transistor M49, a PMOS transistor M411, an NMOS transistor M42, an NMOS transistor M44, an NMOS transistor M47, an NMOS transistor M48, an NMOS transistor M410, an NMOS transistor M412, a resistor R41, a resistor R42, and a capacitor C41.

The PMOS tube M401, the PMOS tube M402, the PMOS tube M403, the PMOS tube M404, the PMOS tube M405, the PMOS tube M406, the PMOS tube M409, the NMOS tube M407, the NMOS tube M408, the NMOS tube M4010, the resistor R401 and the resistor R402 form a three-stage comparator; the PMOS tube M41, the PMOS tube M43, the NMOS tube M42, the NMOS tube M44, the resistor R41, the resistor R42 and the capacitor C41 form a buffer with RC filtering function; the PMOS tube M45, the PMOS tube M46, the PMOS tube M49, the NMOS tube M47, the NMOS tube M48 and the NMOS tube M410 form a Schmidt trigger; the PMOS transistor M411 and the NMOS transistor M412 form an output inverter. The input end of the buffer with the RC filtering function is connected to the comparison output voltage Vo1 of the wide voltage range comparator circuit, the output end of the buffer with the RC filtering function is connected to the input end of the Schmitt trigger, the output end of the Schmitt trigger is connected to the input end of the output inverter, and the output end of the output inverter is the final data output Dout of the high common mode transient suppression differential signal receiving circuit 6.

The internal circuit structure of the three-stage comparator is as follows: the PMOS tube M401, the PMOS tube M402, the PMOS tube M403, the resistor R401 and the resistor R402 form an input stage of the three-stage comparator, the PMOS tube M404, the PMOS tube M405, the PMOS tube M406, the NMOS tube M407 and the NMOS tube M408 form an amplifying stage of the three-stage comparator, and the PMOS tube M409 and the NMOS tube M4010 form an output stage of the three-stage comparator; the connection relation of the internal circuit of the buffer with the RC filter function is as follows: the gates of the PMOS tube M41 and the NMOS tube M42 are simultaneously connected to the comparison output voltage of the three-stage comparator, the drains of the PMOS tube M41 and the NMOS tube M42 are simultaneously connected to the gates of the PMOS tube M43 and the NMOS tube M44, the drain of the PMOS tube M43 is connected to the upper end of the resistor R41, the lower end of the resistor R41 is connected to the upper end of the resistor R42, the upper end of the capacitor C41 and the input end of the Schmitt trigger, the lower end of the resistor R42 is connected to the drain of the NMOS tube M44, the source of the PMOS tube M41 and the PMOS tube M43 is connected to the power supply voltage VCC, and the source of the NMOS tube M42 and the source of the NMOS tube M44 and the lower end of the capacitor C41 are simultaneously connected to the ground voltage Vgnd2.

The output shaping circuit 604 of the present invention shown in fig. 11 provides, on the one hand, three-stage comparators to convert the input differential signal into a standard digital logic signal Dout; on the other hand, RC low-pass filtering and Schmitt trigger combined filtering are adopted, and certain hysteresis is kept for effectively filtering out high-frequency interference influence caused by common-mode noise.

Fig. 12 shows a specific implementation of the common mode adaptive adjustment circuit 605 according to the present invention, which includes a common mode detection circuit 100, a common mode detection signal transmission circuit 101, an adjustment common mode signal generation circuit 102, and a common mode adjustment signal selection circuit 103. The common mode detection circuit 100 is configured to detect power supply and substrate noise, and change the magnitude of a common mode detection signal vcm_det when the noise is greater than a certain threshold, where the common mode detection signal vcm_det is connected to the common mode detection signal transmission circuit 101, and the vcm_det generates common mode selection switch control signals N11, N12, N21, N22, …, NX1, NX2 and NN1, NN2 through the common mode detection signal transmission circuit 101, and outputs the common mode selection switch control signals to the common mode adjustment signal selection circuit 103; the common mode adjustment signal selection circuit 103 generates and adjusts the magnitudes of the common mode adjustment signals C11, C12, C21, C22, …, CX1, CX2, and CN1, CN2 according to the common mode selection switch control signal, and outputs them; the common mode adjustment signal generation circuit 102 is configured to generate various common mode bias signals required by the common mode adjustment signal selection circuit 103, and output the generated common mode bias signals to the common mode adjustment signal selection circuit 503.

In the circuit shown in fig. 12, the common mode detection signal transmission circuit 101 is implemented by using a distributed inverter chain, and the common mode detection signal vcm_det propagates through the distributed N groups of inverter chains to obtain N groups of common mode control signals. The regulated common mode signal generating circuit 102 generates a high input common mode level Vcmh and a low input common mode level Vcml from one bias signal path of the supply voltages VDD to SW. For Vcmh and Vcml implementations, a minimum hardware cost implementation is shown in the figure, and the same functions can be implemented by using other circuits such as reference voltage division or LDO, which are not described here. The internal circuit of the common mode adjustment signal selection circuit 103 is a switch selection array, and the switch array determines the outputs of the common mode adjustment signals C11, C12, C21, C22, …, CX1, CX2 and CN1, CN2 according to the values of the common mode selection switch control signals N11, N12, N21, N22, …, NX1, NX2 and NN1, NN 2.

Fig. 13 shows an implementation of the common mode detection circuit 100 according to the present invention. The common mode detection circuit 100 is configured to detect power supply and substrate noise and to change the magnitude of the common mode detection signal vcm_det when the noise is greater than a certain threshold to control the output of the common mode adaptive adjustment circuit 605 shown in fig. 12. The common mode detection circuit is composed of a PMOS tube M111, a PMOS tube M112 and an NMOS tube M113; the grid electrode and the drain electrode of the PMOS tube M111 are connected and connected to the drain electrode of the PMOS tube M112 and the grid electrode of the NMOS tube M113; the grid electrode of the PMOS tube M112 is connected with the drain electrode of the NMOS tube M113 and is used as an output node of the common mode detection signal Vcm_det; the sources of the PMOS tube M111 and the PMOS tube M112 are connected with the power supply voltage VDD, and the source of the NMOS tube M113 is connected with the ground voltage Vgnd2.

Fig. 14 shows an operation waveform of the common mode detection circuit 100. The typical high-voltage half-bridge gate driving circuit is divided into a high-side driving circuit channel and a low-side driving circuit channel, and the high-side driving circuit realizes signal transmission control in a bootstrap boosting mode. Assuming that the circuit is operating in a half-bridge driven high-side drive circuit, VH is the maximum voltage difference between the half-bridge high and low-side circuits, the Vgnd2 signal must be connected to the half-bridge output node SW, thus requiring Vgnd2 to swing between 0 and VH as well as SW. VDD is connected to the half-bridge driving high-side driving circuit power supply voltage VHB, which is bootstrapped and floated by the bootstrap capacitor on the basis of the SW potential, so that the bootstrap voltage vhb=sw+vcc=vh+vcc in normal operation. Because the capacitor bootstrapping charges also needs a certain charging time, in the capacitor charging process, the bootstrap voltage cannot completely synchronize the fluctuation of the SW, which tends to cause a certain delay of VDD relative to the SW, the voltage difference between the power supply and the ground in the delay interval is not strictly equal to VDD, which is equivalent to the common mode noise of the power supply, and the noise amplitude is large enough to influence the circuit function, so that false triggering of the comparator is generated.

As shown in the waveform of fig. 14, when the half-bridge output SW is stable, the VDD and Vgnd2 voltages are in a stable state, M111 is turned on, M113 is turned on, vcm_det will be pulled down to Vgnd2 by M113, and at a low level; when the half-bridge output SW is switched from 0 to VH, the Vgnd2 voltage is synchronously switched to VH, but the bootstrap voltage has a certain delay, a certain delay interval is generated, VDD does not reach vh+vcc in the delay interval, the gate voltage of M113 is insufficient to enable M113 to be turned on, M113 will be turned off, vcm_det will be influenced by Vgnd2 to generate a peak high pulse under the effect of parasitic capacitance until VDD reaches vh+vcc, at this time, M113 is turned on again, and vcm_det will be pulled down to Vgnd2 by M113.

As shown in FIG. 2, the overall isolation of the capacitor isolation SiC MOSFET driving chip of the invention is realized by two groups of isolation capacitors (Ctp and Crp form a group of P-end series isolation capacitors and Ctn and Crn form a group of N-end series isolation capacitors) which are arranged in series, and the middle is connected with the upper polar plates of the two series isolation capacitors through a Bonding wire (Bonding wire), so that the overall voltage resistance of the capacitor isolator chip is the sum of the voltage resistance of the two capacitors in the series capacitors. In general, the withstand voltage value of SiO2 is about 500V/um, in a general CMOS process of 0.18um, if M1 is used as the lower electrode plate of the isolation capacitor and M6 is used as the upper electrode plate of the isolation capacitor, the total thickness of SiO2 between the metal layers is about 6-7 um, that is, the withstand voltage of a single isolation capacitor is about 3000V-3500V, and the withstand voltages of two isolation capacitors are about 6000V-7000V. The withstand voltage can meet the common and conventional application, and cannot meet the withstand voltage requirement of ultrahigh voltage isolation.

As shown in fig. 15, the present invention provides an ultra-high withstand voltage separating capacitor comprising: the deep N well isolation region DNWELL 50, a lower electrode plate (a first layer M1) 51, an upper electrode plate 54, and a SiO ₂ layer 52 and a passivation layer 53 which are arranged between the lower electrode plate 51 and the upper electrode plate 54 from bottom to top, wherein the passivation layer 53 is a superposition of SiO ₂ and Si ₃N₄. The thickness of the SiO ₂ layer is mainly VIA12, M2 (second layer), VIA23, M3 (third layer), VIA34, M4 (fourth layer), VIA45, M5 (fifth layer), VIA56, M6 (sixth layer), the sum thickness is 8-9 um, and the thickness of the passivation layer 53 is 2-3 um. Si ₃N₄ in the passivation layer 53 is disposed superimposed over SiO ₂ because Si ₃N₄ has better compactness and pressure resistance than SiO ₂. The upper plate 54 is made of metal Cu, and the upper plate 54 is formed by processing the rear end of the wafer, and a layer of metal Cu is formed on the passivation layer 53, and the metal Cu also serves as a PAD. A deep N-well isolation region DNWELL 50 is under the lower plate 51, and a substrate of a wafer is under the deep N-well isolation region 50; the deep N-well isolation region 50 should have an area larger than the planar area of the lower plate 51 and entirely cover the lower surface of the lower plate 51.

According to the scheme of the ultra-high voltage-resistant isolation capacitor, the thickness of the passivation layer is controlled to be about 2.5um through process adjustment, the thickness of a single isolation capacitor is about 12um, the voltage-resistant value can reach 6000V, so that the total thickness of two isolation capacitors connected in series is about 24um, the total voltage-resistant value can reach 12000V, and the requirement of enhancing isolation can be met. The capacitance value of the isolation capacitor is reduced after the isolation capacitor is thickened, the area of the pole plate of the isolation capacitor can be properly increased, the capacitance value of the isolation capacitor is basically kept unchanged, and the transmission quality of the whole isolation signal is not affected.

Fig. 16 is a block diagram of a low voltage generation circuit adopted by the transmitting-end low voltage generation circuit 3, wherein the input is a transmitting-end input power supply voltage VCCbus, the output is a low voltage analog power supply AVCC and a low voltage digital power supply DVCC, and the voltages of the two power supplies are equal and equal to the transmitting-end power supply voltage VCC. The receiving-side low-voltage generation circuit 8 may also be implemented using the same low-voltage generation circuit shown in fig. 16.

The low voltage generation circuit internally includes: a start-up circuit 301, an analog circuit module low voltage supply circuit 302, a digital circuit module low voltage supply circuit 303, a self-biasing bandgap reference voltage generation circuit 304, a bias signal generation circuit 305, a reference voltage generation circuit 306, and n identical reference voltage buffer output circuits 307. The starting circuit 301, the analog circuit module low-voltage power supply circuit 302 and the digital circuit module low-voltage power supply circuit 303 adopt the same transmitting terminal input power supply voltage VCCbus; the self-biased bandgap reference voltage generating circuit 304, the bias signal generating circuit 305, the reference voltage generating circuit 306 and the n identical reference voltage buffer output circuits 307 use the same low voltage analog power supply AVCC. The analog circuit module low voltage power supply circuit 302 generates a low voltage analog power supply AVCC according to the transmitting end input power supply voltage VCCbus, and the digital circuit module low voltage power supply circuit 303 generates a low voltage digital power supply DVCC according to the transmitting end input power supply voltage VCCbus. The bias signal generating circuit 305 generates all bias signals required by the reference voltage generating circuit 306 and n identical reference voltage buffer output circuits 307.

The self-bias bandgap reference voltage generating circuit 304 outputs a bandgap reference voltage Vref to the reference voltage generating circuit 306, and the reference voltage generating circuit 306 generates n reference voltages according to the bandgap reference voltage Vref, wherein the n reference voltages are a first reference voltage V _R1, a second reference voltage V _R2, … …, and an nth reference voltage V _Rn, which are not equal in size. The n reference voltages are respectively input to the n reference voltage buffer output circuits 307, and n output reference voltages with larger driving capability are correspondingly obtained, namely, a first reference voltage V _R1 enters the first reference voltage buffer output circuit to obtain a first output reference voltage V _RO1, a second reference voltage V _R2 enters the second reference voltage buffer output circuit to obtain second output reference voltages V _RO2 and … …, and an n reference voltage V _Rn enters the n reference voltage buffer output circuit to obtain an n output reference voltage V _ROn.

After the power supply voltage VCCbus is input to the transmitting end and powered on, the starting circuit 301 is the circuit that is started first in the whole chip, and generally provides a certain initial bias signal to the low-voltage power supply circuit 302 of the analog circuit module and the low-voltage power supply circuit 303 of the digital circuit module, so as to generate a low-voltage analog power supply AVCC and a low-voltage digital power supply DVCC respectively. The low voltage analog power supply AVCC supplies power to the self-bias bandgap reference voltage generating circuit 304, the bias signal generating circuit 305, the reference voltage generating circuit 306, and the n identical reference voltage buffer output circuit 307 circuits, ultimately generating n output reference voltages V _RO1～V_ROn.

Fig. 17 is an implementation of the analog circuit module low voltage supply circuit 302 described above. The analog circuit module low voltage power supply circuit 302 includes: NPN triode Q1, resistance R170, resistance R171, resistance R172, NMOS pipe M171, NMOS pipe M174, NMOS pipe M175, NMOS pipe M178, PMOS pipe M172, PMOS pipe M173, PMOS pipe M176, PMOS pipe M177 and capacitor C11. The NMOS tube M171, the NMOS tube M174, the NMOS tube M175 and the NMOS tube M178 are all high-voltage MOS tubes, and the PMOS tube M172, the PMOS tube M173, the PMOS tube M176 and the PMOS tube M177 are all low-voltage MOS tubes; the high-voltage MOS tube refers to a MOS tube with source-drain voltage withstand being larger than 10V, and the low-voltage MOS tube refers to a MOS tube with source-drain voltage withstand being smaller than 7V.

The lower end of the resistor R170 is connected with the grid electrode and the drain electrode of the NMOS tube M171 and is also connected with the grid electrodes of the NMOS tube M174 and the NMOS tube M175; the source electrode of the NMOS tube M171 is connected to the collector electrode and the base electrode of the NPN triode Q1; the drain electrode and the grid electrode of the PMOS tube M172 are connected and are also connected to the source electrode of the PMOS tube M173 and the grid electrode of the PMOS tube M177; the drain electrode of the PMOS tube M173 is connected with the grid electrode and is also connected with the drain electrode of the NMOS tube M174 and the grid electrode of the PMOS tube M176; the source of the NMOS tube M174 is connected to the upper end of the resistor R171, and the source of the NMOS tube M175 is connected to the upper end of the resistor R172; the drain electrode of the PMOS tube M176 is connected to the drain electrode of the NMOS tube M175, and the source electrode of the PMOS tube M176 is connected to the drain electrode of the PMOS tube M177 and the grid electrode of the NMOS tube M178; the source electrode of the NMOS tube M178 is connected to the upper end of the capacitor C11 and is also used as an output node of the low-voltage analog power supply AVCC; the upper end of the resistor R10, the source electrode of the PMOS tube M172, the source electrode of the PMOS tube M177 and the drain electrode of the NMOS tube M178 are simultaneously connected VCCbus; the emitter of NPN transistor Q1, the lower end of resistor R170, the lower end of resistor R171, and the lower end of capacitor C11 are simultaneously connected to ground voltage.

In the circuit of fig. 17, the leftmost resistor R170, the NMOS transistor M171 and the NPN transistor Q1 form a dc path from the power supply to the ground, and generate a bias voltage at the gate terminal of the transistor M171, to provide bias for the branches of the PMOS transistor M172, the PMOS transistor M173 and the NMOS transistor M174, and to provide gate bias for the NMOS transistor M178 by further mirroring and bias, thereby obtaining the output low-voltage analog power supply AVCC. To provide a sufficiently large drive current, the NMOS transistor M178 is typically a large-sized transistor. C11 is the filter capacitance, and generally the larger the better. The magnitude of the low-voltage analog power supply AVCC is the gate voltage of the NMOS transistor M178 minus one Vth voltage, and the gate voltage of the NMOS transistor M178 can be realized by adjusting the resistors R171 and R172.

FIG. 18 is a schematic diagram illustrating an embodiment of a reference voltage generation circuit 306 according to the present invention. The circuit is a multi-output LDO circuit, adopts band gap reference voltage Vref to be connected to the positive input end of an operational amplifier A1, the output end of the operational amplifier A1 is connected to an adjusting MOS tube MR1, then a resistor string voltage division is connected to generate a feedback signal, and then the feedback signal is connected to the negative input end of the operational amplifier to form a negative feedback loop, and n reference voltages V _R1,V_R2,…,V_Rn are generated from all nodes of the resistor string. The band-gap reference voltage Vref is provided for a band-gap reference generating circuit, and the band-gap reference generating circuit can be realized by adopting a universal band-gap generating circuit.

FIG. 19 is one implementation of a single reference voltage buffer output circuit. The circuit comprises a PMOS tube M191, a PMOS tube M192, a PMOS tube M193, a PMOS tube M196, a PMOS tube M197, a PMOS tube M1910, an NMOS tube M194, an NMOS tube M195, an NMOS tube M198, an NMOS tube M199, an NMOS tube M1911, a resistor R191, a resistor R192, a resistor R193 and a resistor R194.

The gates of the PMOS transistor M191 and the PMOS transistor M1910 are connected to the bias voltage Vbn; the drain electrode of the PMOS tube M191 is connected to the source electrodes of the PMOS tube M192 and the PMOS tube M193 at the same time; the grid electrode of the PMOS tube M193 is connected to the reference voltage V _Rn; the grid electrode of the PMOS tube M192 is connected to an output feedback signal V _F; the drain electrode and the grid electrode of the NMOS tube M194 are simultaneously connected to the grid electrode of the NMOS tube M198 and the drain electrode of the PMOS tube M192; the drain electrode and the grid electrode of the NMOS tube M195 are simultaneously connected to the grid electrode of the NMOS tube M199 and the drain electrode of the PMOS tube M193; the drain electrode of the NMOS tube M198 is connected to the drain electrode and the grid electrode of the PMOS tube M196 and is also connected to the grid electrode of the PMOS tube M197; the drain electrode of the NMOS tube M199 is connected to the drain electrode of the PMOS tube M197 and the grid electrode of the NMOS tube M1911; the drain electrode of the PMOS tube M1910 is connected with the drain electrode of the NMOS tube M1911 and is connected to the upper end of the resistor R191; the lower end of the resistor R191 is connected to the upper end of the resistor R192 and serves as an output node of the positive-end reference level Vro1 p; the lower end of the resistor R192 is connected to the upper end of the resistor R193 and is also used as an output node for outputting a feedback signal V _F; the lower end of the resistor R193 is connected to the upper end of the resistor R194 and also serves as an output node of the negative terminal reference level Vro1 n; sources of the PMOS tube M191, the PMOS tube M196, the PMOS tube M197 and the PMOS tube M1910 are simultaneously connected to AVCC (=VCC); the sources of the NMOS tube M194, the NMOS tube M195, the NMOS tube M198, the NMOS tube M199 and the NMOS tube M1911 and the lower end of the resistor R194 are simultaneously connected to the ground voltage. Any one of the positive reference level Vro1p and the negative reference level Vro1n can be used as an output reference voltage of the reference voltage buffer output circuit.

The circuit shown in fig. 19 is an operational amplifier with a two-stage push-pull output structure formed by a PMOS transistor M191, a PMOS transistor M192, a PMOS transistor M193, a PMOS transistor M196, a PMOS transistor M197, an NMOS transistor M194, an NMOS transistor M195, an NMOS transistor M198 and an NMOS transistor M199, so as to provide a wide swing output to the greatest extent; the PMOS tube M1910 and the NMOS tube M1911 form a wide-swing output stage circuit, and a resistor voltage division network formed by connecting a driving resistor R191, a resistor R192, a resistor R193 and a resistor R194 in series is used for providing a positive end reference level Vro1p, an output feedback signal V _F and a negative end reference level Vro1n; the output feedback signal V _F is in feedback connection with the ready negative feedback of the operational amplifier input end, and clamps the output feedback signal V _F to the input reference voltage V _Rn; according to the resistor voltage division, the magnitude of the negative reference level Vro1n is Vr+R194/(R193+R194), the magnitude of the positive reference level Vro1p is Vr (R192+R193+R194)/(R193+R194), and the magnitudes of the positive reference level Vro1p and the negative reference level Vro1n can be accurately set by setting the resistor proportion.

The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims

1. The ultra-high voltage insulating isolation SiC MOSFET gate driving circuit is characterized by comprising: the high-common-mode transient suppression differential signal receiving circuit (6), the output driving circuit (7), the transmitting-end low-voltage generating circuit (3), the receiving-end low-voltage generating circuit (8) and the chip state monitoring circuit (4), wherein the input receiving circuit (1), the digital control circuit (2), the modulation transmitting circuit (5), the transmitting-end low-voltage generating circuit (3) and the chip state monitoring circuit (4) form a driving circuit transmitting-end circuit, and the high-common-mode transient suppression differential signal receiving circuit (6), the output driving circuit (7) and the receiving-end low-voltage generating circuit (8) form a driving circuit receiving-end circuit; the ground potentials of all circuits in the driving circuit transmitting end circuit are connected to the transmitting end ground voltage Vgnd1, and the ground potentials of all circuits in the driving circuit receiving end circuit are connected to the receiving end ground voltage Vgnd2; the isolation circuit (9) comprises a positive end transmitting capacitor Ctp, a negative end transmitting capacitor Ctn, a positive end receiving capacitor Crp and a negative end receiving capacitor Crn;

The input receiving circuit (1) receives external low-level logic input data DI, converts the DI into input data Din with a high level VCC, and outputs the input data Din to the digital control circuit (2); the digital control circuit (2) processes input data Din into a group of differential data DxP and DxN according to the states of an undervoltage protection signal UVLO, an overtemperature protection signal OTP and an overcurrent protection signal OCP provided by the chip state monitoring circuit (4); the differential data DxP and DxN enter a modulation transmitting circuit (5) to obtain differential transmitting data TxP and TxN; the differential sending data TxP and TxN are respectively connected to the left end of a positive end sending capacitor Ctp and the left end of a negative end sending capacitor Ctn, the right end of the positive end sending capacitor Ctp and the right end of the negative end sending capacitor Ctn are respectively connected to the left end of a positive end receiving capacitor Crp and the left end of a negative end receiving capacitor Crn, the right end of the positive end receiving capacitor Crp and the right end of the negative end receiving capacitor Crn respectively generate differential receiving data RxP and RxN, and the differential receiving data enter a high common mode transient suppression differential signal receiving circuit (6) to obtain receiving output data Dout through processing; receiving output data Dout and finally entering an output driving circuit (7) to generate an output driving signal DG with large driving current;

The transmitting end low voltage generating circuit (3) adopts a transmitting end input power voltage VCCbus to generate a transmitting end power voltage VCC and reference voltage and bias voltage required by each component circuit in the driving circuit transmitting end circuit; the receiving end low voltage generating circuit (8) adopts a receiving end input power voltage VDDbus to generate a receiving end power voltage VDD and reference voltage and bias voltage required by each component circuit in the receiving end circuit of the driving circuit; the transmitting end low voltage generating circuit (3) and the receiving end low voltage generating circuit (8) are realized by adopting the same low voltage generating circuit; the positive end transmitting capacitor Ctp, the negative end transmitting capacitor Ctn, the positive end receiving capacitor Crp and the negative end receiving capacitor Crn are equal in size and are ultrahigh voltage-resistant isolation capacitors;

The transmitting-end low-voltage generating circuit (3) includes: a starting circuit (301), an analog circuit module low-voltage power supply circuit (302), a digital circuit module low-voltage power supply circuit (303), a self-bias band-gap reference voltage generating circuit (304), a bias signal generating circuit (305), a reference voltage generating circuit (306) and n identical reference voltage buffer output circuits (307); n is a natural number greater than or equal to 2;

The starting circuit (301), the analog circuit module low-voltage power supply circuit (302) and the digital circuit module low-voltage power supply circuit (303) adopt a transmitting end input power supply voltage VCCbus, the analog circuit module low-voltage power supply circuit (302) generates a low-voltage analog power supply AVCC according to the transmitting end input power supply voltage VCCbus, and the digital circuit module low-voltage power supply circuit (303) generates a low-voltage digital power supply DVCC according to the transmitting end input power supply voltage VCCbus; the self-bias band-gap reference voltage generating circuit (304), the bias signal generating circuit (305), the reference voltage generating circuit (306) and n identical reference voltage buffer output circuits (307) adopt a low-voltage analog power supply AVCC; the bias signal generating circuit (305) generates all bias signals required by the reference voltage generating circuit (306) and n identical reference voltage buffer output circuits (307); the low-voltage analog power supply AVCC and the low-voltage digital power supply DVCC are equal in voltage and equal to the transmitting end power supply voltage VCC;

The self-bias band-gap reference voltage generating circuit (304) outputs a band-gap reference voltage Vref and is connected to the input end of the reference voltage generating circuit (306), and the reference voltage generating circuit (306) generates n reference voltages according to the band-gap reference voltage Vref, in particular a first reference voltage V _R1, a second reference voltage V _R2, … … and an nth reference voltage V _Rn which are not equal in size; the n reference voltages are respectively input into n reference voltage buffer output circuits (307), n output reference voltages with larger driving capability are correspondingly obtained, namely, a first reference voltage V _R1 enters the first reference voltage buffer output circuit to obtain a first output reference voltage V _RO1, a second reference voltage V _R2 enters the second reference voltage buffer output circuit to obtain second output reference voltages V _RO2 and … …, and an n reference voltage V _Rn enters the n reference voltage buffer output circuit to obtain an n output reference voltage V _ROn.

2. The ultra-high voltage insulating isolation SiC MOSFET gate drive circuit according to claim 1, characterized in that the high common mode transient suppression differential signal receiving circuit (6) comprises: the differential input receiving circuit (601), the X-stage tandem common mode adjustable amplifying circuit (602), the high-sensitivity common mode adjustable amplifying circuit (603), the output shaping circuit (604) and the common mode self-adaptive adjusting circuit (605); the differential input receiving circuit (601) firstly receives a positive end receiving signal RxP and a negative end receiving signal RxN of differential receiving data, and obtains a positive end input signal Vip and a negative end input signal Vin through filtering processing; the positive end input signal Vip and the negative end input signal Vin enter a first-stage common-mode adjustable amplifying circuit in an X-stage tandem common-mode adjustable amplifying circuit (602), and finally a positive end output signal VoXp and a negative end output signal VoXn of an X-stage common-mode adjustable amplifying circuit are obtained; the positive end output signal VoXp and the negative end output signal VoXn are respectively connected with the positive input end and the negative input end of the high-sensitivity common-mode adjustable amplifying circuit (603), and the high-sensitivity common-mode adjustable amplifying circuit (603) outputs a group of differential output signals, including a positive end output signal VoXp and a negative end output signal VoXn; the output shaping circuit (604) processes the positive output signal VoXp and the negative output signal VoXn to obtain a final data output, namely receiving output data Dout; the common mode self-adaptive adjusting circuit (605) adaptively generates common mode adjusting signals C11, C12, C21, C22, …, CX1 and CX2 for each stage of amplifying circuit according to the change of power supply and ground voltage signals, and the common mode adjusting signals C11 and C12 generated by the common mode self-adaptive adjusting circuit (605) are respectively connected to the common mode adjusting signal input end of the first stage of common mode adjustable amplifying circuit; the common mode adjustment signals C21 and C22 are respectively connected to the common mode adjustment signal input end of the second-stage common mode adjustable amplifying circuit; by analogy, the common mode adjustment signals CX1 and CX2 are respectively connected to the common mode adjustment signal input end of the X-th stage common mode adjustable amplifying circuit; the common mode self-adaptive adjusting circuit (605) also generates common mode adjusting signals CN1 and CN2 which are respectively connected to the common mode adjusting signal input end of the high-sensitivity common mode adjustable amplifying circuit (603); wherein X is a positive integer greater than 1, and N is a positive integer greater than X.

3. The ultra-high voltage insulated SiC MOSFET gate drive circuit according to claim 2, characterized in that the differential input receiving circuit (601) includes: a positive end isolation capacitor C51, a positive end grounding resistor R51, a positive end coupling capacitor C52, a positive end common mode resistor R53, a negative end isolation capacitor C53, a negative end grounding resistor R52, a negative end coupling capacitor C54, a negative end common mode resistor R54 and a receiving common mode generating circuit (6011); the left end of the positive end isolation capacitor C51 and the left end of the negative end isolation capacitor C53 are respectively connected to a positive end receiving signal RXP and a negative end receiving signal RXN; the right end of the positive end isolation capacitor C51 is connected to the lower end of the positive end grounding resistor R51 and the left end of the positive end coupling capacitor C52; the right end of the negative end isolation capacitor C53 is connected to the lower end of the negative end grounding resistor R52 and the left end of the negative end coupling capacitor C54; the right end of the positive end coupling capacitor C52 is connected to the upper end of the positive end common mode resistor R53 and is used as the output end of the positive end input signal Vip; the right end of the negative end coupling capacitor C54 is connected to the lower end of the negative end common mode resistor R54 and is used as the output end of a negative end input signal Vin; the lower end of the positive end common mode resistor R53 is connected with the upper end of the negative end common mode resistor R54 and is simultaneously connected to a common mode output end Vicm of the receiving common mode generating circuit (6011); the receiving common mode generating circuit (6011) dynamically tracks and adjusts the size of the common mode output end Vicm according to the change of the input common mode Vcm, and reduces the influence of the input common mode.

4. The ultra-high voltage insulated SiC MOSFET gate drive circuit according to claim 3, characterized in that the reception common mode generating circuit (6011) includes: NMOS tube M60, NMOS tube M61, PMOS tube M62, NMOS tube M63, PMOS tube M64, PMOS tube M65, NMOS tube M66, NMOS tube M67, PMOS tube M68, NMOS tube M69, PMOS tube M610, NMOS tube M611, PMOS tube M612, NMOS tube M613, NMOS tube M614, PMOS tube M615 and resistor R61, a first Schmitt trigger (600);

The grid electrode of the NMOS tube M60 is connected to an input common mode voltage Vcm; the drain electrode of the NMOS tube M60 is connected to the drain electrode and the grid electrode of the PMOS tube M62 and the grid electrode of the NMOS tube M63; the grid electrode of the NMOS tube M61 is connected to an input common mode control signal Vctrl; the drain electrode of the NMOS tube M61 is connected with the drain electrode of the NMOS tube M63 and is connected to the input end of the first Schmitt trigger (600); the output end of the first Schmitt trigger (600) is simultaneously connected to the grid electrode of the PMOS tube M610, the grid electrode of the NMOS tube M611, the grid electrode of the PMOS tube M612 and the grid electrode of the NMOS tube M613; the drain electrode of the PMOS tube M610 is connected with the drain electrode of the NMOS tube M611 and is also connected to the grid electrode of the NMOS tube M614; the drain electrode of the PMOS tube M612 is connected with the drain electrode of the NMOS tube M613 and is also connected to the grid electrode of the PMOS tube M615; the source electrode of the NMOS tube M614 is connected with the source electrode of the PMOS tube M615 and is also used as an output port of the common mode output end Vicm; the drain of the NMOS tube M614 is connected to the high input common mode level Vcmh, and the drain of the PMOS tube M615 is connected to the low input common mode level Vcml; the source electrode of the NMOS tube M613 is connected to the upper end of the resistor R61; the source electrode of the NMOS tube M60, the source electrode of the NMOS tube M61, the source electrode of the NMOS tube M611 and the lower end of the resistor R61 are simultaneously connected to the ground voltage Vnd 2 of the receiving end; the source of the PMOS transistor M62, the source of the NMOS transistor M63, and the source of the PMOS transistor M610 are simultaneously connected to the receiving end power supply voltage VDD.

5. The ultra-high voltage insulating isolation SiC MOSFET gate driving circuit according to claim 2, wherein the high-sensitivity common mode adjustable amplifying circuit (603) is a front-back two-stage fully differential amplifying circuit, and includes a front-stage common mode adjustable amplifying circuit and a rear-stage differential amplifying circuit connected to each other; the positive input end of the front-stage common-mode adjustable amplifying circuit is the positive input end of the high-sensitivity common-mode adjustable amplifying circuit (603), and the negative input end of the front-stage common-mode adjustable amplifying circuit is the negative input end of the high-sensitivity common-mode adjustable amplifying circuit (603); the positive output end VoNp of the differential amplification circuit is the positive output end of the high-sensitivity common-mode adjustable amplification circuit (603), and the negative output end VoNn of the differential amplification circuit is the negative output end of the high-sensitivity common-mode adjustable amplification circuit (603);

6. The ultra-high voltage insulation isolation SiC MOSFET gate driving circuit according to claim 2, wherein the output shaping circuit (604) includes a three-stage comparator, a buffer with an RC filtering function, a second schmitt trigger, and an output inverter connected in sequence, and an output end of the output inverter is final output data, namely, receiving output data Dout; the connection relation of the internal circuit of the buffer with the RC filter function is as follows: the grid electrode of the PMOS tube M41 and the grid electrode of the NMOS tube M42 are simultaneously connected to the comparison output voltage of the three-stage comparator, the drain electrode of the PMOS tube M41 and the drain electrode of the NMOS tube M42 are simultaneously connected to the grid electrode of the PMOS tube M43 and the grid electrode of the NMOS tube M44, the drain electrode of the PMOS tube M43 is connected to the upper end of the resistor R41, the lower end of the resistor R41 is connected to the upper end of the resistor R42, the upper end of the capacitor C41 and the input end of the second Schmitt trigger, the lower end of the resistor R42 is connected to the drain electrode of the NMOS tube M44, the source electrode of the PMOS tube M41 and the source electrode of the PMOS tube M43 are simultaneously connected to the power supply voltage VCC, and the source electrode of the NMOS tube M44 and the lower end of the capacitor C41 are simultaneously connected to the ground voltage Vgnd2 at the receiving end.

7. The ultra-high voltage insulated SiC MOSFET gate drive circuit according to claim 2, characterized in that the common mode adaptive adjustment circuit (605) comprises: a common mode detection circuit (100), a common mode detection signal transmission circuit (101), an adjustment common mode signal generation circuit (102), and a common mode adjustment signal selection circuit (103); the common mode detection circuit (100) is used for detecting power supply and substrate noise, changing the magnitude of a common mode detection signal Vcm_det when the noise is larger than a certain threshold value, connecting the common mode detection signal Vcm_det to the common mode detection signal transmission circuit (101), generating common mode selection switch control signals N11, N12, N21, N22, …, NX1, NX2 and NN1, NN2 through the common mode detection signal transmission circuit (101), and outputting the common mode selection switch control signals to the common mode adjustment signal selection circuit (103); the common mode adjustment signal selection circuit (103) generates and adjusts the magnitude of the common mode adjustment signals C11, C12, C21, C22, …, CX1, CX2 and CN1, CN2 according to the common mode selection switch control signal and outputs the common mode adjustment signals; the common mode adjustment signal generation circuit (102) is used for generating various common mode bias signals required by the common mode adjustment signal selection circuit (103) and outputting the common mode bias signals to the common mode adjustment signal selection circuit (103).

8. The ultra-high voltage insulated SiC MOSFET gate drive circuit according to claim 7, characterized in that the common mode detection circuit (100) includes: PMOS tube M111, PMOS tube M112 and NMOS tube M113; the grid electrode and the drain electrode of the PMOS tube M111 are connected and connected to the drain electrode of the PMOS tube M112 and the grid electrode of the NMOS tube M113; the grid electrode of the PMOS tube M112 is connected with the drain electrode of the NMOS tube M113 and is used as an output node of the common mode detection signal Vcm_det; the source of the PMOS transistor M111 and the source of the PMOS transistor M112 are connected to the power supply voltage VDD, and the source of the NMOS transistor M113 is connected to the receiving end ground voltage Vgnd2.