CN111490667A - High-speed high-efficiency high-voltage half-bridge gate driving circuit - Google Patents
High-speed high-efficiency high-voltage half-bridge gate driving circuit Download PDFInfo
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- CN111490667A CN111490667A CN202010315906.8A CN202010315906A CN111490667A CN 111490667 A CN111490667 A CN 111490667A CN 202010315906 A CN202010315906 A CN 202010315906A CN 111490667 A CN111490667 A CN 111490667A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
- H02M1/385—Means for preventing simultaneous conduction of switches with means for correcting output voltage deviations introduced by the dead time
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Abstract
The invention belongs to the technical field of integrated circuits, and particularly relates to a high-speed high-efficiency high-voltage half-bridge gate driving circuit required by gate driving of a power device in a power electronic system. The high-speed high-efficiency high-voltage half-bridge gate driving circuit provided by the invention reduces the delay of the level shift circuit by a positive feedback driving current enhancement technology, thereby improving the speed of the whole driving circuit; the driving current can be adaptively adjusted according to the load size and the frequency of the input control pulse, so that the power efficiency of the driving circuit is improved to the maximum extent; the method can be widely applied to various high-power-density power electronic systems, in particular to the gate drive application of wide-bandgap power devices with higher frequency requirements.
Description
Technical Field
The invention relates to a high-speed high-efficiency high-voltage half-bridge gate driving circuit for a power electronic system, and belongs to the technical field of integrated circuits.
Background
In the 21 st century, under the traction of emerging industries such as smart grid, mobile communication and new energy automobile, power electronic application systems require further improvement of system efficiency, miniaturization and added functions, and particularly require trade-offs between circuit application size, quality, power and efficiency, such as server power management, battery charger and micro-inverter of solar electric field. The above applications require power electronics systems to be efficient in design>95% of the total power, and also has high power density (>500W/in3I.e. 30.5W/cm3) High specific power (10 kW/lb, 22kW/kg) and high total load point(s) ((>1000W). With the emergence and widespread use of super-junction MOSFETs and Insulated Gate Bipolar Transistors (IGBTs), and particularly with the advent of wide bandgap power semiconductor devices represented by SiC and GaN, a new generation of electric powerThe electronic application system has increasingly higher requirements on the driving technology of the power semiconductor device, and the most central factor of the driving technology is the high-voltage gate driving chip for controlling the functions of the power semiconductor device. The new generation of power electronic complete machine system puts forward higher requirements on the driving speed and the intellectualization of the high-voltage grid driving chip, thereby further improving the reliability of the complete machine and reducing the design complexity of the complete machine system.
In a typical BCD process, a high-voltage level shifting circuit must use L DMOS which is resistant to high voltage to realize signal transmission, while a high-voltage L DMOS has a large parasitic capacitance and can seriously limit the signal processing speed of the high-voltage level shifting circuit, the speed of the 650V high-side driving circuit adopting the technology is usually limited below 200KHz and cannot meet the processing speed requirement that wide-bandgap power devices represented by GaN and SiC exceed MHz.
In addition, after the conventional half-bridge gate driver chip is designed and shaped, the output driving capability of the high/low side output control signal is solidified. In practical applications, to prevent the output current from damaging the gate of the load power switch, a resistor is usually connected in series with the high/low side output terminal to suppress the gate voltage overshoot effect. When the equivalent capacitance of the gate terminal is larger, the series protection resistor needs to be smaller, otherwise, the series protection resistor needs to be larger. The larger series protection resistor brings 2 problems, firstly, the switch on the resistor is damaged and enlarged, and the efficiency of the driving circuit is reduced; secondly, the driving time delay is increased, and finally the switching frequency of the system is reduced. Therefore, in order to improve the efficiency of the whole driving circuit, it is necessary to provide an output driving circuit capable of automatically adjusting the magnitude of the driving current according to the gate capacitance of the power switch tube.
Based on the gate driving application requirements of wide bandgap power devices represented by GaN and SiC, the invention provides a high-speed high-efficiency high-voltage half-bridge gate driving circuit.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a high-speed high-efficiency high-voltage half-bridge gate driving circuit.
The invention provides a high-speed high-efficiency high-voltage half-bridge gate driving circuit, which comprises an input receiving circuit, a dead time generating circuit, a low-voltage generating circuit, a low-side delay circuit, a low-side high-efficiency output driving circuit L, a low-delay high-voltage level shifting circuit and a high-side high-efficiency output driving circuit H;
the low-voltage digital input signals HI and HI firstly enter an input receiving circuit to carry out signal level discrimination and logic level high-voltage conversion to obtain medium-voltage signals H and L, a dead time generating circuit obtains high-side differential input data HIP and HIN according to the medium-voltage signals H and obtains low-side differential input data L IP and L IN according to a medium-voltage signal L, the high-side differential input data HIP and HIN enter a low-delay high-voltage level shifting circuit to obtain high-side driving data with low potential floating, and then enter a high-efficiency output driving circuit to obtain a high-side output signal HO with larger driving capacity through driving amplification, and the low-side differential input data L IP and L IN enter a low-side delay circuit to obtain low-side driving data and output the low-side to a high-efficiency output driving circuit L to obtain a low-side output signal L O with larger driving capacity through driving amplification;
the low-side high-efficiency output driving circuit L and the high-side high-efficiency output driving circuit H are high-efficiency output driving circuits with completely identical circuit structures, the low-delay high-voltage level shifter circuit needs to use two groups of ground potentials of a low-voltage ground VSS and a floating ground SW at the same time, the high-side high-efficiency output driving circuit H only needs to use the floating ground SW, the input receiving circuit, the dead time generating circuit, the low-voltage generating circuit, the low-side delay circuit and the low-side high-efficiency output driving circuit L share the low-voltage ground VSS, the driving capacity of the high-efficiency output driving circuit is controlled by Start-up signals, Clk-ctrl and n reference voltages Vr 1-Vrn of a trigger control clock signal, the input receiving circuit needs to use a low-voltage power supply voltage VC L and a medium-voltage power supply voltage VCC at the same time, the low-voltage generating circuit generates a low-voltage power supply voltage VC L and n reference voltages 1-Vr n according to the medium-voltage power supply voltage VCC, wherein n.
The low voltage generating circuit internally comprises: the circuit comprises a starting circuit, a band gap reference circuit, a buffer, a biasing circuit and an input low voltage generating circuit; after the voltage VCC of the medium-voltage power supply is electrified, the starting circuit is firstly started, and a certain initial bias signal is provided for the band-gap reference voltage generating circuit to generate a fixed reference voltage and a reference current;
the fixed reference voltage is used for generating n reference voltages Vr 1-Vrn required by the internal work of the chip through a reference voltage generating circuit and outputting the n reference voltages through a driving buffer circuit, the reference current usually enters a bias signal generating circuit and generates various bias signals for providing bias for other analog circuits in the chip and also provides bias for the reference voltage generating circuit and an input low voltage generating circuit, and the input low voltage generating circuit finally generates a low-voltage power supply voltage VC L.
The low-delay high-voltage level shift circuit comprises a first high-voltage L DMOS transistor MD1, a second high-voltage L DMOS transistor MD2, a first protection diode D1, a second protection diode D2, a third resistor R3, a fourth resistor R4, a first resistor R1, a second resistor R2, a first coupling MOS transistor M1, a second coupling MOS transistor M2, a first speed enhancement transistor Me1, a second speed enhancement transistor Me2, an error hysteresis filter circuit and a signal overturn detection circuit;
the device comprises a first high-voltage DMOS transistor MD, a second high-voltage DMOS transistor MD, a third resistor R, a gate terminal of the second coupling MOS transistor M, a drain terminal of the second high-voltage DMOS transistor MD, a drain terminal of the first high-voltage DMOS transistor MD, a drain terminal of the second coupling MOS transistor M, an anode of the second protection diode D, a lower terminal of the fourth resistor R and a gate terminal of the first coupling MOS transistor M, a drain terminal of the error hysteresis filter circuit, a data input P terminal SP and a drain terminal of the first speed enhancement transistor Me, a drain terminal of the second coupling MOS transistor M, a drain terminal of the second resistor R, a drain terminal of the error input N terminal SN and a drain terminal of the second speed enhancement transistor Me, lower terminals of the first coupling MOS transistor R and the second coupling MOS transistor M, a drain terminal of the error hysteresis filter circuit, a drain terminal of the second coupling MOS transistor M, an output terminal of the error hysteresis filter circuit is connected with a floating ground SW, an output of a driving signal N, a driving signal of the error filter circuit, a drain terminal of the error signal input N is connected with a drain terminal of the first high-speed enhancement transistor D, a drain terminal of the first speed enhancement transistor D, a drain terminal of the second high-speed enhancement transistor M.
Further, the high-reliability error hysteresis filtering circuit comprises: the device comprises a P-end coupling phase inverter, a P-end deburring circuit, a P-end OR gate, a P-end data selector, an N-end coupling phase inverter, an N-end deburring circuit, an N-end OR gate and an N-end data selector circuit; the P-end deburring circuit and the N-end deburring circuit have the same structure, and the P-end deburring circuit and the N-end deburring circuit internally comprise 3 2-input NAND gates and a 2-input OR gate.
Specifically, the high-efficiency output driving circuit includes: the device comprises an input P-end inverter chain, an N-end inverter chain, N P-end output inverters, N N-end output inverters, N P-end output PMOS (P-channel metal oxide semiconductor) tubes, N N-end output NMOS (N-channel metal oxide semiconductor) tubes, N P-end output inverter control switches, N N-end output inverter control switches, a sampling switch SW, an input data switch Kin, a test data switch Kcal, a high-speed comparator array, an error filtering circuit, a load judging circuit, a driving current selecting circuit, an input pulse frequency judging circuit and a controller circuit;
the P-end inverter chain comprises k cascaded P-end input buffer inverters, and the driving capability of the k inverters is gradually increased from the front stage to the rear stage; the N-end inverter chain comprises k-1 cascaded N-end input buffer inverters and a delay unit, and the driving capability of the k-1 inverters is gradually increased from a front stage to a rear stage; the delay time of the delay unit must be equal to the delay time of the front-end P-end input buffer inverter; the output of the P-end inverter chain is simultaneously connected to the left sides of the N P-end output inverter control switches, and the output of the N-end inverter chain is simultaneously connected to the left sides of the N N-end output inverter control switches; the P-terminal inverter chain is connected with the input end of the N-terminal inverter chain and also connected to the right side of the input data switch Kin and the test data switch Kcal;
the right sides of the N P-end output inverter control switches are respectively connected with the gate ends of the N P-end output PMOS tubes, and the right sides of the N N-end output inverter control switches are respectively connected with the gate ends of the N N-end output NMOS tubes; the source ends of the N P-end output PMOS tubes are simultaneously connected to power supply voltage, the source ends of the N N-end output NMOS tubes are simultaneously connected to the ground, and the drain ends of the N P-end output PMOS tubes are simultaneously connected to the drain ends of the N N-end output NMOS tubes and the output Vout of the driving circuit;
the output Vout of the driving circuit enters a high-speed comparator array after being sampled by a sampling switch SW, is compared with n reference voltages, and then enters an error filtering circuit to output a load detection code Dtest; the input pulse frequency discrimination circuit compares and quantizes the frequency of input data Din to obtain a Din frequency discrimination code Dfin; the load detection code Dtest and the frequency discrimination code Dfin enter a load discrimination circuit at the same time to calculate to obtain a load evaluation code Dev; the driving current selection circuit selects and outputs switch control signals of N P-end output inverter control switches and switch control signals of N N-end output inverter control switches according to the size of Dev;
the load test signal Dcal output by the controller circuit is connected to the left side of a test data switch Kcal, a test clock Clkcal output by the controller circuit is connected to a clock input end of an input pulse frequency discrimination circuit, a load test control signal Ctrl _ test output by the controller circuit is respectively connected to a control signal input end of the high-speed comparator array and a control signal input end of the error filtering circuit, a control signal Ctrl _ ev output by the controller circuit is connected to a control signal input end of the load discrimination circuit, a Ctrl _ out signal output by the controller circuit is connected to a control signal input end of the driving current selection circuit, and a Ctrl _ fin signal output by the controller circuit is connected to a control signal input end of the input pulse frequency discrimination circuit; the controller circuit is controlled by a trigger control clock signal Clk-ctrl and a power-on signal Start-up;
the frequency of the trigger control clock signal Clk-ctrl must be R times the frequency of the load test signal Dcal;
wherein k and R are any positive integer.
Preferably, the working state of the high-efficiency output driving circuit comprises two modes of driving capability adaptive adjustment and normal working; when the power supply voltage is electrified, firstly, a driving capability self-adaptive adjustment mode is started, and then a normal working mode is entered;
the working process in the driving capability adaptive adjustment mode is as follows:
after the power supply voltage is electrified, the controller circuit closes the input data switch Kin, outputs a test clock Clkcal, and opens the deep pulse frequency discrimination circuit, and the input pulse frequency discrimination circuit compares and quantizes the frequency of the input data Din based on the test clock Clkcal to obtain a Din frequency discrimination code Dfin;
when the output setup time is met, the controller circuit turns on a test data switch Kcal and outputs a load test signal Dcal, and in addition, a high-speed comparator array, an error filtering circuit, a load judging circuit and a driving current selection circuit are turned on, and the output Vout of the driving circuit changes according to different loads;
the controller circuit starts a sampling switch SW to sample the Vout voltage, and a load detection code Dtest is obtained after the sampling switch SW is processed by a high-speed comparator array and an error filtering circuit;
the load judging circuit calculates to obtain a load evaluation code Dev according to the load detection code Dtest and the Din frequency judging code Dfin;
the driving current selection circuit sets the switch control signals of the N P-end output inverter control switches and the switch control signals of the N N-end output inverter control switches according to the load evaluation code Dev, and keeps the switch control signals unchanged;
the output setup time consists of M Clk-ctrl clock cycles, the time span of which must be less than 1 cycle time of Dcal; wherein M is a positive integer less than R;
the process of comparing and quantizing the frequency of the input data Din by the input pulse frequency discrimination circuit needs to quantize the frequency of the Din by using J test clock Clkcal periods, and the time length of the J test clock Clkcal periods must be larger than the integer period of the Din; that is, the frequency of the test clock Clkcal is X times the frequency of the input data Din; wherein X is a positive number greater than 1, and J is a positive integer greater than X.
The controller circuit internally includes: a frequency discrimination control generating circuit for generating a Ctrl _ fin signal to control the input pulse frequency discrimination circuit; a switching signal generating circuit for generating switching control signals Kcal, SW and Kin; the load test control generation circuit is used for generating a load test control signal Ctrl _ test to control the high-speed comparator array and the error filtering circuit; the load discrimination control generation circuit is used for generating a Ctrl _ ev signal to control the load discrimination circuit; the drive current control generating circuit is used for generating a Ctrl _ out signal to control the drive current selecting circuit; a test pattern generation circuit for generating a load test pattern Dcal and a test clock Clkcal; the counter circuit is used for providing the other control signals according to the external trigger control clock signal Clk-ctrl and the power-on signal Start-up to generate the required trigger signals.
The frequency of the external trigger control clock Clk-ctrl must be much higher than the frequency of the input data Din; the frequency of the test clock Clkcal cannot be lower than the frequency of the control clock Clk-ctrl, and the higher the Clkcal frequency, the more accurate the discrimination of the Din frequency.
Further, the load discriminating circuit includes: 2 registers used for storing the load detection code Dtest and the frequency discrimination code Dfin respectively, and a normalization quantization calculation circuit for calculating the load detection code Dtest and the frequency discrimination code Dfin;
the data output of the 2 registers is controlled by the same signal; the load evaluation code Dev output by the normalization quantization calculation circuit is calculated by Dtest and Dfin, and the calculation formula is: dev ═ G × Dtest/Dfin; wherein G is a gain coefficient and is a positive number greater than 1.
The invention has the advantages that: the high-speed high-efficiency high-voltage half-bridge gate driving circuit reduces the delay of the level shift circuit through a positive feedback driving current enhancement technology and improves the speed of the whole driving circuit; the driving current is adaptively adjusted according to the load size and the frequency of the input control pulse, thereby improving the power efficiency of the driving circuit to the maximum extent.
Drawings
Fig. 1 is a structural diagram of a high-speed high-efficiency high-voltage half-bridge gate driving circuit according to the present invention.
FIG. 2 is a block diagram of an input receiving circuit according to the present invention.
Fig. 3 is a diagram showing a dead time generation circuit according to the present invention.
Fig. 4 is a diagram of a low-side delay circuit according to the present invention.
FIG. 5 is a diagram of a low voltage generating circuit according to the present invention.
FIG. 6 is a diagram of a low latency high voltage level shifter circuit according to the present invention.
FIG. 7 is a schematic diagram of the delay reduction principle of the low-delay high-voltage level shift circuit of the present invention.
FIG. 8 is a block diagram of the high reliability error hysteresis filter circuit according to the present invention.
FIG. 9 is a block diagram of the high-efficiency output driving circuit according to the present invention.
Fig. 10 is a flow chart of the adaptive adjustment process of driving capability according to the present invention.
Fig. 11 is a diagram illustrating the load detection principle of the present invention.
FIG. 12 is a block diagram of a load discriminating circuit according to the present invention.
FIG. 13 is a block diagram of a controller circuit according to the present invention.
Detailed Description
The present invention is described in further detail below with reference to the attached drawings and examples.
Fig. 1 is a block diagram of a high-speed, high-efficiency, high-voltage half-bridge gate driver circuit according to the present invention, which includes an input receiving circuit, a dead time generating circuit, a low voltage generating circuit, a low-side delay circuit, a low-side, high-efficiency output driving circuit L, a low-delay, high-voltage level shifting circuit, and a high-side, high-efficiency output driving circuit H.
The low-voltage digital input signals HI and HI firstly enter an input receiving circuit to carry out signal level discrimination and logic level high-voltage conversion to obtain medium-voltage signals H and L, a dead time generating circuit obtains high-side differential input data HIP and HIN according to the medium-voltage signal H and obtains low-side differential input data L IP and L IN according to a medium-voltage signal L, the high-side differential input data HIP and HIN enter a low-delay high-voltage level shifting circuit to obtain high-side driving data Din with floating low potential, the Din enters a high-efficiency output driving circuit, and a high-side output signal HO with large driving capacity is obtained through driving amplification, and the low-side differential input data L IP and L IN enter a low-side delay circuit to obtain low-side driving data and output the low-side high-efficiency output driving circuit L to obtain a low-side output signal L O with large driving capacity through driving amplification;
the low-side high-efficiency output driving circuit L and the high-side high-efficiency output driving circuit H are high-efficiency output driving circuits with completely identical circuit structures, the low-delay high-voltage level shifter circuit needs to use two groups of ground potentials of a low-voltage ground VSS and a floating ground SW at the same time, the high-side high-efficiency output driving circuit H only needs to use the floating ground SW, the input receiving circuit, the dead time generating circuit, the low-voltage generating circuit, the low-side delay circuit and the low-side high-efficiency output driving circuit L share the low-voltage ground VSS, the driving capacity of the high-efficiency output driving circuit is controlled by Start-up signals, Clk-ctrl and n reference voltages Vr 1-Vrn of a trigger control clock signal, the input receiving circuit needs to use a low-voltage power supply voltage VC L and a medium-voltage power supply voltage VCC at the same time, the low-voltage generating circuit generates a low-voltage power supply voltage VC L and n reference voltages 1-Vr n according to the medium-voltage power supply voltage VCC, wherein n.
A basic input receiving circuit structure for a high voltage gate driving chip of the present invention is shown in FIG. 2, and comprises two same input channels, each channel comprises an input ESD protection circuit, a level decision circuit and a medium voltage level shift circuit, the input receiving circuit not only completes the transmission of signals, but also completes the ESD protection of the circuits inside the chip, and prevents the damage of the circuits due to the impact of ESD on the circuit inside, the ESD protection circuit commonly used in the design of integrated circuits has a transverse SCR clamp circuit, an inverse parallel diode clamp circuit, a Zener clamp circuit and a CDM clamp, etc., the level decision circuit is used for identifying whether the external input level is logic "0" or "1", the level decision circuit has enough noise tolerance due to the existence of large interference of external signals, the specific circuit implementation generally comprises 2 types, one is a Schmitt trigger, one is a hysteresis comparator, the speed is different according to the driving object of the driving chip and the input logic signal, the implementation of the Schmitt trigger and the comparator has large difference, the implementation circuit has large difference, the input voltage VCC is generally 10, the input voltage of the driving chip is generally 10V 5, the input voltage of the input signal is generally converted into a logic level of the input voltage, the input voltage of the input signal is judged as well as a relatively lower than the input voltage of the input voltage, the input voltage of the input signal is generally, the input voltage of the input signal is generally equal to the input voltage of the input signal is generally equal to the input voltage of the input voltage.
Due to the existence of a large grid parasitic capacitance, when the power device is switched on or switched off, a certain time is required for charging and discharging the capacitance, and direct connection between two power devices of driven upper and lower bridge arms must be prevented. The dead time is a control means for ensuring the reliable operation of the high-side and low-side power devices, and is aimed at avoiding the simultaneous conduction, i.e. the shoot-through phenomenon, of the high-side and low-side devices to prevent the devices from being destroyed under the condition, and the dead time is to ensure that one device is turned on after being completely turned off. The dead time generating circuit adds an input square wave into the dead time as a driving signal of the high-side and low-side grid electrodes. A block diagram of the basic structure of the dead time generation circuit of the present invention is shown in fig. 3. The dead zone generating mode of the circuit is to adopt a delay circuit to enable two paths of input signals to generate phase difference, and then carry out logic operation on the input signals to obtain dead zone time. The magnitude of the dead time is determined by the delay time generated by the delay circuit, and thus the delay circuit is the core of the dead time circuit. The simplest structure of the delay circuit is an inverter + RC network, but the accuracy of the method is not enough, and the method can only meet the requirements of medium-low speed application occasions. The delay circuit with higher accuracy can be realized by a capacitor structure, a current source structure and a resistor structure.
After the high-end signal passes through the level shift circuit, a certain delay is generated compared with the low-end signal. For medium and high frequency applications, this time already causes phase mismatch of the high and low end signals, which may affect the normal operation of the system. Therefore, a delay matching circuit must be added to the low-side signal path to match the phases of the high-side and low-side signals. The structure of the low-side delay circuit according to the invention is shown in fig. 4. Structurally, in the delay circuit, the RS trigger is used for signal conversion, then the cross-coupling circuit is adopted, so that the rising edge and the falling edge of the signal are steeper, and the delay of the signal is realized through the RC network.
The low-voltage power supply circuit is a basic function module which any analog IC must be equipped with, the high-voltage half-bridge gate drive circuit can use the structure block diagram as shown in figure 5, the bias and power supply circuit comprises a starting circuit, a band gap reference circuit, a buffer, a bias circuit and an input low-voltage generating circuit, after the VCC voltage of a chip is electrified, the starting circuit is the circuit which is firstly started in the whole chip, the starting circuit usually provides a certain initial bias signal to the band gap reference voltage generating circuit to generate a fixed reference voltage and a reference current, the reference voltage then generates various reference voltages Vr1, Vr 2-Vrn required by the internal work of the chip through the reference voltage generating circuit and outputs the reference voltages through the driving buffer circuit, the reference current usually enters the bias signal generating circuit to generate various bias signals for providing bias for other analog circuits in the chip and simultaneously providing bias for the reference voltage generating circuit and the input interface module low-voltage power supply circuit, and the input low-voltage generating circuit usually generates 3-10V floatable low-voltage power supply voltage VC L.
FIG. 6 is a structural diagram of a low-delay high-voltage level shifter circuit according to the present invention, which is obtained by modifying a simple RS flip-flop into a highly reliable error hysteresis filter circuit based on FIG. 2, and adding enhancement transistors Me1 and Me2 for accelerating the rising speed of L SP and L SN, and a signal rollover detection circuit for controlling Me1 and Me 2. the low-delay high-voltage level shifter circuit includes, inside, a first high-voltage L DMOS transistor MD1, a second high-voltage L DMOS transistor MD2, a first protection diode D1, a second protection diode D2, a third resistor R3, a fourth resistor R4, a first resistor R1, a second resistor R2, a first coupling MOS transistor M1, a second coupling MOS transistor M2, a first speed enhancement Me transistor 1, a second speed enhancement transistor Me2, an error hysteresis filter circuit, and a signal rollover detection circuit.
The device comprises a first high-voltage DMOS transistor MD, a second high-voltage DMOS transistor MD, a third resistor R, a gate terminal of the second coupling MOS transistor M, a drain terminal of the second high-voltage DMOS transistor MD, a drain terminal of the first high-voltage DMOS transistor MD, a drain terminal of the second coupling MOS transistor M, an anode of the second protection diode D, a lower terminal of the fourth resistor R and a gate terminal of the first coupling MOS transistor M, a drain terminal of the error hysteresis filter circuit, a data input P terminal SP and a drain terminal of the first speed enhancement transistor Me, a drain terminal of the second coupling MOS transistor M, a drain terminal of the second resistor R, a drain terminal of the error input N terminal SN and a drain terminal of the second speed enhancement transistor Me, lower terminals of the first coupling MOS transistor R and the second coupling MOS transistor M, a drain terminal of the error hysteresis filter circuit, a drain terminal of the second coupling MOS transistor M, an output terminal of the error hysteresis filter circuit is connected with a floating ground SW, an output of a driving signal N, a driving signal of the error filter circuit, a drain terminal of the error signal input N is connected with a drain terminal of the first high-speed enhancement transistor D, a drain terminal of the first speed enhancement transistor D, a drain terminal of the second high-speed enhancement transistor M.
The principle of delay optimization of the invention is that a signal overturn detection circuit detects the change of Din, when the change of Din exceeds a certain threshold, the overturn speed of Din is accelerated, at the time t0, the voltage of L SP begins to change from 0 to 0, Din is caused to change from low to high from SW (in this case, voltage of VH) and at the time tdet, when the signal overturn detection circuit confirms that Din is changed from low to high and Din voltage exceeds the threshold of Vth-det of the signal overturn detection circuit, the signal overturn detection circuit starts a second speed enhancement Me transistor 2, accelerates the voltage rising speed of Vth L SP, so that Din rises from low to high to voltage of VH + Ditden, when the signal overturn detection circuit confirms that Din is changed from low to high and Din voltage exceeds the threshold of the signal overturn detection circuit, the signal overturn detection circuit starts a voltage rising speed of Vth 3825, accelerates the voltage rising speed of Vth L SP, the voltage rising speed of Din from VCC to Vth + is reduced, the time Diten, the voltage rising process that the DIn is increased from VCC to high voltage, the high voltage of the original power supply VH + and the TDen is reduced, the TDen voltage, the TDen delay detection circuit is designed to the high voltage, the TDen delay circuit is set as the high voltage, the delay error, the noise of the voice transmission error is reduced, the voice transmission error of the voice transmission speed of the.
FIG. 8 is a block diagram of a highly reliable error hysteresis filter circuit that may be used with the present invention. The circuit includes: the device comprises a P-end coupling phase inverter, a P-end deburring circuit, a P-end OR gate, a P-end data selector, an N-end coupling phase inverter, an N-end deburring circuit, an N-end OR gate and an N-end data selector circuit; the P-end deburring circuit and the N-end deburring circuit have the same structure, and the P-end deburring circuit and the N-end deburring circuit internally comprise 3 2-input NAND gates and a 2-input OR gate.
For the signal inversion detection circuit in fig. 6, it can be implemented by a conventional combinational logic circuit, and the simplest way is an inverter circuit, or an inverter circuit with a control function, where the inversion threshold of the inverter is Vth-det; the implementation mode with higher precision can be realized by adopting a high-speed comparator, wherein one end of the comparator is Vth-det, and the other end of the comparator is Din.
FIG. 9 is a block diagram of the high-efficiency output driving circuit of the present invention, which includes an input P-side inverter chain, an N-side inverter chain, N P-side output inverters, N N-side output inverters, N P-side output PMOS transistors Mp 1-Mpn, N N-side output NMOS transistors Mn 1-Mnn, N P-side output inverter control switches, N N-side output inverter control switches, a sampling switch SW, an input data switch Kin and a test data switch Kcal, a high-speed comparator array, an error filtering circuit, a load discriminating circuit, a driving current selecting circuit, an input pulse frequency discriminating circuit, and a controller circuit;
the P-end inverter chain comprises k cascaded P-end input buffer inverters, and the driving capability of the k inverters is gradually increased from the front stage to the rear stage; the N-terminal inverter chain comprises k-1 cascaded N-terminal input buffer inverters and a delay unit (delay), and the driving capacity of the k-1 inverters is gradually increased from the front stage to the rear stage; the delay time of the delay unit (delay) must be equal to the delay time of the front-most P-terminal input buffer inverter; the output of the P-end inverter chain is simultaneously connected to the left sides of the N P-end output inverter control switches, and the output of the N-end inverter chain is simultaneously connected to the left sides of the N N-end output inverter control switches; the P-terminal inverter chain is connected with the input end of the N-terminal inverter chain and also connected to the right side of the input data switch Kin and the test data switch Kcal; the right sides of the N P-end output inverter control switches are respectively connected with the grid ends of the N P-end output PMOS tubes, and the right sides of the N N-end output inverter control switches are respectively connected with the grid ends of the N N-end output NMOS tubes; the source ends of N P-end output PMOS tubes are simultaneously connected to power supply voltage, the source ends of N N-end output NMOS tubes are simultaneously connected to the ground, and the drain ends of the N P-end output PMOS tubes are simultaneously connected to the drain ends of the N N-end output NMOS tubes and the output Vout of the high-efficiency output driving circuit;
the output Vout of the high-efficiency output driving circuit enters a high-speed comparator array after being sampled by a sampling switch SW, is compared with n reference voltages to obtain a quantization code Dout, enters an error filtering circuit, and outputs a load detection code Dtest after being filtered; the input pulse frequency discrimination circuit compares and quantizes the frequency of the input data Din based on the test clock Clkcal to obtain a Din frequency discrimination code Dfin; the load detection code Dtest and the frequency discrimination code Dfin enter the load discrimination circuit at the same time to calculate to obtain a load evaluation code Dev; the driving current selection circuit selects and outputs switch control signals Kp 1-Kpn of N P-end output inverter control switches and switch control signals Kn 1-Knn of N N-end output inverter control switches according to the size of Dev;
the load test signal Dcal output by the controller circuit is connected to the left side of the test data switch Kcal, the test clock Clkcal output by the controller circuit is connected to the clock input end of the input pulse frequency discrimination circuit, the load test control signal Ctrl _ test output by the controller circuit is respectively connected to the control signal input ends of the high-speed comparator array and the error filter circuit, the control signal Ctrl _ ev output by the controller circuit is connected to the control signal input end of the load discrimination circuit, the Ctrl _ out signal output by the controller circuit is connected to the control signal input end of the drive current selection circuit, and the Ctrl _ fin signal output by the controller circuit is connected to the control signal input end of the input pulse frequency discrimination circuit; the controller circuit is controlled by a trigger control clock signal Clk-ctrl and a power-on signal Start-up; the frequency of the trigger control clock signal Clk-ctrl must be R times the frequency of the load test signal Dcal; wherein n, k and R are any positive integer.
Fig. 9 shows the high-efficiency output driving circuit according to the present invention, which has two modes of adaptive adjustment of driving capability and normal operation. After the power supply voltage is electrified, the high-efficiency output driving circuit firstly starts a driving capability self-adaptive adjusting mode and then enters a normal working mode.
The adaptive adjustment process of the driving capability of the high-efficiency output driving circuit is shown in fig. 10. After the power supply voltage is electrified, the electrifying Start-up signal is started to be effective from low to high; the controller circuit closes the input data switch Kin, outputs a test clock Clkcal, and opens a deep pulse frequency discrimination circuit, and the input pulse frequency discrimination circuit compares and quantizes the frequency of the input data Din based on the test clock Clkcal to obtain a Din frequency discrimination code Dfin; the controller circuit then turns on the test data switches Kcal, Kp1 and Kn1, and outputs the load test signal Dcal, and in addition, turns on the high-speed comparator array, the error filtering circuit, the load judging circuit and the driving current selecting circuit, and the output Vout of the driving circuit generates different dv/dt changes according to different loads; at the Mth Clk-ctrl clock edge after the Dcal output, when the output setup time (the time required for Vout voltage to rise) is satisfied, the controller circuit will turn on the sampling switch SW to sample the Vout voltage, and the load detection code Dtest is obtained by processing through the high-speed comparator array and the error filtering circuit; the load judging circuit calculates to obtain a load evaluation code Dev according to the load detection code Dtest and the Din frequency judging code Dfin; the driving current selection circuit sets switch control signals Kp 2-Kpn and Kn 2-Knn according to the load evaluation code Dev and keeps the same; at this time, the output driving capability of the high-efficiency output driving circuit is kept unchanged, and the driving capability adaptive adjustment mode is ended; the controller circuit finally turns on the switch Kin, turns off the switch Kal and the load test signal Dcal, and the output driving circuit starts the normal operation mode.
The self-adaptive adjustment process of the driving capability of the output high-efficiency driving circuit is triggered by a power-on Start-up signal, the power-on Start-up signal is effective from low to high, and a clock Clk-ctrl enters a controller circuit; the controller circuit starts a deep pulse frequency discrimination circuit to output a test clock Clkcal, the input pulse frequency discrimination circuit compares and quantizes the frequency of input data Din based on the test clock Clkcal, and Din frequency discrimination codes Dfin are obtained through J test clocks Clkcal; the controller circuit then outputs a load test signal Dcal, and the output Vout of the driving circuit generates different dv/dt changes according to different loads; at the Mth Clk-ctrl clock edge after the Dcal output, the controller circuit will turn on the sampling switch SW to sample the Vout voltage, and the load detection code Dtest is obtained by the processing of the high-speed comparator array and the error filtering circuit; the load judging circuit calculates a load evaluation code Dev at the Juge clock edge according to the load detection code Dtest and the Din frequency judging code Dfin, and keeps the load evaluation code Dev unchanged; the driving current selection circuit sets switch control signals Kp 2-Kpn and Kn 2-Knn according to the load evaluation code Dev and keeps the same; and finally, the power-on Start-up signal is changed from high to low to be invalid, the output driving capability of the output driving circuit is kept unchanged, and the driving capability self-adaptive adjustment mode is ended.
In the adaptive adjustment process of the driving capability, the frequency of the control clock Clk-ctrl must be much higher than the frequency of the input data Din, for example, the Din frequency is 100KHz, and the Clk-ctrl frequency is usually set above 10 MHz; the frequency of the test clock Clkcal cannot be lower than the frequency of the control clock Clk-ctrl, and the higher the Clkcal frequency, the more accurate the discrimination of the Din frequency.
In the process of comparing and quantizing the frequency of the input data Din by the input pulse frequency judging circuit, the time length of J test clock Clkcal periods is required to be larger than an integer period of the Din. For example, if Din has a frequency of 100KHz and the test clock Clkcal has a frequency of 10MHz, then Din and Clkcal have corresponding signal periods of 10us and 0.1us, respectively, and J must be greater than 100. If Clkcal has a frequency X times Din, then J must be a positive integer greater than X, and it is clear that the larger the value of J, the more precise the value of Dfin, and X is a positive number greater than 1.
The Mth Clk-ctrl clock edge after the Dcal output, whose time span must be less than 1 cycle time of Dcal. For example, if the Dcal frequency is 200KHz and the Clk-ctrl frequency is 5MHz, then Dcal and Clk-ctrl correspond to signal periods of 5us and 0.2us, respectively, then the value of M must be less than 25, and obviously the closer the value of M is to 25, the more accurate the value of Dtest is.
Fig. 11 is a diagram illustrating the load detection principle of the present invention. Assuming that after the high efficiency output driver circuit shown in fig. 10 turns on Kp1 and Kn1, the output currents provided by the N-side output NMOS transistor Mn1 and the P-side output PMOS transistor Mp1 are 0.5A, the frequency of Clk-ctrl is 5MHz (corresponding to a signal period of 0.2us), and M is selected to be 5, the sampling switch SW samples the Vout voltage at the beginning of 1us of Dcal high level. For a fixed output Iout, it is obvious that the larger the load capacitance is driven, the lower the rising slope of Vout, and the inverse relationship between the Vout voltage and the load capacitance is established at 1us, i.e. the Vout voltage at 0.5nF should be 3 times the Vout voltage at 1.5 nF. Therefore, under the condition of a fixed driving current, the size of the output driving load can be determined according to the voltage Vout in 1us, and the size of the output driving load can be quantized by comparing the voltage Vout with n reference voltages Vr 1-Vrn to obtain a load quantization code Dout.
According to the embodiment of the invention, under the condition of fixed driving current, the work of comparing and quantizing the Vout voltage and n reference voltages Vr 1-Vrn at 1us is realized by the high-speed comparator array, the function of the comparator array is similar to that of an ADC (analog to digital converter) circuit, and therefore, the combination forms of the comparator array are various according to the difference of the quantization speeds of load detection. The Vout voltage and n reference voltages Vr 1-Vrn can be compared and quantized by adopting n comparators, and the load quantization code Dout can be obtained by comparison in one clock period, the total scheme has the advantage of high speed, but the number of the used comparators is large, and the hardware overhead is large; the total scheme has the advantage of low hardware overhead, but the speed is relatively slow when the same comparator is used for multiple times. The n reference voltages Vr 1-Vrn are also arranged in a matched way with the comparator combined strategy, and can be arranged at uniform intervals by adopting thermometer codes or arranged at different weights in a binary system. Therefore, in practical implementation, a proper comparator type and combination strategy can be selected according to the requirements of the driver chip application system.
Because the high-speed comparator has certain offset, and the higher the working speed of the comparator is, the more serious the offset is, for this reason, the error filtering needs to be carried out on the load quantization code Dout to obtain the load detection code Dtest, and the realization of the error filtering circuit has great difference according to the combination realization strategy of the type of the Dout code and the front-end high-speed comparator array circuit. If the comparator array circuit adopts n comparators to work in parallel, a digital algorithm for offset calibration of a Flash ADC comparator is adopted for error filtering; if the comparator array circuit adopts 1 comparator for multiplexing work, a digital algorithm for SAR ADC offset calibration needs to be adopted for error filtering.
Fig. 12 is a block diagram showing a load discrimination circuit according to the present invention, which includes 2 registers 1 and 2 for storing the load detection code Dtest and the frequency discrimination code Dfin, respectively, and a normalization quantization calculation circuit for performing calculation processing on the load detection code Dtest and the frequency discrimination code Dfin. The data output of register 1 and register 2 is controlled by the Juge signal. The load evaluation code Dev output by the normalization quantization calculation circuit is calculated by Dtest and Dfin, and the calculation formula is: dev G Dtest/Dfin. Where G is a gain factor, which is an empirical value, and is usually a positive number greater than 1 in practical applications, according to the application context of the output driver circuit of the present invention.
The practical function of the normalization quantization calculation circuit is to further optimize the output driving current of the output driving circuit according to the present invention according to the frequency of the input data Din. Because the load test signal Dcal is a fixed frequency signal, after the output load is tested, if the frequency of the input data Din is far less than that of Dcal, the driving current can be continuously reduced, thereby further improving the efficiency of the driving circuit and saving unnecessary power consumption overhead. For example, if Din and Dcal correspond to signal periods of 10us and 1us, respectively, then Din is slower by 10 times in frequency and the charging time of the load capacitor can be extended by 10 times with respect to a fixed load, so that a smaller driving current can be selected for charging and discharging the output load. Therefore, under the condition of meeting the requirement of the application system of the driving circuit, the coefficient G can be set to scale the Dev value, the output driving current is reduced, the efficiency of the driving circuit is further improved, and unnecessary power consumption expense is saved.
Fig. 13 is a block diagram of a controller circuit according to the present invention, which functions to provide control signals required for other circuits to operate according to an external trigger control clock signal and a power-on signal. The controller circuit internally includes: a frequency discrimination control generating circuit for generating a Ctrl _ fin signal to control the input pulse frequency discrimination circuit; a switching signal generating circuit for generating switching control signals Kcal, SW and Kin; the load test control generation circuit is used for generating a load test control signal Ctrl _ test to control the high-speed comparator array and the error filtering circuit; the load discrimination control generation circuit is used for generating a Ctrl _ ev signal to control the load discrimination circuit; the drive current control generating circuit is used for generating a Ctrl _ out signal to control the drive current selecting circuit; a test code generation circuit for generating a load test code Dcal; the counter circuit is used for providing the other control signals according to the external trigger control clock signal Clk-ctrl and the power-on signal Start-up to generate the required trigger signals.
The input pulse frequency discrimination circuit has the circuit function of comparing and quantizing the frequency of input data Din by adopting a test clock Clkcal, and the function can be realized by adopting a phase discriminator circuit. The drive current selection circuit can adopt a decoder or a multiplexer to realize signal switch selection.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (9)
1. A high-speed high-efficiency high-voltage half-bridge gate drive circuit is characterized by comprising an input receiving circuit, a dead time generating circuit, a low-voltage generating circuit, a low-side delay circuit, a low-side high-efficiency output drive circuit L, a low-delay high-voltage level shift circuit and a high-side high-efficiency output drive circuit H;
the low-voltage digital input signals HI and HI firstly enter an input receiving circuit to carry out signal level discrimination and logic level high-voltage conversion to obtain medium-voltage signals H and L, a dead time generating circuit obtains high-side differential input data HIP and HIN according to the medium-voltage signals H and obtains low-side differential input data L IP and L IN according to a medium-voltage signal L, the high-side differential input data HIP and HIN enter a low-delay high-voltage level shifting circuit to obtain high-side driving data with low potential floating, and then enter a high-efficiency output driving circuit to obtain a high-side output signal HO with larger driving capacity through driving amplification, and the low-side differential input data L IP and L IN enter a low-side delay circuit to obtain low-side driving data and output the low-side to a high-efficiency output driving circuit L to obtain a low-side output signal L O with larger driving capacity through driving amplification;
the low-side high-efficiency output driving circuit L and the high-side high-efficiency output driving circuit H are high-efficiency output driving circuits with completely identical circuit structures, the low-delay high-voltage level shifter circuit needs to use two groups of ground potentials of a low-voltage ground VSS and a floating ground SW at the same time, the high-side high-efficiency output driving circuit H only needs to use the floating ground SW, the input receiving circuit, the dead time generating circuit, the low-voltage generating circuit, the low-side delay circuit and the low-side high-efficiency output driving circuit L share the low-voltage ground VSS, the driving capacity of the high-efficiency output driving circuit is controlled by Start-up signals, Clk-ctrl and n reference voltages Vr 1-Vrn of a trigger control clock signal, the input receiving circuit needs to use a low-voltage power supply voltage VC L and a medium-voltage power supply voltage VCC at the same time, the low-voltage generating circuit generates a low-voltage power supply voltage VC L and n reference voltages 1-Vr n according to the medium-voltage power supply voltage VCC, wherein n.
2. The high speed, high efficiency, high voltage half bridge gate driver circuit as claimed in claim 1, wherein said low voltage generating circuit comprises: the circuit comprises a starting circuit, a band gap reference circuit, a buffer, a biasing circuit and an input low voltage generating circuit; after the voltage VCC of the medium-voltage power supply is electrified, the starting circuit is firstly started, and a certain initial bias signal is provided for the band-gap reference voltage generating circuit to generate a fixed reference voltage and a reference current;
the fixed reference voltage is used for generating n reference voltages Vr 1-Vrn required by the internal work of the chip through a reference voltage generating circuit and outputting the n reference voltages through a driving buffer circuit, the reference current usually enters a bias signal generating circuit and generates various bias signals for providing bias for other analog circuits in the chip and also provides bias for the reference voltage generating circuit and an input low voltage generating circuit, and the input low voltage generating circuit finally generates a low-voltage power supply voltage VC L.
3. The high-speed high-efficiency high-voltage half-bridge gate driving circuit as claimed in claim 1, wherein the low-delay high-voltage level shifter circuit comprises a first high-voltage L DMOS transistor MD1, a second high-voltage L DMOS transistor MD2, a first protection diode D1, a second protection diode D2, a third resistor R3, a fourth resistor R4, a first resistor R1, a second resistor R2, a first coupling MOS transistor M1, a second coupling MOS transistor M2, a first speed enhancement transistor Me1, a second speed enhancement transistor Me2, an error hysteresis filter circuit and a signal flip detection circuit;
the device comprises a first high-voltage DMOS transistor MD, a second high-voltage DMOS transistor MD, a third resistor R, a gate terminal of the second coupling MOS transistor M, a drain terminal of the second high-voltage DMOS transistor MD, a drain terminal of the first high-voltage DMOS transistor MD, a drain terminal of the second coupling MOS transistor M, an anode of the second protection diode D, a lower terminal of the fourth resistor R and a gate terminal of the first coupling MOS transistor M, a drain terminal of the error hysteresis filter circuit, a data input P terminal SP and a drain terminal of the first speed enhancement transistor Me, a drain terminal of the second coupling MOS transistor M, a drain terminal of the second resistor R, a drain terminal of the error input N terminal SN and a drain terminal of the second speed enhancement transistor Me, lower terminals of the first coupling MOS transistor R and the second coupling MOS transistor M, a drain terminal of the error hysteresis filter circuit, a drain terminal of the second coupling MOS transistor M, an output terminal of the error hysteresis filter circuit is connected with a floating ground SW, an output of a driving signal N, a driving signal of the error filter circuit, a drain terminal of the error signal input N is connected with a drain terminal of the first high-speed enhancement transistor D, a drain terminal of the first speed enhancement transistor D, a drain terminal of the second high-speed enhancement transistor M.
4. The high speed, high efficiency, high voltage half bridge gate drive circuit of claim 3, wherein said highly reliable error hysteresis filter circuit comprises: the device comprises a P-end coupling phase inverter, a P-end deburring circuit, a P-end OR gate, a P-end data selector, an N-end coupling phase inverter, an N-end deburring circuit, an N-end OR gate and an N-end data selector circuit; the P-end deburring circuit and the N-end deburring circuit have the same structure, and the P-end deburring circuit and the N-end deburring circuit internally comprise 3 2-input NAND gates and a 2-input OR gate.
5. The high speed, high efficiency, high voltage half bridge gate driver circuit of claim 1, wherein said high efficiency output driver circuit comprises: the device comprises an input P-end inverter chain, an N-end inverter chain, N P-end output inverters, N N-end output inverters, N P-end output PMOS (P-channel metal oxide semiconductor) tubes, N N-end output NMOS (N-channel metal oxide semiconductor) tubes, N P-end output inverter control switches, N N-end output inverter control switches, a sampling switch SW, an input data switch Kin, a test data switch Kcal, a high-speed comparator array, an error filtering circuit, a load judging circuit, a driving current selecting circuit, an input pulse frequency judging circuit and a controller circuit;
the P-end inverter chain comprises k cascaded P-end input buffer inverters, and the driving capability of the k inverters is gradually increased from the front stage to the rear stage; the N-end inverter chain comprises k-1 cascaded N-end input buffer inverters and a delay unit, and the driving capability of the k-1 inverters is gradually increased from a front stage to a rear stage; the delay time of the delay unit must be equal to the delay time of the front-end P-end input buffer inverter; the output of the P-end inverter chain is simultaneously connected to the left sides of the N P-end output inverter control switches, and the output of the N-end inverter chain is simultaneously connected to the left sides of the N N-end output inverter control switches; the P-terminal inverter chain is connected with the input end of the N-terminal inverter chain and also connected to the right side of the input data switch Kin and the test data switch Kcal;
the right sides of the N P-end output inverter control switches are respectively connected with the gate ends of the N P-end output PMOS tubes, and the right sides of the N N-end output inverter control switches are respectively connected with the gate ends of the N N-end output NMOS tubes; the source ends of the N P-end output PMOS tubes are simultaneously connected to power supply voltage, the source ends of the N N-end output NMOS tubes are simultaneously connected to the ground, and the drain ends of the N P-end output PMOS tubes are simultaneously connected to the drain ends of the N N-end output NMOS tubes and the output Vout of the driving circuit;
the output Vout of the driving circuit enters a high-speed comparator array after being sampled by a sampling switch SW, is compared with n reference voltages, and then enters an error filtering circuit to output a load detection code Dtest; the input pulse frequency discrimination circuit compares and quantizes the frequency of input data Din to obtain a Din frequency discrimination code Dfin; the load detection code Dtest and the frequency discrimination code Dfin enter a load discrimination circuit at the same time to calculate to obtain a load evaluation code Dev; the driving current selection circuit selects and outputs switch control signals of N P-end output inverter control switches and switch control signals of N N-end output inverter control switches according to the size of Dev;
the load test signal Dcal output by the controller circuit is connected to the left side of a test data switch Kcal, a test clock Clkcal output by the controller circuit is connected to a clock input end of an input pulse frequency discrimination circuit, a load test control signal Ctrl _ test output by the controller circuit is respectively connected to a control signal input end of the high-speed comparator array and a control signal input end of the error filtering circuit, a control signal Ctrl _ ev output by the controller circuit is connected to a control signal input end of the load discrimination circuit, a Ctrl _ out signal output by the controller circuit is connected to a control signal input end of the driving current selection circuit, and a Ctrl _ fin signal output by the controller circuit is connected to a control signal input end of the input pulse frequency discrimination circuit; the controller circuit is controlled by a trigger control clock signal Clk-ctrl and a power-on signal Start-up;
the frequency of the trigger control clock signal Clk-ctrl must be R times the frequency of the load test signal Dcal;
wherein k and R are any positive integer.
6. The high speed, high efficiency, high voltage half bridge gate driver circuit as claimed in claim 5, wherein the operating conditions of said high efficiency output driver circuit include adaptive adjustment of driving capability and normal operation; when the power supply voltage is electrified, firstly, a driving capability self-adaptive adjustment mode is started, and then a normal working mode is entered;
the working process in the driving capability adaptive adjustment mode is as follows:
after the power supply voltage is electrified, the controller circuit closes the input data switch Kin, outputs a test clock Clkcal, and opens the deep pulse frequency discrimination circuit, and the input pulse frequency discrimination circuit compares and quantizes the frequency of the input data Din based on the test clock Clkcal to obtain a Din frequency discrimination code Dfin;
when the output setup time is met, the controller circuit turns on a test data switch Kcal and outputs a load test signal Dcal, and in addition, a high-speed comparator array, an error filtering circuit, a load judging circuit and a driving current selection circuit are turned on, and the output Vout of the driving circuit changes according to different loads;
the controller circuit starts a sampling switch SW to sample the Vout voltage, and a load detection code Dtest is obtained after the sampling switch SW is processed by a high-speed comparator array and an error filtering circuit;
the load judging circuit calculates to obtain a load evaluation code Dev according to the load detection code Dtest and the Din frequency judging code Dfin;
the driving current selection circuit sets the switch control signals of the N P-end output inverter control switches and the switch control signals of the N N-end output inverter control switches according to the load evaluation code Dev, and keeps the switch control signals unchanged;
the output setup time consists of M Clk-ctrl clock cycles, the time span of which must be less than 1 cycle time of Dcal; wherein M is a positive integer less than R;
the process of comparing and quantizing the frequency of the input data Din by the input pulse frequency discrimination circuit needs to quantize the frequency of the Din by using J test clock Clkcal periods, and the time length of the J test clock Clkcal periods must be larger than the integer period of the Din; that is, the frequency of the test clock Clkcal is X times the frequency of the input data Din; wherein X is a positive number greater than 1, and J is a positive integer greater than X.
7. The high speed, high efficiency, high voltage half bridge gate driver circuit as claimed in claim 5, wherein said controller circuit internally comprises: a frequency discrimination control generating circuit for generating a Ctrl _ fin signal to control the input pulse frequency discrimination circuit; a switching signal generating circuit for generating switching control signals Kcal, SW and Kin; the load test control generation circuit is used for generating a load test control signal Ctrl _ test to control the high-speed comparator array and the error filtering circuit; the load discrimination control generation circuit is used for generating a Ctrl _ ev signal to control the load discrimination circuit; the drive current control generating circuit is used for generating a Ctrl _ out signal to control the drive current selecting circuit; a test pattern generation circuit for generating a load test pattern Dcal and a test clock Clkcal; the counter circuit is used for providing the other control signals according to the external trigger control clock signal Clk-ctrl and the power-on signal Start-up to generate the required trigger signals.
8. The high speed, high efficiency, high voltage half bridge gate drive circuit of claim 7, wherein: the frequency of the external trigger control clock Clk-ctrl must be much higher than the frequency of the input data Din; the frequency of the test clock Clkcal cannot be lower than the frequency of the control clock Clk-ctrl, and the higher the Clkcal frequency, the more accurate the discrimination of the Din frequency.
9. The high speed, high efficiency, high voltage half bridge gate driver circuit as claimed in claim 5, wherein the load discrimination circuit comprises: 2 registers used for storing the load detection code Dtest and the frequency discrimination code Dfin respectively, and a normalization quantization calculation circuit for calculating the load detection code Dtest and the frequency discrimination code Dfin;
the data output of the 2 registers is controlled by the same signal; the load evaluation code Dev output by the normalization quantization calculation circuit is calculated by Dtest and Dfin, and the calculation formula is: dev ═ G × Dtest/Dfin; wherein G is a gain coefficient and is a positive number greater than 1.
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| CN113067564B (en) * | 2021-03-31 | 2022-03-01 | 无锡英诺赛思科技有限公司 | High-efficiency insulation isolation SiCMOS (silicon-on-insulator-semiconductor field effect transistor) gate drive circuit |
| CN113078801A (en) * | 2021-03-31 | 2021-07-06 | 无锡英诺赛思科技有限公司 | Ultrahigh-voltage insulated isolation IGBT half-bridge gate driving circuit |
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| CN113067564A (en) * | 2021-03-31 | 2021-07-02 | 无锡英诺赛思科技有限公司 | High-efficiency insulation isolation SiC MOSFET gate drive circuit |
| CN113067567A (en) * | 2021-03-31 | 2021-07-02 | 江苏中科汉韵半导体有限公司 | Ultrahigh-voltage insulation isolation SiC MOSFET gate drive circuit |
| CN113162378A (en) * | 2021-03-31 | 2021-07-23 | 黄山学院 | High-efficiency intelligent high-voltage insulated isolation half-bridge gate driving circuit |
| CN113098471B (en) * | 2021-03-31 | 2022-04-05 | 无锡英诺赛思科技有限公司 | Ultra-high-speed insulated isolation GaN half-bridge gate driving circuit |
| CN113067567B (en) * | 2021-03-31 | 2024-04-30 | 江苏中科汉韵半导体有限公司 | Ultra-high voltage insulation isolation SiC MOSFET gate driving circuit |
| CN113659972A (en) * | 2021-09-13 | 2021-11-16 | 复旦大学 | Drive circuit and electronic device |
| CN113659972B (en) * | 2021-09-13 | 2024-01-05 | 复旦大学 | Driving circuit and electronic device |
| CN113872709B (en) * | 2021-10-14 | 2023-10-24 | 上海橙科微电子科技有限公司 | System for continuously monitoring presence or absence of high-speed signal |
| CN113872709A (en) * | 2021-10-14 | 2021-12-31 | 上海橙科微电子科技有限公司 | System for continuously monitoring existence of high-speed signals |
| CN114244083A (en) * | 2021-12-17 | 2022-03-25 | 无锡惠芯半导体有限公司 | High-speed MOSFET half-bridge gate drive circuit |
| CN114583927A (en) * | 2022-04-20 | 2022-06-03 | 成都功成半导体有限公司 | Drive current adjustable power device drive circuit |
| CN115242106A (en) * | 2022-07-29 | 2022-10-25 | 无锡惠芯半导体有限公司 | High-frequency MOSFET half-bridge intelligent power module |
| CN115242106B (en) * | 2022-07-29 | 2024-08-02 | 无锡惠芯半导体有限公司 | High-frequency MOSFET half-bridge intelligent power module |
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Address after: 245000 No. 39 West Sea Road, Tunxi District, Anhui, Huangshan City Applicant after: HUANGSHAN University Applicant after: Huangshan core Microelectronics Co., Ltd Address before: 245000 No. 39 West Sea Road, Tunxi District, Anhui, Huangshan City Applicant before: HUANGSHAN University Applicant before: HUANGSHAN ELECTRIC APPLIANCE Co.,Ltd. |
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