CN113067567A

CN113067567A - Ultrahigh-voltage insulation isolation SiC MOSFET gate drive circuit

Info

Publication number: CN113067567A
Application number: CN202110347567.6A
Authority: CN
Inventors: 陈珍海; 袁述; 卢基存; 黎力
Original assignee: Jiangsu Zhongkehanyun Semiconductor Co ltd
Current assignee: Jiangsu Zhongkehanyun Semiconductor Co ltd
Priority date: 2021-03-31
Filing date: 2021-03-31
Publication date: 2021-07-02
Anticipated expiration: 2041-03-31
Also published as: CN113067567B

Abstract

The invention discloses an ultrahigh voltage insulation isolation SiC MOSFET gate drive circuit, which comprises: the device comprises an input receiving circuit, a digital control circuit, a modulation transmitting circuit, a high-voltage isolation circuit, a high common-mode transient suppression differential signal receiving circuit, an output driving circuit, a transmitting end low-voltage generating circuit, a receiving end low-voltage generating circuit and a chip state monitoring circuit. On one hand, the ultrahigh voltage insulation isolation SiC MOSFET gate drive circuit provided by the invention adopts a high voltage insulation isolation technology, so that ultrahigh voltage-resistant insulation capacitance can be realized; on the other hand, the magnitude of the ground potential common mode transient noise can be automatically detected, and the error generated by the common mode transient noise is dynamically compensated when the noise exceeds a threshold value. The invention can be widely applied to driving various high-voltage SiC MOSFET and IGBT devices.

Description

Ultrahigh-voltage insulation isolation SiC MOSFET gate drive circuit

Technical Field

The invention relates to an ultrahigh voltage insulation isolation SiC MOSFET gate drive circuit, and belongs to the technical field of integrated circuits.

Background

Under the traction of emerging industries such as smart grids, mobile communication, new energy automobiles and the like, power electronic application systems require further improvement of efficiency, miniaturization and added functions of the systems, and particularly require trade-offs among size, quality, power and efficiency of system equipment, such as server power management, battery chargers and micro-inverters of solar farms. With the advent and widespread use of Si-based superjunction MOSFETs and Insulated Gate Bipolar Transistors (IGBTs), silicon devices have begun to be unsuitable for some high voltage, high temperature, high efficiency and high power density applications due to their physical property limitations. Compared with Si materials, the high thermal conductivity of SiC materials determines the high current density characteristics of the SiC materials, and the high breakdown field strength and the high working temperature of SiC devices are determined by the high forbidden band width of the SiC materials. Particularly, in the aspects of development and application of the SiC MOSFET, compared with the Si MOSFET with the same power grade, the SiC MOSFET has greatly reduced on-resistance and switching loss, is suitable for higher working frequency, and greatly improves the high-temperature stability due to the high-temperature working characteristic.

Because the device characteristics of the SiC MOSFET are greatly different from those of the traditional Si MOSFET, the performance of the SiC MOSFET drive circuit plays a crucial role in the whole system. A new generation of power electronic complete machine system based on SiC devices puts higher demands on the driving speed and the intellectualization of a high-voltage grid driving chip, thereby further improving the reliability of the complete machine and reducing the design complexity of the complete machine system. Compared with a Si MOSFET, a SiC MOSFET has smaller parasitic capacitance, which differs by more than ten times, and thus is more sensitive to parasitic parameters of a driving circuit. On the other hand, the drive voltage range of SiC MOSFETs is typically-5V- +25V, whereas the drive voltage range of conventional Si MOSFETs is-30V- + 30V. Therefore, the SiC MOSFET has a smaller safety threshold than the conventional Si MOSFET, and a voltage spike of the driving circuit is likely to break down the oxide layer between the gate and the source, which also requires careful design of the output control level of the driving circuit.

The high-voltage gate driving chip is used for meeting the requirements of switching driving between a low-power level signal provided by an output interface of the CPU controller and a high-voltage high-current signal required by gate driving of a high-power output device. The core function of the gate drive IC in the whole system is to convert a low-power level signal (1mA/3-5V) output by a CPU controller into a high-voltage high-current signal (0.5-5A/5-20V) required by gate drive of a high-power device, amplify output current and output voltage swing, and have an isolation region signal transmission module in charge of signal transmission between two sides of an isolation region in a chip because signal connection is required between high-voltage and low-voltage region circuits. Due to the fact that application scenes of the power semiconductor devices are different greatly, voltage difference of VH existing between maximum values of a high voltage region and a low voltage region can span from 40V to 6500V, current spans from a few amperes to hundreds of amperes, switching frequency spans from a few KHz to a few MHz, and requirements of different application scenes on performance and cost of a gate drive IC are completely different. The VH size directly determines the electrical isolation grade in the chip, and different grades of electrical isolation are realized in the chip to form a circuit, so that the technology and cost quality grade of circuit devices required to be adopted are greatly different. The high-voltage electrical isolation technology for the gate drive IC mainly includes two major types, namely, monolithic integration isolation technology and physical insulation isolation technology. The isolation technology of the monolithic integration is mainly a PN junction isolation technology which is commonly used for realizing a monolithic integration gate drive IC product below 650V; the insulation isolation technology isolates the high-voltage and low-voltage signal processing circuit in a physical space, and the ultra-high voltage electrical isolation exceeding 6500V can be realized.

Fig. 1 shows a schematic diagram of a capacitive isolation driving circuit architecture in the prior art, in which two signal communication modules: the transmitting-side circuit and the receiving-side circuit are connected to ground voltages Vgnd1 and Vgnd2, respectively, wherein an isolation circuit 20 is provided to isolate the two ground voltages Vgnd1 and Vgnd 2. As is well known, DI is the input and RO is the output of a capacitively isolated driver circuit. In the transmission process of signals, firstly, the input DI controls the sending end circuit to generate a group of differential signals, the 2 groups of isolation capacitors configured between the sending end circuit and the receiving end circuit couple the differential signals from the sending end to the receiving end circuit, and the output signals RO are obtained through signal demodulation and output driving. However, since there is usually a certain level of common mode transient noise between the two ground voltages Vgnd1 and Vgnd2, the signal will generate errors during transmission. For example, spikes (spikes) between two ground voltages, power loops, or any loss on the system are among the common transient noise factors. The common mode transient noise VGND is generally defined to be equal to the voltage difference (VGND1-VGND2), and for a typical application scenario of a 1200V SiC MOSFET, the common mode transient noise VGND will periodically rise rapidly from 0V to 1200V, and then fall rapidly from 1200V to 0V. Under the interference of the common mode transient noise VGND, the voltage of the receiving terminal Vcm will produce a spike error, inevitably causing data errors of the receiving terminal circuit, and the influence of the common mode transient noise will be further deteriorated as the switching frequency increases. Therefore, in order to achieve highly reliable driving of SiC MOSFET devices, effective suppression of common mode transient noise is necessary.

Disclosure of Invention

The invention aims to overcome the defects in the prior art aiming at the driving application requirements of SiC MOSFET devices, and provides an ultrahigh voltage insulated gate driving circuit which is based on an insulated isolation technology and has high common-mode transient noise suppression characteristics.

According to the technical scheme provided by the invention, the ultrahigh voltage insulation isolation SiC MOSFET gate drive circuit comprises: the circuit comprises an input receiving circuit, a digital control circuit, a modulation transmitting circuit, an isolation circuit, a high common mode transient suppression differential signal receiving circuit, an output driving circuit, a transmitting end low voltage generating circuit, a receiving end low voltage generating circuit and a chip state monitoring circuit, wherein the input receiving circuit, the digital control circuit, the modulation transmitting circuit, the transmitting end low voltage generating circuit and the chip state monitoring circuit form a driving circuit transmitting end circuit, and the high common mode transient suppression differential signal receiving circuit, the output driving circuit and the receiving end low voltage generating circuit form a driving circuit receiving end circuit; the ground potentials of all circuits inside the sending end circuit of the driving circuit are connected to a sending end ground voltage Vgnd1, and the ground potentials of all circuits inside the receiving end circuit of the driving circuit are connected to a receiving end ground voltage Vgnd 2; the isolation circuit comprises a positive end sending capacitor Ctp, a negative end sending capacitor Ctn, a positive end receiving capacitor Crp and a negative end receiving capacitor Crn;

the input receiving circuit receives external low-level logic input data DI, converts the DI into input data Din with high level VCC and outputs the input data Din to the digital control circuit; the digital control circuit processes input data Din into a group of differential data DxP and DxN according to the states of an undervoltage protection signal UVLO, an over-temperature protection signal OTP and an over-current protection signal OCP provided by the chip state monitoring circuit; the differential data DxP and DxN enter a modulation transmitting circuit to obtain differential transmitting data TxP and TxN; the differential sending data TxP and TxN are respectively connected to the left end of a positive terminal sending capacitor Ctp and the left end of a negative terminal sending capacitor Ctn, the right end of the positive terminal sending capacitor Ctp and the right end of the negative terminal sending capacitor Ctn are respectively connected to the left end of a positive terminal receiving capacitor Crp and the left end of a negative terminal receiving capacitor Crn, differential receiving data RxP and RxN are respectively generated at the right end of the positive terminal receiving capacitor Crp and the right end of the negative terminal receiving capacitor Crn, the differential receiving data and the RxN enter a high common-mode transient suppression differential signal receiving circuit, and receiving output data Dout is obtained after processing; receiving output data Dout and finally entering an output driving circuit to generate an output driving signal DG with large driving current;

the transmitting end low-voltage generating circuit adopts transmitting end input power voltage VCCbus to generate transmitting end power voltage VCC and reference voltage and bias voltage required by each component circuit in the transmitting end circuit of the driving circuit; the receiving end low voltage generating circuit adopts receiving end input power voltage VDDBUS to generate receiving end power voltage VDD and reference voltage and bias voltage which are used for driving all the internal component circuits of the receiving end circuit of the circuit; the transmitting end low-voltage generating circuit and the receiving end low-voltage generating circuit are realized by adopting the same low-voltage generating circuit; the positive end sending capacitor Ctp, the negative end sending capacitor Ctn, the positive end receiving capacitor Crp and the negative end receiving capacitor Crn are equal in size and are all ultrahigh voltage-resistant isolation capacitors.

Specifically, the high common-mode transient suppression differential signal receiving circuit includes: the device comprises a differential input receiving circuit, an X-level front-back cascade common mode adjustable amplifying circuit, a high-sensitivity common mode adjustable amplifying circuit, an output shaping circuit and a common mode self-adaptive adjusting circuit; the differential input receiving circuit firstly receives a positive terminal receiving signal RxP and a negative terminal receiving signal RxN of differential receiving data, and obtains a positive terminal input signal Vip and a negative terminal input signal Vin through filtering processing; the positive end input signal Vip and the negative end input signal Vin enter a first-stage common mode adjustable amplifying circuit in X-stage common mode adjustable amplifying circuits which are cascaded in front and at the back, and finally a positive end output signal VoXp and a negative end output signal VoXn of the X-stage common mode adjustable amplifying circuit are obtained; the positive end output signal VoXp and the negative end output signal VoXn are respectively connected with the positive input end and the negative input end of the high-sensitivity common-mode adjustable amplifying circuit, and the high-sensitivity common-mode adjustable amplifying circuit outputs a group of differential output signals which comprise the positive end output signal VoXp and the negative end output signal VoXn; the output shaping circuit is used for processing to obtain final data output according to the positive end output signal VoXp and the negative end output signal VoXn, namely receiving output data Dout; the common mode self-adaptive adjusting circuit generates common mode adjusting signals C11, C12, C21, C22, …, CX1 and CX2 for each stage of amplifying circuit in a self-adaptive mode according to changes of power supply and ground voltage signals, and the common mode adjusting signals C11 and C12 generated by the common mode self-adaptive adjusting circuit are respectively connected to a common mode adjusting signal input end of the first stage of common mode adjustable amplifying circuit; the common mode adjusting signals C21 and C22 are respectively connected to the common mode adjusting signal input end of the second-stage common mode adjustable amplifying circuit; by analogy, the common mode adjusting signals CX1 and CX2 are respectively connected to the common mode adjusting signal input end of the X-th order common mode adjustable amplifying circuit; the common mode self-adaptive adjusting circuit also generates common mode adjusting signals CN1 and CN2 which are respectively connected to a common mode adjusting signal input end of the high-sensitivity common mode adjustable amplifying circuit; wherein X is a positive integer greater than 1, and N is a positive integer greater than X.

Specifically, the differential input receiving circuit includes: the common-mode receiver comprises a positive-end isolation capacitor C51, a positive-end grounding resistor R51, a positive-end coupling capacitor C52, a positive-end common-mode resistor R53, a negative-end isolation capacitor C53, a negative-end grounding resistor R52, a negative-end coupling capacitor C54, a negative-end common-mode resistor R54 and a receiving common-mode generating circuit; the left end of the positive side isolation capacitor C51 and the left end of the negative side isolation capacitor C53 are connected to a positive side receiving signal RXP and a negative side receiving signal RXN, respectively; the right end of the positive side isolation capacitor C51 is connected to the lower end of the positive side ground resistor R51 and the left end of the positive side coupling capacitor C52; the right end of the negative side isolation capacitor C53 is connected to the lower end of the negative side ground resistor R52 and the left end of the negative side coupling capacitor C54; the right end of the positive terminal coupling capacitor C52 is connected to the upper end of the positive terminal common mode resistor R53 and serves as the output terminal of the positive terminal input signal Vip; the right end of the negative end coupling capacitor C54 is connected to the lower end of the negative end common mode resistor R54 and serves as the output end of a negative end input signal Vin; the lower end of the positive end common mode resistor R53 is connected with the upper end of the negative end common mode resistor R54 and is simultaneously connected to a common mode output end Vicm of the receiving common mode generating circuit; the receiving common mode generating circuit dynamically tracks and adjusts the size of a common mode output end Vicm according to the change of an input common mode Vcm, and the influence of an input common mode is reduced.

Specifically, the receiving common mode generating circuit includes: an NMOS transistor M60, an NMOS transistor M61, a PMOS transistor M62, an NMOS transistor M63, a PMOS transistor M64, a PMOS transistor M65, an NMOS transistor M66, an NMOS transistor M67, a PMOS transistor M68, an NMOS transistor M69, a PMOS transistor M610, an NMOS transistor M611, a PMOS transistor M612, an NMOS transistor M613, an NMOS transistor M614, a PMOS transistor M615, a resistor R61 and a first Schmidt trigger;

the grid electrode of the NMOS tube M60 is connected to an input common mode voltage Vcm; the drain electrode of the NMOS tube M60 is connected to the drain electrode and the gate electrode of the PMOS tube M62 and the gate electrode of the NMOS tube M63; the grid electrode of the NMOS tube M61 is connected to an input common mode control signal Vctrl; the drain electrode of the NMOS tube M61 is connected with the drain electrode of the NMOS tube M63 and is connected to the input end of the first Schmitt trigger; the output end of the first Schmitt trigger is simultaneously connected to the grid electrode of the PMOS tube M610, the grid electrode of the NMOS tube M611, the grid electrode of the PMOS tube M612 and the grid electrode of the NMOS tube M613; the drain electrode of the PMOS tube M610 is connected with the drain electrode of the NMOS tube M611 and is also connected to the grid electrode of the NMOS tube M614; the drain of the PMOS tube M612 is connected with the drain of the NMOS tube M613, and is also connected to the gate of the PMOS tube M615; the source electrode of the NMOS tube M614 is connected with the source electrode of the PMOS tube M615 and is also used as an output port of the common mode output end Vicm; the drain electrode of the NMOS tube M614 is connected to a high input common mode level Vcmh, and the drain electrode of the PMOS tube M615 is connected to a low input common mode level Vcml; the source of the NMOS transistor M613 is connected to the upper end of the resistor R61; the source electrode of the NMOS tube M60, the source electrode of the NMOS tube M61, the source electrode of the NMOS tube M611 and the lower end of the resistor R61 are simultaneously connected to a receiving end ground voltage Vgnd 2; the source of the PMOS transistor M62, the source of the NMOS transistor M63 and the source of the PMOS transistor M610 are simultaneously connected to the receiving terminal power voltage VDD.

Specifically, the high-sensitivity common-mode adjustable amplifying circuit is a front-stage and a rear-stage fully differential amplifying circuit, and comprises a front-stage common-mode adjustable amplifying circuit and a rear-stage differential amplifying circuit which are connected with each other; the positive input end of the preceding common mode adjustable amplifying circuit is the positive input end of the high-sensitivity common mode adjustable amplifying circuit, and the negative input end of the preceding common mode adjustable amplifying circuit is the negative input end of the high-sensitivity common mode adjustable amplifying circuit; a positive output end VoNp of the differential amplifying circuit is a positive output end of the high-sensitivity common-mode adjustable amplifying circuit, and a negative output end VoNn of the differential amplifying circuit is a negative output end of the high-sensitivity common-mode adjustable amplifying circuit;

the left side of the front-stage common mode adjustable amplifying circuit comprises a PMOS tube M81 and an NMOS tube M83 which are connected in series through a drain electrode; the source electrode of the PMOS tube M81 is connected with a power supply VDD, a capacitor C81 is connected between the grid electrode and the source electrode of the PMOS tube M81, the grid electrode of the PMOS tube M81 is also connected to the upper end of a bias resistor R81, and the drain electrode of the PMOS tube M81 is also connected to the lower end of the bias resistor R82; the lower end of the bias resistor R81 is connected with the upper end of the bias resistor R82 and is also used as a first signal input end of the differential amplification circuit; the drain of the NMOS transistor M83 is connected with the drain of a PMOS transistor M81 and is also connected with the third signal input end of the differential amplifying circuit; the grid electrode of the NMOS tube M83 is connected with the positive input end of the preceding-stage common-mode adjustable amplification circuit and receives a positive-end output signal VoXp; the right side of the front-stage common mode adjustable amplifying circuit comprises a PMOS tube M82 and an NMOS tube M84 which are connected in series through a drain electrode; the source electrode of the PMOS tube M82 is connected with a power supply VDD, a capacitor C82 is connected between the grid electrode and the source electrode of the PMOS tube M82, the grid electrode of the PMOS tube M82 is also connected to the upper end of a bias resistor R83, and the drain electrode of the PMOS tube M82 is also connected to the lower end of the bias resistor R84; the lower end of the bias resistor R83 is connected with the upper end of the bias resistor R84 and is also used as a second signal input end of the differential amplifying circuit; the drain of the NMOS transistor M84 is connected with the drain of a PMOS transistor M82 and is also connected with the fourth signal input end of the differential amplifying circuit; the grid electrode of the NMOS tube M84 is connected with the negative input end of the preceding-stage common-mode adjustable amplifying circuit and receives a negative end output signal VoXn; the PMOS tube M81 and the PMOS tube M82 on the left side and the right side of the preceding stage common mode adjustable amplifying circuit are connected in parallel, and the NMOS tube M83 and the NMOS tube M84 are connected in parallel; the source electrodes of the NMOS transistor M83 and the NMOS transistor M84 are connected with the drain electrodes of the NMOS transistor M85, the NMOS transistor M86 and the NMOS transistor M87 which are grounded; the grid electrode of the ground NMOS tube M85 is connected with a bias voltage Vb1, and provides bias current required by normal operation of the amplifier; the gates of the NMOS transistor M86 and the NMOS transistor M87 are respectively connected to common mode adjusting signals CN1 and CN 2;

the differential amplifier circuit includes: PMOS transistor M88, PMOS transistor M89, PMOS transistor M812, PMOS transistor M813, NMOS transistor M810, NMOS transistor M811, NMOS transistor M814, NMOS transistor M815 and resistor 85; the grid of the PMOS tube M88 is a first signal input end of the differential amplification circuit, the grid of the PMOS tube M89 is a second signal input end of the differential amplification circuit, the PMOS tube M812 is a third signal input end of the differential amplification circuit, and the PMOS tube M813 is a fourth signal input end of the differential amplification circuit; the drain electrode of the PMOS tube M88 is connected with the drain electrode of the PMOS tube M89, is connected with the drain electrode of the NMOS tube M810 and is used as a positive output end VoNp of the differential amplifying circuit; the drain electrode of the PMOS pipe M812 is connected with the drain electrode of the PMOS pipe M813 and is connected to the upper end of the resistor R85; the lower end of the resistor R85 is connected with the drain electrode of the NMOS tube M814 and is used as the negative output end VoNn of the differential amplifying circuit; the NMOS transistor M810 and the NMOS transistor M811 form a cascode current source structure, the NMOS transistor M814 and the NMOS transistor M815 form the cascode current source structure, the gates of the NMOS transistor M810 and the NMOS transistor M814 are connected with the same bias voltage Vb81, and the gates of the NMOS transistor M811 and the NMOS transistor M815 are connected with the same bias voltage Vb 82.

Specifically, the output shaping circuit comprises a three-level comparator, a buffer with an RC filtering function, a second schmitt trigger and an output inverter which are connected in sequence, wherein an output end of the output inverter is final output data, namely receiving output data Dout; the connection relationship of the internal circuit of the buffer with the RC filtering function is as follows: the grid electrode of the PMOS tube M41 and the grid electrode of the NMOS tube M42 are simultaneously connected to the comparison output voltage of the three-stage comparator, the drain electrode of the PMOS tube M41 and the drain electrode of the NMOS tube M42 are simultaneously connected to the grid electrode of the PMOS tube M43 and the grid electrode of the NMOS tube M44, the drain electrode of the PMOS tube M43 is connected to the upper end of a resistor R41, the lower end of the resistor R41 is connected to the upper end of a resistor R42, the upper end of a capacitor C41 and the input end of a second Schmidt trigger, the lower end of the resistor R42 is connected to the drain electrode of the NMOS tube M44, the source electrode of the PMOS tube M41 and the source electrode of the PMOS tube M43 are simultaneously connected to a power supply voltage VCC, and the source electrode of the NMOS tube M42.

Specifically, the common-mode adaptive adjustment circuit includes: the common mode detection circuit, the common mode detection signal transmission circuit, the common mode adjustment signal generation circuit and the common mode adjustment signal selection circuit; the common mode detection circuit is used for detecting power supply and substrate noise, and changing the size of a common mode detection signal Vcm _ det when the noise is larger than a certain threshold value, the common mode detection signal Vcm _ det is connected to the common mode detection signal transmission circuit, common mode selection switch control signals N11, N12, N21, N22, …, NX1, NX2, NN1 and NN2 are generated through the common mode detection signal transmission circuit and output to the common mode adjustment signal selection circuit; the common mode adjusting signal selection circuit generates and adjusts the size of common mode adjusting signals C11, C12, C21, C22, …, CX1, CX2 and CN1, CN2 according to the common mode selecting switch control signal and outputs the common mode adjusting signals; the adjusting common-mode signal generating circuit is used for generating various common-mode bias signals required by the common-mode adjusting signal selecting circuit and outputting the common-mode bias signals to the common-mode adjusting signal selecting circuit.

Specifically, the common mode detection circuit includes: a PMOS transistor M111, a PMOS transistor M112 and an NMOS transistor M113; the grid electrode and the drain electrode of the PMOS tube M111 are connected, and the grid electrode is connected with the drain electrode of the PMOS tube M112 and the grid electrode of the NMOS tube M113; the grid electrode of the PMOS tube M112 is connected with the drain electrode of the NMOS tube M113 and is used as an output node of a common mode detection signal Vcm _ det; the source of the PMOS transistor M111 and the source of the PMOS transistor M112 are connected to a power supply voltage VDD, and the source of the NMOS transistor M113 is connected to a receiving terminal ground voltage Vgnd 2.

Specifically, the sending-end low-voltage generating circuit includes: the device comprises a starting circuit, an analog circuit module low-voltage power supply circuit, a digital circuit module low-voltage power supply circuit, a self-biased band gap reference voltage generating circuit, a bias signal generating circuit, a reference voltage generating circuit and n same reference voltage buffer output circuits; n is a natural number greater than or equal to 2;

the starting circuit, the analog circuit module low-voltage power supply circuit and the digital circuit module low-voltage power supply circuit adopt a sending end input power supply voltage VCCbus, the analog circuit module low-voltage power supply circuit generates a low-voltage analog power supply AVCC according to the sending end input power supply voltage VCCbus, and the digital circuit module low-voltage power supply circuit generates a low-voltage digital power supply DVCC according to the sending end input power supply voltage VCCbus; the self-biased band gap reference voltage generating circuit, the bias signal generating circuit, the reference voltage generating circuit and the n same reference voltage buffer output circuits adopt a low-voltage analog power supply AVCC; the bias signal generating circuit generates all bias signals required by the reference voltage generating circuit and the n same reference voltage buffer output circuits; the voltage of the low-voltage analog power supply AVCC and the voltage of the low-voltage digital power supply DVCC are equal and equal to the power supply voltage VCC of a sending end;

the self-biased band-gap reference voltage generation circuit outputs a band-gap reference voltage Vref and is connected to the input end of the reference voltage generation circuit, and the reference voltage generation circuit generates n reference voltages according to the band-gap reference voltage Vref, specifically, first reference voltages V with unequal magnitudes_R1A second reference voltage V_R2… …, nth reference voltage V_Rn(ii) a The n reference voltages are respectively input into n reference voltage buffer output circuits to correspondingly obtain n output reference voltages with larger driving capability, namely a first reference voltage V_R1Entering a first reference voltage buffer output circuit to obtain a first output reference voltage V_RO1Second reference voltage V_R2Entering a second reference voltage buffer output circuit to obtain a second output reference voltage V_RO2… …, nth reference voltage V_RnEntering an nth reference voltage buffer output circuit to obtain an nth output reference voltage V_ROn。

The invention has the advantages that: on one hand, the provided ultrahigh voltage insulation isolation SiC MOSFET gate drive circuit adopts a high voltage insulation isolation technology to realize ultrahigh voltage-resistant insulation capacitance; on the other hand, the magnitude of the ground potential common mode transient noise can be automatically detected, and the error generated by the common mode transient noise is dynamically compensated when the noise exceeds a threshold value.

Drawings

Fig. 1 is a schematic diagram of a capacitive isolation driving circuit architecture.

Fig. 2 is a structure diagram of the gate driving circuit of the ultra-high voltage insulation isolation SiC MOSFET of the present invention.

Fig. 3 is a structural diagram of a modulation transmission circuit of the present invention.

FIG. 4 is a circuit diagram of a refresh module according to the present invention.

FIG. 5 is a circuit diagram of an encoding module according to the present invention.

Fig. 6 is a structural diagram of a high common mode transient suppression differential signal receiving circuit according to the present invention.

Fig. 7 shows an embodiment of the differential input receiving circuit of the present invention.

Fig. 8 is a diagram of an embodiment of a receiving common mode generating circuit according to the present invention.

Fig. 9 shows an embodiment of a common mode adjustable amplifier circuit according to the present invention.

Fig. 10 shows an embodiment of the high-sensitivity common-mode tunable amplifier circuit according to the present invention.

Fig. 11 is a diagram of an embodiment of an output shaping circuit according to the present invention.

Fig. 12 is a diagram of an embodiment of a common mode adaptive adjustment circuit according to the invention.

FIG. 13 is a diagram of an embodiment of a common mode detection circuit according to the invention.

Fig. 14 is a waveform diagram of the circuit shown in fig. 13.

FIG. 15 is a cross-sectional view of a semiconductor structure of an embodiment of a high voltage isolation capacitor of the present invention.

Fig. 16 shows an embodiment of the low voltage generation circuit of the present invention.

Fig. 17 is an embodiment of the analog circuit module low voltage power supply circuit of the present invention.

FIG. 18 is a diagram of an embodiment of the reference voltage generating circuit in FIG. 16.

FIG. 19 is an embodiment of the single reference voltage buffer output circuit of FIG. 16.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples.

As shown in fig. 2, the gate driving circuit of the ultra-high voltage insulated isolated SiC MOSFET of the present invention includes an input receiving circuit 1, a digital control circuit 2, a modulation transmitting circuit 5, an isolation circuit 9, a high common mode transient suppression differential signal receiving circuit 6, an output driving circuit 7, a transmitting end low voltage generating circuit 3, a receiving end low voltage generating circuit 8, and a chip state monitoring circuit 4. The input receiving circuit 1, the digital control circuit 2, the modulation transmitting circuit 5, the transmitting end low voltage generating circuit 3 and the chip state monitoring circuit 4 form a transmitting end circuit of the driving circuit, and the high common mode transient suppression differential signal receiving circuit 6, the output driving circuit 7 and the receiving end low voltage generating circuit 8 form a receiving end circuit of the driving circuit. The ground potentials of all circuits inside the transmitting-end circuit of the driving circuit are connected to a transmitting-end ground voltage Vgnd1, and the ground potentials of all circuits inside the receiving-end circuit of the driving circuit are connected to a receiving-end ground voltage Vgnd 2. The isolation circuit 10 includes a positive terminal sending capacitor Ctp, a negative terminal sending capacitor Ctn, a positive terminal receiving capacitor Crp, and a negative terminal receiving capacitor Crn.

The input receiving circuit 1 receives external low-level logic input data DI, and the DI is converted into input data Din with a high level VCC through processing; the digital control circuit 2 processes the input data Din according to the states of the undervoltage protection signal UVLO, the over-temperature protection signal OTP and the over-current protection signal OCP provided by the chip state monitoring circuit 4 to obtain differential data DxP and DxN; the differential data dxP and dxN enter a modulation transmitting circuit 5 to obtain differential transmitting data TxP and TxN; the differential sending data TxP and TxN are respectively connected to the left end of a positive side sending capacitor Ctp and the left end of a negative side sending capacitor Ctn, the right end of the positive side sending capacitor Ctp and the right end of the negative side sending capacitor Ctn are respectively connected to the left end of a positive side receiving capacitor Crp and the left end of a negative side receiving capacitor Crn, and the right end of the positive side receiving capacitor Crp and the right end of the negative side receiving capacitor Crn generate differential receiving data RxP and RxN; the differential receiving data RxP and RxN enter the high common mode transient suppression differential signal receiving circuit 6, and receiving output data Dout is obtained after processing; the received output data Dout finally enters the output drive circuit 7, which generates an output drive signal DG with a large drive current.

The sending end low voltage generating circuit 3 adopts sending end input power voltage VCCbus to generate sending end power voltage VCC and various reference voltages and bias voltages required by each component circuit in the sending end circuit of the driving circuit. The receiving-end low-voltage generating circuit 8 generates a receiving-end power supply voltage VDD and various reference voltages and bias voltages required for driving the constituent circuits inside the receiving-end circuit by using a receiving-end input power supply voltage VDDbus. The sending end low voltage generating circuit 3 and the receiving end low voltage generating circuit 8 are realized by the same low voltage generating circuit. The positive end sending capacitor Ctp, the negative end sending capacitor Ctn, the positive end receiving capacitor Crp and the negative end receiving capacitor Crn are equal in size and are all ultrahigh voltage-resistant isolation capacitors.

In the circuit shown in fig. 2, the chip state monitoring circuit 4 can be realized by adopting conventional temperature protection, under-voltage protection and over-current protection circuits, and reference voltages required by various protection circuits are generated by the transmitting-end low-voltage generating circuit 3; the chip state monitoring circuit 4 is used for providing an undervoltage protection signal UVLO, an over-temperature protection signal OTP and an over-current protection signal OCP, and the digital control circuit 2 is used for judging whether the chip state is correct or not. When the circuit is subjected to overcurrent (OCP is effective), overtemperature (OTP is effective) or power supply voltage undervoltage (UVLO is effective), the digital control circuit 2 blocks two paths of output DxP and DxN; when the overcurrent and overtemperature alarm is relieved and the power supply recovers to normal working voltage, the digital control circuit 2 indicates that the circuit works normally. The output driver circuit 7 in the circuit shown in fig. 2 functions to convert the received output data Dout without driving capability into a large current driving signal DG, and the simplest implementation is a well-known inverter chain driver circuit.

In the circuit shown in fig. 2, the input receiving circuit 1 is generally composed of an input ESD protection circuit and a level discrimination circuit connected in this order. The input receiving circuit 1 not only needs to complete the transmission of signals, but also needs to complete the ESD protection of the internal circuit of the chip, so as to prevent the circuit from being damaged due to the impact of ESD to the internal circuit. The level discrimination circuit is used to discriminate whether the external input level is logic "0" or "1". Since there is a large interference from external signals, the level decision circuit must have sufficient interference noise tolerance, and the specific circuit implementation usually includes 2 types, one is a Schmitt trigger, and the other is a hysteresis comparator. According to different speeds of driving objects and input logic signals of the driving chip, the implementation circuits of the Schmitt trigger and the hysteresis comparator are greatly different. The logic signal output by the level discrimination circuit is a Din signal.

The digital control circuit 2 is used for integrating the chip state monitoring signals, judging whether the circuit is normal or not, and switching off data output when the chip is abnormal. The digital control circuit 2 is composed of a combinational logic gate, when the circuit is subjected to overcurrent (OCP is effective), overtemperature (OTP is effective) or power supply voltage undervoltage (UVLO is effective), the error logic circuit outputs a low level signal to indicate that the circuit is abnormal, and blocks two paths of output DxP and DxN; when the over-current and over-temperature alarm is released and the power supply recovers to normal working voltage, the error logic circuit immediately outputs a high-level signal to indicate that the circuit works normally.

Fig. 3 is an implementation structure of a modulation transmitting circuit, and a specifically adopted modulation scheme is pulse counting modulation, which uses a method of describing a rising edge of an input signal by double pulses and describing a falling edge of the input signal by single pulses. The input of the whole system is a signal to be isolated, and the output is the signal after isolation and shaping. The modulation transmitting circuit 5 mainly includes a filter module 503 for processing rising and falling edges of an input signal, a refresh module 501 and an encoding module 502. Specifically, the filter module 503 is mainly used for processing an interference signal such as a spur on the input signal so as not to affect the generation of the pulse by the encoding module 502; the refresh module 501 feeds a refresh signal to the encoding module 502 at a fixed time according to the timing of the internal timing circuit, so as to avoid the influence of an external interference signal on the pulse under the condition of a large signal period. The encoding module 502 is used for generating a double-pulse signal and a single-pulse signal corresponding to a rising edge and a falling edge. In fig. 3, DxP is input data, R1 and R2 are high-frequency refresh signals generated by the refresh module 501, and the output is a modulated pulse signal TxP. The modulation transmission circuit 5 of the present invention employs 2 sets of modulation transmission circuits shown in fig. 3.

The filter module 503 in the circuit shown in fig. 3 is used for removing glitches and shaping signals, and may be implemented by using a combination of a schmitt trigger and an SR latch, where an input signal is connected to the schmitt trigger, and then reset and shaped by the SR latch, so as to recover the original input signal from which an external interference signal is removed. Fig. 4 shows an implementation structure of the refresh module 501 according to the present invention. The input signal Fpre enters a simple delay circuit consisting of an inverter and a capacitor, the Fpre signal is delayed and then is subjected to XOR with an original signal to obtain a signal PF, and the PF is a pulse corresponding to a jump edge of the Fpre signal. O and O _ L are signals whose high and low levels are completely opposite. WatchDog is a timing circuit that can be reset via inputs Fpre and CLR _ W. After the chip is powered on, the internal current of the WatchDog charges the capacitor, and finally the output W _ D is at a high level, so that state locking is formed, and the locking state is kept unchanged unless Fpre or CLR _ W is reset. The signals W _ D to CLR _ W pass through the timing circuit WatchDog to form an oscillation signal OSC, the period of the oscillation is the timing time of the WatchDog plus the delay time of O and O _ L, and the delay time of O and O _ L is negligible relative to the timing time of the WatchDog, so the period of the oscillation is the timing time of the WatchDog.

FIG. 5 is a circuit diagram of an encoding module 502 according to the present invention. The modulation scheme adopted by the circuit is pulse counting modulation, and the rising edge and the falling edge of the input signal are separated by using a method of describing the rising edge of the input signal by double pulses and describing the falling edge of the input signal by single pulses so as to generate corresponding pulse driving signals. The input DxPin of the coding module 502 is filtered input data and output is a modulated pulse signal TxP. The refresh signals R1 and R2 correspond to the refresh command signals of a falling edge single pulse and a rising edge double pulse, respectively, and the circuit operates normally when the signal is high, and performs a refresh operation to refresh the circuit when the signal is low. Besides the logic gate, the circuit also has a delay module TD, which can be composed of an inverter, a capacitor and a Schmitt trigger.

As shown in fig. 6, the structure of the high common mode transient suppression differential signal receiving circuit 6 of the present invention includes: the circuit comprises a differential input receiving circuit 1, an X-stage tandem common mode adjustable amplifying circuit 602(CM 1-CMX), a high-sensitivity common mode adjustable amplifying circuit 603(CMN), an output shaping circuit 604 and a common mode adaptive adjusting circuit 605. The differential input receiving circuit 1 first receives the differential signals (positive terminal receiving signal RxP and negative terminal receiving signal RxN) coupled from the transmitting terminal circuit shown in fig. 2 through the isolation circuit 10, and obtains a positive terminal input signal Vip and a negative terminal input signal Vin through filtering processing; vip and Vin enter a first-pole common-mode adjustable amplifying circuit CM1 of an X-stage common-mode adjustable amplifying circuit 602 cascaded in front and behind, and finally a positive-end output signal VoXp and a negative-end output signal VoXn of the X-stage common-mode adjustable amplifying circuit are obtained; VoXp and VoXn are respectively connected to the positive input terminal and the negative input terminal of the high-sensitivity common-mode adjustable amplifier circuit 603(CMN), so as to obtain differential output signals (a positive-side output signal VoNp and a negative-side output signal VoNn) of the high-sensitivity common-mode adjustable amplifier circuit 603; the output shaping circuit 604 processes the VoNp and VoNn to obtain the final data output Dout. The common mode adaptive adjusting circuit 605 adaptively generates common mode adjusting signals C11, C12, C21, C22, …, CX1, CX2, CN1 and CN2 for each stage of amplifying circuit according to the change of power supply and ground voltage signals, and common mode adjusting signals C11 and C12 generated by the common mode adaptive adjusting circuit 605 are respectively connected to a common mode adjusting signal input end of the first stage of common mode adjustable amplifying circuit CM 1; the common mode adjusting signal C21 and the common mode adjusting signal C22 are respectively connected to a common mode adjusting signal input end of the second-stage common mode adjustable amplifying circuit CM 2; … … and so on, the common mode adjusting signal CX1 and the common mode adjusting signal CX2 are respectively connected to the common mode adjusting signal input terminal of the X-th common mode adjustable amplifying circuit CMX; the common mode adjustment signal CN1 and the common mode adjustment signal CN2 are respectively connected to the common mode adjustment signal input terminal of the high-sensitivity common mode adjustable amplification circuit 603 (CMN). Wherein X is a positive integer greater than 1, and N is a positive integer greater than X.

In fig. 6, the internal of the common-mode adaptive adjusting circuit 605 automatically detects the magnitude of the transient common-mode noise caused by the fluctuation of the power supply voltage VDD of the receiving circuit and the ground potential Vgnd2, and when the transient common-mode noise exceeds a certain threshold, adjusts the values of the common-mode adjusting signals C11, C12, C21, C22, …, CX1, CX2, CN1, and CN2 and correspondingly outputs the values to the common-mode adjustable amplifying circuits CM1 to CMX and the high-sensitivity common-mode adjustable amplifying circuit 603(CMN) cascaded in the X-stage front-back, so as to adjust the common-mode levels of the common-mode adjustable amplifying circuits CM1 to CMX and the high-sensitivity common-mode adjustable amplifying circuit 3 cascaded in the X-stage front-back, and compensate the influence. Besides the common mode adaptive adjustment, the invention also adopts a high-reliability output shaping circuit 604, and adopts RC low-pass filtering and Schmitt trigger combined filtering to filter the influence of high-frequency noise, and finally obtains the data output Dout which is not influenced by transient common mode noise.

Fig. 7 shows an implementation of the differential input receiving circuit 601 of the present invention, which is composed of a positive side isolation capacitor C51, a positive side ground resistor R51, a positive side coupling capacitor C52, a positive side common mode resistor R53, a negative side isolation capacitor C53, a negative side ground resistor R52, a negative side coupling capacitor C54, a negative side common mode resistor R54, and a receiving common mode generating circuit 6011. The left end of the positive side isolation capacitor C51 and the left end of the negative side isolation capacitor C53 are connected to the positive side receive signal RxP and the negative side receive signal RxN, respectively; the right end of the positive side isolation capacitor C51 is connected to the lower end of the positive side ground resistor R51 and the left end of the positive side coupling capacitor C52; the right end of the negative side isolation capacitor C53 is connected to the lower end of the negative side ground resistor R52 and the left end of the negative side coupling capacitor C54; the right end of the positive terminal coupling capacitor C52 is connected to the upper end of the positive terminal common mode resistor R53 and serves as the output terminal of the positive terminal input signal Vip; the right end of the negative end coupling capacitor C54 is connected to the lower end of the negative end common mode resistor R54 and serves as the output end of a negative end input signal Vin; the lower end of the positive common-mode resistor R53 is connected to the upper end of the negative common-mode resistor R54, and is also connected to the common-mode output terminal Vicm of the receiving common-mode generating circuit 6011.

In the circuit shown in FIG. 7, the positive side isolation capacitor C51 and the negative side isolation capacitor C53 are high-voltage capacitors, and the size of the capacitors is usually dozens of fp; the positive side coupling capacitor C52 and the negative side coupling capacitor C54 are low voltage capacitors, and the capacitance values thereof are relatively small. The positive side receiving signal RxP and the negative side receiving signal RxN are input to output, and are filtered by 2 stages of DC blocking coupling to obtain a positive side input signal Vip and a negative side input signal Vin. The common mode level of the positive side input signal Vip and the negative side input signal Vin is provided by the receive common mode generation circuit 6011.

Fig. 8 is an implementation of the receiving common mode generating circuit 6011 according to the present invention. The circuit is composed of an NMOS tube M60, an NMOS tube M61, a PMOS tube M62, an NMOS tube M63, a PMOS tube M64, a PMOS tube M65, an NMOS tube M66, an NMOS tube M67, a PMOS tube M68, an NMOS tube M69, a PMOS tube M610, an NMOS tube M611, a PMOS tube M612, an NMOS tube M613, an NMOS tube M614, a PMOS tube M615 and a resistor R61; the schmitt trigger 600 is composed of a PMOS transistor M64, a PMOS transistor M65, an NMOS transistor M66, an NMOS transistor M67, a PMOS transistor M68 and an NMOS transistor M69.

The grid electrode of the NMOS tube M60 is connected to an input common mode voltage Vcm; the drain electrode of the NMOS tube M60 is connected to the drain electrode and the gate electrode of the PMOS tube M62 and the gate electrode of the NMOS tube M63; the grid electrode of the NMOS tube M61 is connected to an input common mode control signal Vctrl; the drain electrode of the NMOS tube M61 is connected with the drain electrode of the NMOS tube M63 and is connected to the input end of the Schmitt trigger 600; the output end of the Schmitt trigger 600 is simultaneously connected to the gates of a PMOS transistor M610, an NMOS transistor M611, a PMOS transistor M612 and an NMOS transistor M613; the drain electrode of the PMOS tube M610 is connected with the drain electrode of the NMOS tube M611 and is also connected to the grid electrode of the NMOS tube M614; the drain of the PMOS tube M612 is connected with the drain of the NMOS tube M613, and is also connected to the gate of the PMOS tube M615; the source electrode of the NMOS tube M614 is connected with the source electrode of the PMOS tube M615 and is also used as an output port of the common mode output end Vicm; the drain electrode of the NMOS tube M614 is connected to a high input common mode level Vcmh, and the drain electrode of the PMOS tube M615 is connected to a low input common mode level Vcml; the source of the NMOS transistor M613 is connected to the upper end of the resistor R61; the source electrode of the NMOS tube M60, the source electrode of the NMOS tube M61, the source electrode of the NMOS tube M611 and the lower end of the resistor R61 are connected to a ground voltage Vgnd 2; the source electrode of the PMOS transistor M62, the source electrode of the NMOS transistor M63, the source electrode of the PMOS transistor M64 and the source electrode of the PMOS transistor M610 are simultaneously connected to the receiving end power supply voltage VDD. The ground terminals of this circuit are each connected to the receive circuit ground voltage Vgnd 2.

The function of the circuit shown in fig. 8 is to dynamically track and adjust the size of the common-mode output end Vicm according to the change of the input common-mode Vcm, so as to reduce the influence of the input common-mode. If the input common mode Vcm is reduced, the input end of the schmitt trigger 600 will be synchronously reduced, and if the fluctuation exceeds the threshold of the schmitt trigger 600, the output of the schmitt trigger 600 will become high level, the PMOS transistor M615 will be turned on, and the common mode output end Vicm will output low input common mode level Vcml to match with the input common mode; assuming that the input common mode Vcm increases and exceeds the threshold of the schmitt trigger 600, the NMOS transistor M614 is turned on, and the common mode output terminal Vicm will output a high input common mode level Vcmh. It can be seen that the circuit of fig. 8 can achieve dynamic compensation of input common mode variations for different input common mode fluctuations. In the circuit shown in fig. 8, in order to better realize the output of the common-mode signal at the common-mode output end Vicm, an NMOS transistor is used for transmitting a high input common-mode level Vcmh, and a PMOS transistor is used for transmitting a low input common-mode level Vcml.

Fig. 9 shows an implementation of a cascade unit of the common mode adjustable amplifier circuit according to the present invention. The circuit is a fully differential single-stage amplifying circuit, and the left side of the circuit comprises a PMOS tube M71 and an NMOS tube M73 which are connected in series through a drain electrode; the source electrode of the PMOS tube M71 is connected with a power supply VDD, a capacitor C71 is connected between the grid electrode and the source electrode of the PMOS tube M71, and a bias resistor R71 is connected between the grid electrode and the drain electrode of the PMOS tube; the drain output negative terminal output signal Vo1n of the NMOS transistor M73 is connected to the negative input terminal of the next cascade unit (the second cascade unit outputs the negative terminal output signal Vo2n to the next cascade unit, and so on), and the gate of the NMOS transistor M73 is connected to the positive input terminal Vip of the common mode adjustable amplifier circuit 602; the right side of the circuit comprises: a PMOS transistor M72 and an NMOS transistor M74 which are connected in series through drains; the source electrode of the PMOS tube M72 is connected with a power supply VDD, a capacitor C72 is connected between the grid electrode and the source electrode of the PMOS tube M72, and a bias resistor R72 is connected between the grid electrode and the drain electrode of the PMOS tube M72; the drain of the NMOS transistor M74 outputs a positive end output signal Vo1p to the positive input terminal of the next cascade unit (the second cascade unit outputs a positive end output signal Vo2p to the next cascade unit, and so on), and the gate of the NMOS transistor M74 is connected to the negative input terminal Vin of the common mode adjustable amplifier circuit 602; the sources of the PMOS tube M71 and the PMOS tube M72 at the two sides of the amplifying circuit are connected in parallel, and the sources of the NMOS tube M73 and the NMOS tube M74 are connected in parallel; the source electrodes of the NMOS transistor M73 and the NMOS transistor M74 are connected with the drain electrodes of the NMOS transistor M75, the NMOS transistor M76 and the NMOS transistor M77 which are grounded; the grid electrode of the ground NMOS tube M75 is connected with a bias voltage Vb1, and provides bias current required by normal operation of the amplifier; the gates of the NMOS transistor M76 and the NMOS transistor M77 are connected to common mode adjustment signals C11 and C12, respectively.

As can be seen from the circuit shown in fig. 9, by changing the magnitudes of the common mode adjustment signals C11 and C12, the bias currents flowing through the NMOS transistor M73 and the NMOS transistor M74 change, and the output voltages of the negative side output signal Vo1n and the positive side output signal Vo1p of the cascade unit change correspondingly and simultaneously, so as to adjust the output common mode voltage. The receiving end circuit of the invention adopts a plurality of stages of common mode adjustable amplifying circuits which are the same as those shown in figure 9 and are cascaded in front and back, and an X-th stage common mode adjustable amplifying circuit CMX outputs a positive end output signal VoXp and a negative end output signal VoXn, thereby finally realizing the dynamic compensation of common mode noise.

Fig. 10 shows an implementation of the high-sensitivity common-mode tunable amplifier circuit 603 according to the present invention. The circuit is a front-stage and a rear-stage fully differential amplifying circuits, the front-stage common mode adjustable amplifying circuit adopts an amplifying circuit structure similar to that of fig. 9, and the rear-stage amplifying circuit is a differential amplifying circuit (DDA). The positive input end of the preceding common mode adjustable amplifier circuit is the positive input end of the high-sensitivity common mode adjustable amplifier circuit 603, and the negative input end of the preceding common mode adjustable amplifier circuit is the negative input end of the high-sensitivity common mode adjustable amplifier circuit 603; the positive output terminal VoNp of the differential amplifier circuit is the positive output terminal of the high-sensitivity common mode adjustable amplifier circuit 603, and the negative output terminal VoNn of the differential amplifier circuit is the negative output terminal of the high-sensitivity common mode adjustable amplifier circuit 603.

The left side of the front-stage common mode adjustable amplifying circuit comprises a PMOS tube M81 and an NMOS tube M83 which are connected in series through a drain electrode; the source electrode of the PMOS tube M81 is connected with a power supply VDD, a capacitor C81 is connected between the grid electrode and the source electrode of the PMOS tube M81, the grid electrode of the PMOS tube M81 is also connected to the upper end of a bias resistor R81, and the drain electrode of the PMOS tube M81 is also connected to the lower end of the bias resistor R82; the lower end of the bias resistor R81 is connected with the upper end of the bias resistor R82 and is also used as a first signal input end of the differential amplification circuit; the drain of the NMOS transistor M83 is connected with the drain of a PMOS transistor M81 and is also connected with the third signal input end of the differential amplifying circuit; the grid electrode of the NMOS tube M83 is connected with the positive input end VoXp of the preceding-stage common-mode adjustable amplifying circuit; the right side of the circuit comprises a PMOS tube M82 and an NMOS tube M84 which are connected in series through a drain electrode; the source electrode of the PMOS tube M82 is connected with a power supply VDD, a capacitor C82 is connected between the grid electrode and the source electrode of the PMOS tube M82, the grid electrode of the PMOS tube M82 is also connected to the upper end of a bias resistor R83, and the drain electrode of the PMOS tube M82 is also connected to the lower end of the bias resistor R84; the lower end of the bias resistor R83 is connected with the upper end of the bias resistor R84 and is also used as a second signal input end of the differential amplifying circuit; the drain of the NMOS transistor M84 is connected with the drain of a PMOS transistor M82 and is also connected with the fourth signal input end of the differential amplifying circuit; the grid electrode of the NMOS tube M84 is connected with the negative input end VoXn of the preceding-stage common-mode adjustable amplifying circuit; the sources of the PMOS tube M81 and the PMOS tube M82 at the two sides of the amplifying circuit are connected in parallel, and the sources of the NMOS tube M83 and the NMOS tube M84 are connected in parallel; the source electrodes of the NMOS transistor M83 and the NMOS transistor M84 are connected with the drain electrodes of the NMOS transistor M85, the NMOS transistor M86 and the NMOS transistor M87 which are grounded; the grid electrode of the ground NMOS tube M85 is connected with a bias voltage Vb1, and provides bias current required by normal operation of the amplifier; the gates of the NMOS transistor M86 and the NMOS transistor M87 are connected to common mode adjustment signals CN1 and CN2, respectively.

Fig. 11 shows an implementation manner of the output shaping circuit 604 of the present invention, which includes a PMOS transistor M401, a PMOS transistor M402, a PMOS transistor M403, a PMOS transistor M404, a PMOS transistor M405, a PMOS transistor M406, a PMOS transistor M409, an NMOS transistor M407, an NMOS transistor M408, an NMOS transistor M4010, a resistor R401, a resistor R402, a PMOS transistor M41, a PMOS transistor M43, a PMOS transistor M45, a PMOS transistor M46, a PMOS transistor M49, a PMOS transistor M411, an NMOS transistor M42, an NMOS transistor M44, an NMOS transistor M47, an NMOS transistor M48, an NMOS transistor M410, an NMOS transistor M412, a resistor R41, a resistor R42, and a capacitor C41.

The PMOS transistor M401, the PMOS transistor M402, the PMOS transistor M403, the PMOS transistor M404, the PMOS transistor M405, the PMOS transistor M406, the PMOS transistor M409, the NMOS transistor M407, the NMOS transistor M408, the NMOS transistor M4010, the resistor R401 and the resistor R402 form a three-stage comparator; the PMOS tube M41, the PMOS tube M43, the NMOS tube M42, the NMOS tube M44, the resistor R41, the resistor R42 and the capacitor C41 form a buffer with an RC filtering function; a Schmitt trigger is formed by a PMOS tube M45, a PMOS tube M46, a PMOS tube M49, an NMOS tube M47, an NMOS tube M48 and an NMOS tube M410; the PMOS transistor M411 and the NMOS transistor M412 form an output inverter. The input end of the buffer with the RC filtering function is connected to the comparison output voltage Vo1 of the wide voltage range comparator circuit, the output end of the buffer with the RC filtering function is connected to the input end of the schmitt trigger, the output end of the schmitt trigger is connected to the input end of the output inverter, and the output end of the output inverter is the final data output Dout of the high common mode transient suppression differential signal receiving circuit 6.

The internal circuit structure of the three-level comparator is as follows: the PMOS tube M401, the PMOS tube M402, the PMOS tube M403, the resistor R401 and the resistor R402 form an input stage of a three-stage comparator, the PMOS tube M404, the PMOS tube M405, the PMOS tube M406, the NMOS tube M407 and the NMOS tube M408 form an amplification stage of the three-stage comparator, and the PMOS tube M409 and the NMOS tube M4010 form an output stage of the three-stage comparator; the connection relationship of the internal circuit of the buffer with the RC filtering function is as follows: the grid electrodes of the PMOS tube M41 and the NMOS tube M42 are connected to the comparison output voltage of the three-stage comparator at the same time, the drain electrodes of the PMOS tube M41 and the NMOS tube M42 are connected to the grid electrodes of the PMOS tube M43 and the NMOS tube M44 at the same time, the drain electrode of the PMOS tube M43 is connected to the upper end of the resistor R41, the lower end of the resistor R41 is connected to the upper end of the resistor R42, the upper end of the capacitor C41 and the input end of the Schmidt trigger, the lower end of the resistor R42 is connected to the drain electrode of the NMOS tube M44, the simultaneous source electrodes of the PMOS tube M41 and the PMOS tube M43 are connected to a power supply voltage VCC, and the source electrodes of the NMOS tube M42 and the NMOS tube M44 and.

The output shaping circuit 604 of the present invention shown in fig. 11 provides, on the one hand, a three-stage comparator for converting an input differential signal into a standard digital logic signal Dout; on the other hand, the RC low-pass filtering and the Schmitt trigger combined filtering are adopted, and a certain hysteresis quantity is kept so as to effectively filter the high-frequency interference influence caused by the common-mode noise.

Fig. 12 is a specific implementation of the common mode adaptive adjustment circuit 605 according to the present invention, which includes a common mode detection circuit 100, a common mode detection signal transmission circuit 101, an adjustment common mode signal generation circuit 102, and a common mode adjustment signal selection circuit 103. The common mode detection circuit 100 is configured to detect power supply and substrate noise, and change the magnitude of a common mode detection signal Vcm _ det when the noise is greater than a certain threshold, where the common mode detection signal Vcm _ det is connected to the common mode detection signal transmission circuit 101, and the Vcm _ det generates common mode selection switch control signals N11, N12, N21, N22, …, NX1, NX2, NN1, NN2 through the common mode detection signal transmission circuit 101, and outputs the common mode selection switch control signals N11, N12, N21, N22, N1, N2, NN1, and NN2 to the common mode; the common mode adjusting signal selecting circuit 103 generates and adjusts the magnitude of the common mode adjusting signals C11, C12, C21, C22, …, CX1, CX2, CN1 and CN2 according to the common mode selecting switch control signal and outputs the common mode adjusting signals; the adjustment common mode signal generating circuit 102 is configured to generate various common mode bias signals required by the common mode adjustment signal selecting circuit 103, and output the common mode bias signals to the common mode adjustment signal selecting circuit 503.

In the circuit shown in fig. 12, the common mode detection signal transmission circuit 101 is implemented by using a distributed inverter chain, and the common mode detection signal Vcm _ det is propagated through N sets of distributed inverter chains to obtain N sets of common mode control signals. The adjustment common mode signal generating circuit 102 generates a high input common mode level Vcmh and a low input common mode level Vcml through a bias signal path from the power supply voltage VDD to SW. For the implementation of Vcmh and Vcml, an implementation with the minimum hardware overhead is shown in the figure, and the same function can be realized by adopting reference voltage division or other circuits such as LDO and the like, which are not described herein. The common mode adjusting signal selecting circuit 103 has an internal circuit of a switch selecting array, and the switch array determines the outputs of the common mode adjusting signals C11, C12, C21, C22, …, CX1, CX2, CN1 and CN2 according to the values of the common mode selecting switch control signals N11, N12, N21, N22, …, NX1, NX2, NN1 and NN 2.

Fig. 13 shows an implementation of the common mode detection circuit 100 according to the present invention. The common mode detection circuit 100 is used to detect power supply and substrate noise, and change the magnitude of the common mode detection signal Vcm _ det when the noise is greater than a certain threshold value, so as to control the output of the common mode adaptive adjustment circuit 605 shown in fig. 12. The common mode detection circuit is composed of a PMOS tube M111, a PMOS tube M112 and an NMOS tube M113; the grid electrode and the drain electrode of the PMOS tube M111 are connected, and the grid electrode is connected with the drain electrode of the PMOS tube M112 and the grid electrode of the NMOS tube M113; the grid electrode of the PMOS tube M112 is connected with the drain electrode of the NMOS tube M113 and is used as an output node of a common mode detection signal Vcm _ det; the sources of the PMOS transistors M111 and M112 are connected to the power supply voltage VDD, and the source of the NMOS transistor M113 is connected to the ground voltage Vgnd 2.

Fig. 14 shows a waveform diagram of the operation of the common mode detection circuit 100. The typical high-voltage half-bridge gate driving circuit is divided into two paths of driving circuit channels of a high side and a low side, and the high side driving circuit adopts a bootstrap boosting mode to realize signal transmission control. Assuming that the circuit is operating in a half bridge driven high side drive circuit, VH is the maximum voltage difference between the half bridge high and low side circuits, the Vgnd2 signal must be connected to the half bridge output node SW, thus requiring Vgnd2 to swing between 0 and VH as well as SW. VDD is connected to a half-bridge driving high-side driving circuit power supply voltage VHB, and VHB is bootstrap-floated by a bootstrap capacitor based on the SW potential, so that the bootstrap voltage VHB becomes SW + VCC and becomes VH + VCC during normal operation. The capacitor bootstrap charging also needs a certain charging time, and in the capacitor charging process, the bootstrap voltage cannot completely synchronize with the fluctuation of the SW, so that a certain delay exists between the VDD and the SW, the voltage difference between the power supply and the ground in a delay interval is not strictly equal to the VDD, which is equivalent to the common-mode noise of the power supply, and when the noise amplitude is large enough, the circuit function is influenced, and the false triggering of the comparator is generated.

As shown in the waveforms of fig. 14, when the half-bridge output SW is stable, the VDD and Vgnd2 voltages are in a stable state, M111 is turned on, M113 is turned on, and Vcm _ det will be pulled down to Vgnd2 by M113, and is at a low level; when the half-bridge output SW is switched from 0 to VH, Vgnd2 voltage is synchronously switched to VH, but a certain delay exists in the bootstrap voltage, a certain delay interval is generated, VDD does not reach VH + VCC in the delay interval, the grid voltage of M113 is not enough to enable M113 to be switched on, M113 is switched off, Vcm _ det under the effect of parasitic capacitance is influenced by Vgnd2 to generate a peak high pulse until VDD reaches VH + VCC, at the moment, M113 is switched on again, and Vcm _ det is pulled down to Vgnd2 by M113.

As shown in fig. 2, the total isolation of the capacitive isolation SiC MOSFET driving chip of the present invention is realized by two sets of isolation capacitors (Ctp and Crp form a set of P-end series isolation capacitors, Ctn and Crn form a set of N-end series isolation capacitors) arranged in series to achieve voltage-withstanding isolation, and the middle is connected to the upper plates of the two series isolation capacitors through Bonding wires (Bonding wires), so that the total voltage-withstanding value of the capacitive isolator chip is the sum of the voltage-withstanding values of the two capacitors in the series capacitors. Usually, the withstand voltage of SiO2 is about 500V/um, and in a CMOS process of 0.18um, if M1 is used as the lower plate of the isolation capacitor and M6 is used as the upper plate of the isolation capacitor, the total thickness of SiO2 between metal layers is about 6-7 um, that is, the withstand voltage of a single isolation capacitor is about 3000V-3500V, and the withstand voltages of two isolation capacitors are about 6000V-7000V. The voltage resistance can meet common and conventional application, and cannot meet the voltage resistance requirement of ultrahigh voltage isolation.

As shown in fig. 15, the present invention provides an ultra high withstand voltage separating capacitor, including: a deep N-well isolation region DNWELL 50, a lower plate (a first layer M1)51, an upper plate 54 and SiO arranged between the lower plate 51 and the upper plate 54 from bottom to top₂A layer 52 and a passivation layer 53, the passivation layer 53 being SiO₂And Si₃N₄And (3) superposition. Wherein, SiO₂The layer thickness mainly is VIA12, M2 (second layer), VIA23, M3 (third layer), VIA34, M4 (fourth layer), VIA45, M5 (fifth layer), VIA56, M6 (sixth layer), and the sum thickness is 8 ~ 9um, and the thickness of passivation layer 53 is 2 ~ 3 um. Si in the passivation layer 53₃N₄Is arranged on SiO in an overlapping way₂Above because of Si₃N₄Having a specific SiO ratio₂Better compactness and pressure resistance. The upper plate 54 is made of metal Cu, and the upper plate 54 is formed by processing the rear end of the wafer, and a layer of metal Cu is formed on the passivation layer 53, and the metal Cu also serves as a PAD. A deep N-well isolation region DNWELL 50 is arranged below the lower polar plate 51, and a substrate of a wafer is arranged below the deep N-well isolation region 50; the area of the deep N-well isolation region 50 is larger than the planar area of the lower plate 51, and the deep N-well isolation region completely covers the lower plateThe lower surface of the plate 51.

According to the scheme of the ultrahigh voltage-withstanding isolation capacitor, the thickness of the passivation layer is controlled to be about 2.5um through process adjustment, the thickness of a single isolation capacitor is about 12um approximately, and the voltage withstanding value can reach 6000V, so that the total thickness of two isolation capacitors connected in series is about 24um, the total voltage withstanding value can reach 12000V, and the requirement of isolation enhancement can be met. The capacitance value is reduced after the isolation capacitor is thickened, the area of the polar plate of the isolation capacitor can be properly increased, the capacitance value of the isolation capacitor is basically kept unchanged, and the transmission quality of the whole isolation signal is not influenced.

Fig. 16 is a block diagram of a low voltage generating circuit used in the low voltage generating circuit 3 of the transmitting terminal, in which the input is a transmitting terminal input power voltage VCCbus, the output is a low voltage analog power supply AVCC and a low voltage digital power supply DVCC, and the voltages of the two power supplies are equal and equal to the transmitting terminal power voltage VCC. The receiving-side low voltage generation circuit 8 may also be implemented using the same low voltage generation circuit shown in fig. 16.

The low voltage generating circuit internally comprises: the circuit comprises a starting circuit 301, an analog circuit module low-voltage power supply circuit 302, a digital circuit module low-voltage power supply circuit 303, a self-biased bandgap reference voltage generating circuit 304, a bias signal generating circuit 305, a reference voltage generating circuit 306 and n identical reference voltage buffer output circuits 307. The starting circuit 301, the analog circuit module low-voltage power supply circuit 302 and the digital circuit module low-voltage power supply circuit 303 adopt the same sending end to input power supply voltage VCCbus; the self-biased bandgap reference voltage generating circuit 304, the bias signal generating circuit 305, the reference voltage generating circuit 306 and the n same reference voltage buffer output circuits 307 adopt the same low-voltage analog power supply AVCC. The analog circuit module low-voltage power supply circuit 302 generates a low-voltage analog power supply AVCC according to a sending end input power supply voltage VCCbus, and the digital circuit module low-voltage power supply circuit 303 generates a low-voltage digital power supply DVCC according to the sending end input power supply voltage VCCbus. The bias signal generating circuit 305 generates all bias signals required by the reference voltage generating circuit 306 and the n identical reference voltage buffer output circuits 307.

The self-biased bandgap reference voltage generating circuit 304 outputs a bandgap reference voltage Vref to the reference voltage generating circuit 306, and the reference voltage generating circuit 306 generates n reference voltages according to the bandgap reference voltage Vref, where the n reference voltages are first reference voltages V with different magnitudes_R1A second reference voltage V_R2… …, nth reference voltage V_Rn. The n reference voltages are respectively input to n reference voltage buffer output circuits 307, and n output reference voltages with large driving capability, i.e. a first reference voltage V, are obtained correspondingly_R1Entering a first reference voltage buffer output circuit to obtain a first output reference voltage V_RO1Second reference voltage V_R2Entering a second reference voltage buffer output circuit to obtain a second output reference voltage V_RO2… …, nth reference voltage V_RnEntering an nth reference voltage buffer output circuit to obtain an nth output reference voltage V_ROn。

After the power supply voltage VCCbus input at the transmitting end is powered on, the start circuit 301 is the first circuit to be turned on in the whole chip, and usually provides a certain initial bias signal to the analog circuit module low-voltage power supply circuit 302 and the digital circuit module low-voltage power supply circuit 303, so as to generate a low-voltage analog power supply AVCC and a low-voltage digital power supply DVCC respectively. The low voltage analog power supply AVCC supplies power to the self-biased bandgap reference voltage generation circuit 304, the bias signal generation circuit 305, the reference voltage generation circuit 306 and the n same reference voltage buffer output circuits 307, and finally generates n output reference voltages V_RO1～V_ROn。

Fig. 17 shows an implementation of the analog circuit block low voltage power supply circuit 302. The analog circuit module low voltage power supply circuit 302 includes: the NPN triode Q1, the resistor R170, the resistor R171, the resistor R172, the NMOS transistor M171, the NMOS transistor M174, the NMOS transistor M175, the NMOS transistor M178, the PMOS transistor M172, the PMOS transistor M173, the PMOS transistor M176, the PMOS transistor M177 and the capacitor C11. The NMOS transistor M171, the NMOS transistor M174, the NMOS transistor M175 and the NMOS transistor M178 are all high-voltage MOS transistors, and the PMOS transistor M172, the PMOS transistor M173, the PMOS transistor M176 and the PMOS transistor M177 are all low-voltage MOS transistors; the high-voltage MOS tube refers to an MOS tube with source-drain withstand voltage larger than 10V, and the low-voltage MOS tube refers to an MOS tube with source-drain withstand voltage smaller than 7V.

The lower end of the resistor R170 is connected with the grid electrode and the drain electrode of the NMOS tube M171, and is also connected with the grid electrodes of the NMOS tube M174 and the NMOS tube M175; the source electrode of the NMOS transistor M171 is connected to the collector electrode and the base electrode of an NPN triode Q1; the drain electrode of the PMOS tube M172 is connected with the grid electrode, and is also connected with the source electrode of the PMOS tube M173 and the grid electrode of the PMOS tube M177; the drain electrode of the PMOS tube M173 is connected with the grid electrode, and is also connected with the drain electrode of the NMOS tube M174 and the grid electrode of the PMOS tube M176; the source of the NMOS transistor M174 is connected to the upper end of the resistor R171, and the source of the NMOS transistor M175 is connected to the upper end of the resistor R172; the drain electrode of the PMOS tube M176 is connected to the drain electrode of the NMOS tube M175, and the source electrode of the PMOS tube M176 is connected to the drain electrode of the PMOS tube M177 and the grid electrode of the NMOS tube M178; the source electrode of the NMOS tube M178 is connected to the upper end of the capacitor C11 and also serves as an output node of a low-voltage analog power supply AVCC; the upper end of the resistor R10, the source electrode of the PMOS tube M172, the source electrode of the PMOS tube M177 and the drain electrode of the NMOS tube M178 are simultaneously connected with VCCbus; the emitter of the NPN transistor Q1, the lower end of the resistor R170, the lower end of the resistor R171, and the lower end of the capacitor C11 are connected to the ground voltage at the same time.

In the circuit of fig. 17, the leftmost resistor R170, the NMOS transistor M171, and the NPN transistor Q1 form a dc path from the power supply to the ground, and generate a bias voltage at the gate terminal of M171 to provide bias to the branches of the PMOS transistor M172, the PMOS transistor M173, and the NMOS transistor M174, and further mirror and bias provide the gate bias of the NMOS transistor M178, so as to obtain the output low voltage analog power supply AVCC. To provide a sufficiently large driving current, the NMOS transistor M178 is typically a large-sized transistor. C11 is the filter capacitance, generally the larger the better. The low-voltage analog power supply AVCC is obtained by subtracting a Vth voltage from the gate voltage of the NMOS transistor M178, and the gate voltage of the NMOS transistor M178 can be realized by adjusting the resistors R171 and R172.

FIG. 18 shows an implementation of the reference voltage generating circuit 306 according to the present invention. The circuit is a multi-output LDO circuit, a band-gap reference voltage Vref is connected to a positive input end of an operational amplifier A1, an output end of the operational amplifier A1 is connected to an adjusting MOS tube MR1, then a resistor string is connected for voltage division to generate a feedback signal, the feedback signal is connected to a negative input end of the operational amplifier to form a negative feedback loop, and n reference voltages V are generated from nodes of the resistor string_R1，V_R2，…，V_Rn. The band-gap reference voltage Vref is provided for a band-gap reference generating circuit, and the band-gap reference generating circuit can be realized by adopting a general band-gap generating circuit.

FIG. 19 is one implementation of a single reference voltage buffer output circuit. The circuit comprises a PMOS tube M191, a PMOS tube M192, a PMOS tube M193, a PMOS tube M196, a PMOS tube M197, a PMOS tube M1910, an NMOS tube M194, an NMOS tube M195, an NMOS tube M198, an NMOS tube M199, an NMOS tube M1911, a resistor R191, a resistor R192, a resistor R193 and a resistor R194.

The gates of the PMOS tubes M191 and M1910 are connected to a bias voltage Vbn; the drain electrode of the PMOS tube M191 is simultaneously connected to the source electrodes of the PMOS tube M192 and the PMOS tube M193; the grid electrode of the PMOS pipe M193 is connected to a reference voltage V_Rn(ii) a The grid electrode of the PMOS tube M192 is connected to the output feedback signal V_F(ii) a The drain electrode and the grid electrode of the NMOS tube M194 are simultaneously connected to the grid electrode of the NMOS tube M198 and the drain electrode of the PMOS tube M192; the drain and the gate of the NMOS transistor M195 are simultaneously connected to the gate of the NMOS transistor M199 and the drain of the PMOS transistor M193; the drain electrode of the NMOS tube M198 is connected to the drain electrode and the grid electrode of the PMOS tube M196, and is also connected to the grid electrode of the PMOS tube M197; the drain electrode of the NMOS tube M199 is connected to the drain electrode of the PMOS tube M197 and the gate electrode of the NMOS tube M1911; the drain electrode of the PMOS pipe M1910 is connected with the drain electrode of the NMOS pipe M1911 and is connected to the upper end of the resistor R191; the lower end of resistor R191 is connected to the upper end of resistor R192 and serves as the output node of the positive terminal reference level Vro1 p; the lower end of the resistor R192 is connected to the upper end of the resistor R193 and also serves as an output feedback signal V_FAn output node of (a); the lower end of the resistor R193 is connected to the upper end of the resistor R194 and also serves as an output node of the negative terminal reference level Vro1 n; the sources of the PMOS transistor M191, the PMOS transistor M196, the PMOS transistor M197 and the PMOS transistor M1910 are simultaneously connected to AVCC (VCC); the source of the NMOS transistor M194, the NMOS transistor M195, the NMOS transistor M198, the NMOS transistor M199, the source of the NMOS transistor M1911 and the lower end of the resistor R194 are connected to the ground voltage at the same time. Any one of the positive terminal reference level Vro1p and the negative terminal reference level Vro1n can be used as an output reference voltage of the reference voltage buffer output circuit.

The circuit shown in FIG. 19 comprises PMOS transistor M191, PMOS transistor M192, PMOS transistor M193, PMOS transistor M196, PMOS transistor M197, NMOS transistor M194, NMOS transistor M195, and NMOS transistor,The NMOS tube M198 and the NMOS tube M199 form an operational amplifier with a two-stage push-pull output structure, so that wide-swing output is provided to the maximum extent; the PMOS tube M1910 and the NMOS tube M1911 form a wide-swing output stage circuit, a resistor voltage division network formed by connecting a driving resistor R191, a resistor R192, a resistor R193 and a resistor R194 in series is used for providing a positive terminal reference level Vro1p and an output feedback signal V_FAnd a negative side reference level Vro1 n; output feedback signal V_FThe feedback is connected to the ready negative feedback of the input end of the operational amplifier, and the output feedback signal V is output_FClamped to an input reference voltage V_Rn(ii) a According to the resistance voltage division, the negative terminal reference level Vro1n is Vr R194/(R193+ R194), the positive terminal reference level Vro1p is Vr (R192+ R193+ R194)/(R193+ R194), and the positive terminal reference level Vro1p and the negative terminal reference level Vro1n can be accurately set by setting the resistance ratio.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. Insulating isolation SiC MOSFET gate drive circuit of superhigh pressure, characterized by includes: the circuit comprises an input receiving circuit (1), a digital control circuit (2), a modulation transmitting circuit (5), an isolation circuit (9), a high common mode transient suppression differential signal receiving circuit (6), an output driving circuit (7), a transmitting end low voltage generating circuit (3), a receiving end low voltage generating circuit (8) and a chip state monitoring circuit (4), wherein the input receiving circuit (1), the digital control circuit (2), the modulation transmitting circuit (5), the transmitting end low voltage generating circuit (3) and the chip state monitoring circuit (4) form a driving circuit transmitting end circuit, and the high common mode transient suppression differential signal receiving circuit (6), the output driving circuit (7) and the receiving end low voltage generating circuit (8) form a driving circuit receiving end circuit; the ground potentials of all circuits inside the sending end circuit of the driving circuit are connected to a sending end ground voltage Vgnd1, and the ground potentials of all circuits inside the receiving end circuit of the driving circuit are connected to a receiving end ground voltage Vgnd 2; the isolation circuit (9) comprises a positive end sending capacitor Ctp, a negative end sending capacitor Ctn, a positive end receiving capacitor Crp and a negative end receiving capacitor Crn;

the input receiving circuit (1) receives external low-level logic input data DI, converts the DI into input data Din with high level VCC, and outputs the input data Din to the digital control circuit (2); the digital control circuit (2) processes input data Din into a group of differential data DxP and DxN according to the states of an undervoltage protection signal UVLO, an over-temperature protection signal OTP and an over-current protection signal OCP provided by the chip state monitoring circuit (4); the differential data DxP and DxN enter a modulation transmitting circuit (5) to obtain differential transmitting data TxP and TxN; the differential sending data TxP and TxN are respectively connected to the left end of a positive terminal sending capacitor Ctp and the left end of a negative terminal sending capacitor Ctn, the right end of the positive terminal sending capacitor Ctp and the right end of the negative terminal sending capacitor Ctn are respectively connected to the left end of a positive terminal receiving capacitor Crp and the left end of a negative terminal receiving capacitor Crn, differential receiving data RxP and RxN are respectively generated at the right end of the positive terminal receiving capacitor Crp and the right end of the negative terminal receiving capacitor Crn, the differential receiving data and the RxN enter a high common-mode transient suppression differential signal receiving circuit (6), and receiving output data Dout is obtained after processing; receiving the output data Dout and finally entering an output driving circuit (7) to generate an output driving signal DG with large driving current;

the transmitting end low voltage generating circuit (3) adopts transmitting end input power supply voltage VCCbus to generate transmitting end power supply voltage VCC and reference voltage and bias voltage required by each component circuit in the transmitting end circuit of the driving circuit; the receiving end low voltage generating circuit (8) adopts receiving end input power supply voltage VDDBUS to generate receiving end power supply voltage VDD and reference voltage and bias voltage which are used for driving all the internal component circuits of the receiving end circuit of the circuit; the sending end low-voltage generating circuit (3) and the receiving end low-voltage generating circuit (8) are realized by adopting the same low-voltage generating circuit; the positive end sending capacitor Ctp, the negative end sending capacitor Ctn, the positive end receiving capacitor Crp and the negative end receiving capacitor Crn are equal in size and are all ultrahigh voltage-resistant isolation capacitors.

2. The ultra-high voltage isolation SiC MOSFET gate drive circuit according to claim 1, wherein the high common mode transient suppression differential signal receiving circuit (6) comprises: the device comprises a differential input receiving circuit (601), an X-level front-back cascade common mode adjustable amplifying circuit (602), a high-sensitivity common mode adjustable amplifying circuit (603), an output shaping circuit (604) and a common mode self-adaptive adjusting circuit (605); the differential input receiving circuit (601) receives a positive terminal receiving signal RxP and a negative terminal receiving signal RxN of differential receiving data at first, and obtains a positive terminal input signal Vip and a negative terminal input signal Vin through filtering processing; the positive end input signal Vip and the negative end input signal Vin enter a first-stage common mode adjustable amplifying circuit in an X-stage common mode adjustable amplifying circuit (602) which is cascaded in front and at the back, and finally a positive end output signal VoXp and a negative end output signal VoXn of the X-stage common mode adjustable amplifying circuit are obtained; the positive end output signal VoXp and the negative end output signal VoXn are respectively connected with the positive input end and the negative input end of the high-sensitivity common mode adjustable amplifying circuit (603), and the high-sensitivity common mode adjustable amplifying circuit (603) outputs a group of differential output signals which comprise the positive end output signal VoXp and the negative end output signal VoXn; the output shaping circuit (604) obtains final data output through processing according to the magnitude of the positive end output signal VoXp and the negative end output signal VoXn, namely receiving output data Dout; the common mode self-adaptive adjusting circuit (605) generates common mode adjusting signals C11, C12, C21, C22, …, CX1 and CX2 for each stage of amplifying circuit in a self-adaptive mode according to changes of power supply and ground voltage signals, and the common mode adjusting signals C11 and C12 generated by the common mode self-adaptive adjusting circuit (605) are respectively connected to a common mode adjusting signal input end of the first stage of common mode adjustable amplifying circuit; the common mode adjusting signals C21 and C22 are respectively connected to the common mode adjusting signal input end of the second-stage common mode adjustable amplifying circuit; by analogy, the common mode adjusting signals CX1 and CX2 are respectively connected to the common mode adjusting signal input end of the X-th order common mode adjustable amplifying circuit; the common mode adaptive adjusting circuit (605) also generates common mode adjusting signals CN1 and CN2 which are respectively connected to the common mode adjusting signal input end of the high-sensitivity common mode adjustable amplifying circuit (603); wherein X is a positive integer greater than 1, and N is a positive integer greater than X.

3. The ultra high voltage isolation SiC MOSFET gate drive circuit of claim 2, wherein the differential input receiving circuit (601) comprises: a positive side isolation capacitor C51, a positive side grounding resistor R51, a positive side coupling capacitor C52, a positive side common mode resistor R53, a negative side isolation capacitor C53, a negative side grounding resistor R52, a negative side coupling capacitor C54, a negative side common mode resistor R54 and a receiving common mode generating circuit (6011); the left end of the positive side isolation capacitor C51 and the left end of the negative side isolation capacitor C53 are connected to a positive side receiving signal RXP and a negative side receiving signal RXN, respectively; the right end of the positive side isolation capacitor C51 is connected to the lower end of the positive side ground resistor R51 and the left end of the positive side coupling capacitor C52; the right end of the negative side isolation capacitor C53 is connected to the lower end of the negative side ground resistor R52 and the left end of the negative side coupling capacitor C54; the right end of the positive terminal coupling capacitor C52 is connected to the upper end of the positive terminal common mode resistor R53 and serves as the output terminal of the positive terminal input signal Vip; the right end of the negative end coupling capacitor C54 is connected to the lower end of the negative end common mode resistor R54 and serves as the output end of a negative end input signal Vin; the lower end of the positive end common mode resistor R53 is connected with the upper end of the negative end common mode resistor R54 and is simultaneously connected to a common mode output end Vicm of the receiving common mode generating circuit (6011); the receiving common mode generating circuit (6011) dynamically tracks and adjusts the size of a common mode output end Vicm according to the change of an input common mode Vcm, and the influence of an input common mode is reduced.

4. The ultra-high voltage isolation SiC MOSFET gate drive circuit according to claim 3, wherein the receiving common mode generating circuit (6011) comprises: NMOS transistor M60, NMOS transistor M61, PMOS transistor M62, NMOS transistor M63, PMOS transistor M64, PMOS transistor M65, NMOS transistor M66, NMOS transistor M67, PMOS transistor M68, NMOS transistor M69, PMOS transistor M610, NMOS transistor M611, PMOS transistor M612, NMOS transistor M613, NMOS transistor M614, PMOS transistor M615, resistor R61, and first Schmidt trigger (600);

the grid electrode of the NMOS tube M60 is connected to an input common mode voltage Vcm; the drain electrode of the NMOS tube M60 is connected to the drain electrode and the gate electrode of the PMOS tube M62 and the gate electrode of the NMOS tube M63; the grid electrode of the NMOS tube M61 is connected to an input common mode control signal Vctrl; the drain electrode of the NMOS tube M61 is connected with the drain electrode of the NMOS tube M63 and is connected to the input end of the first Schmitt trigger (600); the output end of the first Schmitt trigger (600) is simultaneously connected to the grid electrode of the PMOS tube M610, the grid electrode of the NMOS tube M611, the grid electrode of the PMOS tube M612 and the grid electrode of the NMOS tube M613; the drain electrode of the PMOS tube M610 is connected with the drain electrode of the NMOS tube M611 and is also connected to the grid electrode of the NMOS tube M614; the drain of the PMOS tube M612 is connected with the drain of the NMOS tube M613, and is also connected to the gate of the PMOS tube M615; the source electrode of the NMOS tube M614 is connected with the source electrode of the PMOS tube M615 and is also used as an output port of the common mode output end Vicm; the drain electrode of the NMOS tube M614 is connected to a high input common mode level Vcmh, and the drain electrode of the PMOS tube M615 is connected to a low input common mode level Vcml; the source of the NMOS transistor M613 is connected to the upper end of the resistor R61; the source electrode of the NMOS tube M60, the source electrode of the NMOS tube M61, the source electrode of the NMOS tube M611 and the lower end of the resistor R61 are simultaneously connected to a receiving end ground voltage Vgnd 2; the source of the PMOS transistor M62, the source of the NMOS transistor M63 and the source of the PMOS transistor M610 are simultaneously connected to the receiving terminal power voltage VDD.

5. The gate driving circuit of the ultra-high voltage insulated isolation SiC MOSFET of claim 2, wherein the high-sensitivity common-mode adjustable amplifier circuit (603) is a front-and-back two-stage fully differential amplifier circuit, comprising a front-stage common-mode adjustable amplifier circuit and a back-stage differential amplifier circuit connected with each other; the positive input end of the preceding common mode adjustable amplifying circuit is the positive input end of the high-sensitivity common mode adjustable amplifying circuit (603), and the negative input end of the preceding common mode adjustable amplifying circuit is the negative input end of the high-sensitivity common mode adjustable amplifying circuit (603); a positive output end VoNp of the differential amplifying circuit is a positive output end of the high-sensitivity common-mode adjustable amplifying circuit (603), and a negative output end VoNn of the differential amplifying circuit is a negative output end of the high-sensitivity common-mode adjustable amplifying circuit (603);

6. The gate driving circuit of the ultra-high voltage insulation isolation SiC MOSFET, as recited in claim 2, wherein the output shaping circuit (604) comprises a three-level comparator, a buffer with RC filtering function, a second Schmitt trigger and an output inverter, which are connected in sequence, and the output end of the output inverter is the final output data, i.e. the received output data Dout; the connection relationship of the internal circuit of the buffer with the RC filtering function is as follows: the grid electrode of the PMOS tube M41 and the grid electrode of the NMOS tube M42 are simultaneously connected to the comparison output voltage of the three-stage comparator, the drain electrode of the PMOS tube M41 and the drain electrode of the NMOS tube M42 are simultaneously connected to the grid electrode of the PMOS tube M43 and the grid electrode of the NMOS tube M44, the drain electrode of the PMOS tube M43 is connected to the upper end of a resistor R41, the lower end of the resistor R41 is connected to the upper end of a resistor R42, the upper end of a capacitor C41 and the input end of a second Schmidt trigger, the lower end of the resistor R42 is connected to the drain electrode of the NMOS tube M44, the source electrode of the PMOS tube M41 and the source electrode of the PMOS tube M43 are simultaneously connected to a power supply voltage VCC, and the source electrode of the NMOS tube M42.

7. The gate drive circuit of an extra-high voltage isolation SiC MOSFET of claim 2, wherein the common mode adaptive adjustment circuit (605) comprises: the common mode detection circuit (100), the common mode detection signal transmission circuit (101), the adjustment common mode signal generation circuit (102) and the common mode adjustment signal selection circuit (103); the common mode detection circuit (100) is used for detecting power supply and substrate noise and changing the size of a common mode detection signal Vcm _ det when the noise is larger than a certain threshold, the common mode detection signal Vcm _ det is connected to the common mode detection signal transmission circuit (101), common mode selection switch control signals N11, N12, N21, N22, …, NX1, NX2, NN1 and NN2 are generated through the common mode detection signal transmission circuit (101) and output to the common mode adjustment signal selection circuit (103); the common mode adjusting signal selection circuit (103) generates and adjusts the magnitude of common mode adjusting signals C11, C12, C21, C22, …, CX1, CX2, CN1 and CN2 according to the common mode selecting switch control signal and outputs the common mode adjusting signals; the adjusting common-mode signal generating circuit (102) is used for generating various common-mode bias signals required by the common-mode adjusting signal selecting circuit (103) and outputting the common-mode bias signals to the common-mode adjusting signal selecting circuit (103).

8. The ultra-high voltage isolation SiC MOSFET gate drive circuit of claim 7, wherein the common mode detection circuit (100) comprises: a PMOS transistor M111, a PMOS transistor M112 and an NMOS transistor M113; the grid electrode and the drain electrode of the PMOS tube M111 are connected, and the grid electrode is connected with the drain electrode of the PMOS tube M112 and the grid electrode of the NMOS tube M113; the grid electrode of the PMOS tube M112 is connected with the drain electrode of the NMOS tube M113 and is used as an output node of a common mode detection signal Vcm _ det; the source of the PMOS transistor M111 and the source of the PMOS transistor M112 are connected to a power supply voltage VDD, and the source of the NMOS transistor M113 is connected to a receiving terminal ground voltage Vgnd 2.

9. The gate driving circuit of an ultra-high voltage isolation SiC MOSFET according to claim 1, wherein the transmitting-side low voltage generating circuit (3) comprises: the circuit comprises a starting circuit (301), an analog circuit module low-voltage power supply circuit (302), a digital circuit module low-voltage power supply circuit (303), a self-biased bandgap reference voltage generating circuit (304), a bias signal generating circuit (305), a reference voltage generating circuit (306) and n identical reference voltage buffer output circuits (307); n is a natural number greater than or equal to 2;

the starting circuit (301), the analog circuit module low-voltage power supply circuit (302) and the digital circuit module low-voltage power supply circuit (303) adopt a sending end input power supply voltage VCCbus, the analog circuit module low-voltage power supply circuit (302) generates a low-voltage analog power supply AVCC according to the sending end input power supply voltage VCCbus, and the digital circuit module low-voltage power supply circuit (303) generates a low-voltage digital power supply DVCC according to the sending end input power supply voltage VCCbus; the self-biased bandgap reference voltage generating circuit (304), the bias signal generating circuit (305), the reference voltage generating circuit (306) and the n same reference voltage buffer output circuits (307) adopt a low-voltage analog power supply AVCC; the bias signal generating circuit (305) generates all bias signals required by the reference voltage generating circuit (306) and the n same reference voltage buffer output circuits (307); the voltage of the low-voltage analog power supply AVCC and the voltage of the low-voltage digital power supply DVCC are equal and equal to the power supply voltage VCC of a sending end;

the self-biased bandgap reference voltage generation circuit (304) outputs a bandgap reference voltage Vref and is connected to an input terminal of a reference voltage generation circuit (306), and the reference voltage generation circuit (306) generates n reference voltages according to the bandgap reference voltage Vref, specifically, first reference voltages V with different sizes_R1A second reference voltage V_R2… …, nth reference voltage V_Rn(ii) a The n reference voltages are respectively input into n reference voltage buffer output circuits (307), and n output reference voltages with larger driving capability, namely a first reference voltage V, are correspondingly obtained_R1Entering a first reference voltage buffer output circuit to obtain a first output reference voltage V_RO1Second reference voltage V_R2Entering a second reference voltage buffer output circuit to obtain a second output reference voltage V_RO2… …, nth reference voltage V_RnEntering an nth reference voltage buffer output circuit to obtain an nth output reference voltage V_ROn。