CN118554894A - Isolation driving receiving circuit for improving common mode transient immunity - Google Patents
Isolation driving receiving circuit for improving common mode transient immunity Download PDFInfo
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Abstract
The invention relates to an isolation driving receiving circuit for improving common mode transient immunity. The invention comprises a modulation transmitting module, an isolation capacitor, a first differential amplifier, a second differential amplifier, a current compensation module, a demodulation module, a common mode transient detection module and a pulse shielding module; the modulation transmitting module is used for converting an input single-ended signal into a high-frequency differential carrier signal; the input end of the first differential amplifier is connected with the output end of the modulation transmitting module through an isolation capacitor, and the output end of the first differential amplifier is connected with the input end of the second differential amplifier; the current compensation module is connected with the first differential amplifier; the input end and the output end of the demodulation module are respectively connected with the output end of the second differential amplifier and the input end of the pulse shielding module, the input end of the pulse shielding module is connected with the output end of the demodulation module, and the pulse shielding module is further connected with the isolation capacitor through the common mode transient detection module. The invention effectively improves the common mode transient immunity of the chip.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an isolation driving receiving circuit for improving common mode transient immunity.
Background
When the isolation type chip works in different voltage domains, a voltage difference of hundreds of volts is often arranged between the high voltage domain and the low voltage domain, when the voltage of the high voltage domain is switched at a high speed, the generated high-speed voltage change rate (dv/dt) can bring a large common mode current through an internal isolation capacitor, the common mode current can extract or pour current from a receiving end (RX) according to the positive and negative of the dv/dt, so that the chip function is abnormal, and the larger the common mode current is, the more serious the influence degree is. Thus, the Common Mode Transient Immunity (CMTI) of the chip can be improved from the point of view of the common mode current.
When dv/dt is constant, the current I=C of the isolation capacitor is dv/dt, the magnitude of common mode current is in direct proportion to the capacitance value of the isolation capacitor, the capacitance value of the isolation capacitor can be reduced to improve the CMTI of the chip, but the capacitance value of the isolation capacitor also affects the transmission of carrier signals, the larger the capacitance value of the isolation capacitor is, the larger the amplitude of the carrier signals which can be accepted by the receiving end is, the more beneficial to demodulation, and therefore the selection of the capacitance value of the isolation capacitor can be balanced between the two. This often results in isolated chips that are fixed with unreduced common mode currents and require other ways to optimize the effects of the common mode currents.
Disclosure of Invention
Therefore, the invention provides an isolation driving receiving circuit for improving the common mode transient immunity, which judges whether a chip experiences common mode transient interference or not by detecting the common mode voltage of a receiving end, and if the chip experiences common mode transient interference, a current path is provided through a differential amplifier; and secondly, when the detected common-mode voltage exceeds a design judgment threshold value, a control signal is generated, and a demodulation abnormal waveform caused by common-mode transient interference is shielded through a switch switching delay circuit.
In order to solve the above technical problems, the present invention provides an isolation driving receiving circuit for improving common mode transient immunity, which is applied to an isolation chip, and includes: the device comprises a modulation transmitting module, an isolation capacitor, a first differential amplifier, a second differential amplifier, a current compensation module, a demodulation module, a common mode transient detection module and a pulse shielding module;
the modulation transmitting module is used for converting an input single-ended signal into a high-frequency differential carrier signal;
The input end of the first differential amplifier is connected with the output end of the modulation transmitting module through the isolation capacitor, the output end of the first differential amplifier is connected with the input end of the second differential amplifier, and the differential carrier signal sequentially passes through the first differential amplifier and the second differential amplifier for amplification after passing through the isolation capacitor;
The current compensation module is connected with the first differential amplifier and is used for providing compensation current for the first differential amplifier when the chip experiences common mode transient interference from low to high; and reducing the current input to the first differential amplifier to reduce the input common mode voltage of the first differential amplifier when the chip experiences high-to-low common mode transient disturbances;
The input end and the output end of the demodulation module are respectively connected with the output end of the second differential amplifier and the input end of the pulse shielding module,
The demodulation module is used for demodulating the output signal of the second differential amplifier and converting the output signal into a single-ended input signal of the transmitting end;
The input end of the pulse shielding module is connected with the output end of the demodulation module, and the pulse shielding module is also connected with the isolation capacitor through the common mode transient detection module;
the common mode transient detection module is used for generating a control signal according to the detected common mode transient interference signal, and the pulse shielding module can receive the control signal and control transmission shielding delay through switching.
In one embodiment of the present invention, the modulation transmitting module adopts OOK modulation.
In one embodiment of the present invention, the first differential amplifier includes an NMOS transistor M3, an NMOS transistor M4, an NMOS transistor M5, an NMOS transistor M6, a resistor RCM1, and a resistor RCM2;
The drains of the NMOS tube M5 and the NMOS tube M6 are correspondingly connected with the grid of the NMOS tube M and are respectively connected to the power supply voltage VDD;
The source electrode of the NMOS tube M5 is connected to the differential signal input end V1-, and the source electrode of the NMOS tube M6 is connected to the differential signal input end V1+;
the drains of the NMOS tube M3 and the NMOS tube M4 are respectively connected with common mode signal input ends V < 2+ > and V < 2 > -and are connected to a power supply voltage VDD through loads;
the grid electrode of the NMOS tube M3 is connected to the grid electrode of the NMOS tube M5, and the source electrode of the NMOS tube M3 is connected to the differential signal input end V1+;
the grid electrode of the NMOS tube M4 is connected to the grid electrode of the NMOS tube M6, and the source electrode of the NMOS tube M4 is connected to the differential signal input end V1-;
The differential signal input terminal v1+ is grounded to the ground terminal GND through the resistor RCM 1;
the differential signal input terminal V1 is grounded to the ground GND through the resistor RCM 2.
In one embodiment of the present invention, the current compensation module includes a first compensation module and a second compensation module;
the first compensation module comprises an NMOS tube M0, a resistor R1 and a resistor R2;
The drain electrode and the source electrode of the NMOS tube M0 are respectively connected to a differential signal input end V1+ and a ground end GND of the first differential amplifier, the grid electrode of the NMOS tube M0 is connected between one end of a resistor R1 and one end of a resistor R2, the other end of the resistor R1 is grounded, and the other end of the resistor R2 is connected with the differential signal input end V1+;
the second compensation module comprises an NMOS tube M1, a resistor R3 and a resistor R4;
The drain electrode and the source electrode of the NMOS tube M1 are respectively connected to a differential signal input end V1-and a ground end GND of the first differential amplifier, the grid electrode of the NMOS tube M1 is connected between one end of a resistor R3 and one end of a resistor R4, the other end of the resistor R3 is grounded, and the other end of the resistor R4 is connected with the differential signal input end V1-.
In one embodiment of the present invention, the common mode transient detection module includes a first comparator, a second comparator, an or gate, and an inverter;
the output end of each of the first comparator and the second comparator is connected to the input end of the OR gate, and the output end of the OR gate is connected to the output end of the inverter.
In one embodiment of the present invention, the input common-mode voltage of the first differential amplifier is connected to the non-inverting input terminal of the first comparator and the inverting input terminal of the second comparator, respectively, the inverting input terminal of the first comparator is connected to a fixed positive value vref+, and the non-inverting input terminal of the second comparator is connected to a fixed negative value vref-.
In one embodiment of the present invention, the pulse shielding module includes an NMOS tube M7, an NMOS tube M8, an NMOS tube M9, an NMOS tube M10, an NMOS tube M11, an NMOS tube M12, an NMOS tube M13, an NMOS tube M14, an NMOS tube M15, a PMOS tube M0, a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, a PMOS tube M5, and a PMOS tube M6;
the source electrodes of the NMOS tube M7, the NMOS tube M8, the NMOS tube M10, the NMOS tube M11, the NMOS tube M12 and the NMOS tube M14 are grounded to the GND;
the grid electrode of the NMOS tube M7 is respectively connected with the drain electrode of the NMOS tube M8 and the grid electrode of the NMOS tube M;
the source electrode of the NMOS tube M9 is connected with the drain electrode of the NMOS tube M8, and the grid electrode of the NMOS tube M9 is connected with a high level V_detect+;
the grid electrode of the NMOS tube M10 is respectively connected with the drain electrode of the NMOS tube M11 and the grid electrode of the NMOS tube M12;
the drain electrode of the NMOS tube M12 is connected with the source electrode of the NMOS tube M13;
the drain electrode of the NMOS tube M14 is connected with the source electrode of the NMOS tube M15, and the grid electrode of the NMOS tube M14 is connected with a high level V_detect+;
The sources of the PMOS tube P0, the PMOS tube P1, the PMOS tube P2, the PMOS tube P3 and the PMOS tube P6 are respectively connected with the power supply voltage VDD;
The drain electrode of the PMOS tube P0 is respectively connected with the grid electrode of the PMOS tube P0, the drain electrode of the NMOS tube M9 and the grid electrode of the PMOS tube P1;
The drain electrode of the PMOS tube P1 is connected with the drain electrode of the NMOS tube M10;
The drain electrode of the PMOS tube P2 is respectively connected with the grid electrode of the PMOS tube P2, the drain electrode of the NMOS tube M11 and the grid electrode of the PMOS tube P3;
the drain electrode of the PMOS tube P3 is connected with the source electrode of the PMOS tube P4;
The drain electrode of the PMOS tube P4 is connected with the drain electrode of the NMOS tube M13, and the grid electrode of the PMOS tube P4 is connected with the grid electrode of the NMOS tube M13;
the grid electrode of the PMOS tube P6 is connected with a high level V_detect+, and the drain electrode of the PMOS tube P6 is connected with the source electrode of the PMOS tube P5;
The drain electrode of the PMOS tube P5 is connected with the drain electrode of the NMOS tube M15, and the grid electrode of the PMOS tube P5 is connected with the grid electrode of the NMOS tube M15;
the demodulated output signal cmp_out is connected between the gate of the PMOS transistor P4 and the gate of the NMOS transistor M13, and between the gate of the PMOS transistor P5 and the gate of the NMOS transistor M15, respectively.
In an embodiment of the present invention, the drain terminal of the PMOS transistor P4 is connected to the drain terminal of the NMOS transistor M13, the drain terminal of the PMOS transistor P5 is connected to the drain terminal of the NMOS transistor M15, and the other terminal of the capacitor c_blank is connected to the ground terminal GND.
In one embodiment of the present invention, the circuit further comprises a schmitt trigger, a first inverter unit and a second inverter unit, wherein the schmitt trigger, the first inverter unit and the second inverter unit are sequentially connected with one end of the capacitor c_blank, and the second inverter unit outputs a pulse shielding signal v_blank.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the isolation driving receiving circuit for improving the common mode transient immunity, the Common Mode Transient Immunity (CMTI) of a chip is effectively improved through the synergistic effect of the first differential amplifier, the second differential amplifier, the current compensation module, the demodulation module, the common mode transient detection module and the pulse shielding module, and the current compensation module can provide or release current when the common mode transient is interfered, so that the influence of the common mode current on the circuit is reduced, and the normal operation of the differential amplifier is maintained. The current compensation module shares partial current through an additional current path when the common mode transient interference (CMTII+ and CMTII-) occurs, so as to prevent the input common mode Voltage (VCM) from being too high or too low and ensure the input voltage of the first differential amplifier to be stable.
The invention ensures that the signal keeps very low transmission delay under normal transmission and low common mode transient interference; under high common mode transient interference, CMTI of the circuit is improved by sacrificing a portion of the transmission delay.
Drawings
In order that the invention may be more readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof that are illustrated in the appended drawings.
Fig. 1 is a schematic diagram of an isolated drive receiver circuit according to the present invention.
Fig. 2 is a block diagram of a first differential amplifier and current compensation module of the present invention.
Fig. 3 is a block diagram of a common mode transient detection module of the present invention.
Fig. 4 is a block diagram of a pulse mask module of the present invention.
Fig. 5 is a waveform diagram of the common mode transient signal transmission of the present invention.
Description of the specification reference numerals:
100. A modulation transmitting module; 200. an isolation capacitor; 300. a first differential amplifier; 400. a second differential amplifier; 500. a current compensation module; 600. a demodulation module; 700. a common mode transient detection module; 800. a pulse shielding module.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and specific examples, which are not intended to be limiting, so that those skilled in the art will better understand the invention and practice it.
In the present invention, if directions (up, down, left, right, front and rear) are described, they are merely for convenience of description of the technical solution of the present invention, and do not indicate or imply that the technical features must be in a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
In the present invention, "a plurality of" means one or more, and "a plurality of" means two or more, and "greater than", "less than", "exceeding", etc. are understood to not include the present number; "above", "below", "within" and the like are understood to include this number. In the description of the present invention, the description of "first" and "second" if any is used solely for the purpose of distinguishing between technical features and not necessarily for the purpose of indicating or implying a relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the present invention, unless clearly defined otherwise, terms such as "disposed," "mounted," "connected," and the like should be construed broadly and may be connected directly or indirectly through an intermediate medium, for example; the connecting device can be fixedly connected, detachably connected and integrally formed; can be mechanically connected, electrically connected or capable of communicating with each other; may be a communication between two elements or an interaction between two elements. The specific meaning of the words in the invention can be reasonably determined by a person skilled in the art in combination with the specific content of the technical solution.
Referring to fig. 1, an isolation driving receiving circuit for improving common mode transient immunity of the present invention is applied to an isolation chip, and includes: the device comprises a modulation transmitting module 100, an isolation capacitor 200, a first differential amplifier 300, a second differential amplifier 400, a current compensation module 500, a demodulation module 600, a common mode transient detection module 700 and a pulse shielding module 800;
The modulation transmitting module 100 is configured to convert an input single-ended signal into a high-frequency differential carrier signal;
The input end of the first differential amplifier 300 is connected with the output end of the modulation transmitting module 100 through the isolation capacitor 200, the output end of the first differential amplifier 300 is connected with the input end of the second differential amplifier 400, and the differential carrier signal passes through the isolation capacitor 200 and then sequentially passes through the first differential amplifier 300 and the second differential amplifier 400 for amplification;
The current compensation module 500 is connected to the first differential amplifier 300 and is configured to provide a compensation current to the first differential amplifier 300 when the chip experiences a low-to-high common mode transient disturbance; and reducing the current input to the first differential amplifier 300 to reduce the input common mode voltage of the first differential amplifier 300 when the chip experiences high-to-low common mode transient disturbances;
the input and output terminals of the demodulation module 600 are connected to the output terminal of the second differential amplifier 400 and the input terminal of the pulse mask module 800,
The demodulation module 600 is configured to demodulate the output signal of the second differential amplifier 400, and convert the output signal into a single-ended input signal of the transmitting end;
the input end of the pulse shielding module 800 is connected with the output end of the demodulation module 600, and the pulse shielding module 800 is also connected with the isolation capacitor 200 through the common mode transient detection module 700;
The common mode transient detection module 700 is configured to generate a control signal according to the detected common mode transient interference signal, and the pulse mask module 800 is capable of receiving the control signal and controlling a transmission mask delay through switching.
Through the arrangement, the current compensation module 500 can optimize the influence of common mode current generated temporarily by common mode transient interference on the receiving end; the common mode transient detection module 700 detects common mode transient interference and generates a control signal; the pulse mask module 800 receives the control signal of the common mode transient detection module 700, and controls the transmission mask delay through switching to improve the Common Mode Transient Immunity (CMTI) of the chip.
In one embodiment, the modulation transmission module 100 employs OOK (On-Off Keying) modulation. The signal is not transmitted at low level, the signal is transmitted at high level, and the input single-ended signal is converted into a high-frequency differential carrier signal; the common mode rejection ratio of the signals can be improved to some extent using differential signaling.
The first differential amplifier 300 is capable of amplifying the high frequency carrier signal passing through the isolation capacitor 200; the second differential amplifier 400 amplifies the output signal of the first differential amplifier 300 again; the demodulation module 600 demodulates the output signal of the second differential amplifier 400, and converts the output signal into a single-ended input signal at the transmitting end.
It should be noted that, if the chip experiences low-to-high common mode transient interference (cmti+), at this time, the transmitting end (TX) will draw current to the receiving end first differential amplifier 300 through the isolation capacitor 200, and the current compensation module 500 is turned on to open a branch to provide current;
If the chip experiences high-to-low common mode transient interference (CMTI "), at this time, the transmitting end will sink current into the receiving end first differential amplifier 300, the current compensation module 500 is turned on, a bleed-off branch is provided, the current flowing into the input resistor of the first differential amplifier 300 is reduced, the input common mode voltage is reduced, and the input common mode Voltage (VCM) of the first differential amplifier 300 is prevented from being too high, so that the first differential amplifier 300 cannot work normally.
In one embodiment, referring to fig. 2, the first differential amplifier 300 includes an NMOS transistor M3, an NMOS transistor M4, an NMOS transistor M5, an NMOS transistor M6, a resistor RCM1, and a resistor RCM2;
The drains of the NMOS tube M5 and the NMOS tube M6 are correspondingly connected with the grid of the NMOS tube M and are respectively connected to the power supply voltage VDD;
The source electrode of the NMOS tube M5 is connected to the differential signal input end V1-, and the source electrode of the NMOS tube M6 is connected to the differential signal input end V1+;
the drains of the NMOS tube M3 and the NMOS tube M4 are respectively connected with common mode signal input ends V < 2+ > and V < 2 > -and are connected to a power supply voltage VDD through loads;
the grid electrode of the NMOS tube M3 is connected to the grid electrode of the NMOS tube M5, and the source electrode of the NMOS tube M3 is connected to the differential signal input end V1+;
the grid electrode of the NMOS tube M4 is connected to the grid electrode of the NMOS tube M6, and the source electrode of the NMOS tube M4 is connected to the differential signal input end V1-;
The differential signal input terminal v1+ is grounded to the ground terminal GND through the resistor RCM 1;
the differential signal input terminal V1 is grounded to the ground GND through the resistor RCM 2.
Through the above arrangement, the first differential amplifier 300 adopts the fully differential gate cross-coupling method, and since the common gate input-output has no miller capacitance, the structure is more suitable for the application of a high-bandwidth circuit to transmit Gao Pingzai wave signals at the transmitting end; meanwhile, the fully differential structure has certain inhibition capability on common mode signals, so that common mode transients generated by a chip can be inhibited by the circuit structure before the common mode transient detection circuit is started. Therefore, the structure of the fully differential cross-coupled common gate circuit has the advantages of high bandwidth, high common mode rejection and the like. The second differential amplifier 400 may then take a similar structure as the first differential amplifier 300.
In one embodiment, referring to FIG. 2, the current compensation module 500 includes a first compensation module and a second compensation module;
the first compensation module comprises an NMOS tube M0, a resistor R1 and a resistor R2;
The drain electrode and the source electrode of the NMOS tube M0 are respectively connected to a differential signal input end V1+ and a ground end GND of the first differential amplifier 300, the grid electrode of the NMOS tube M0 is connected between one end of a resistor R1 and one end of a resistor R2, the other end of the resistor R1 is grounded, and the other end of the resistor R2 is connected with the differential signal input end V1+;
the second compensation module comprises an NMOS tube M1, a resistor R3 and a resistor R4;
The drain and the source of the NMOS transistor M1 are respectively connected to the differential signal input terminal V1-and the ground terminal GND of the first differential amplifier 300, the gate of the NMOS transistor M1 is connected between one end of the resistor R3 and one end of the resistor R4, the other end of the resistor R3 is grounded, and the other end of the resistor R4 is connected to the differential signal input terminal V1-.
The differential signal passing through the isolation capacitor 200 enters from the differential signal input terminal v1+ and the differential signal input terminal V1-,
The NMOS tube M0, the NMOS tube M1, the resistor R2, the resistor R3 and the resistor R4 form a current compensation structure, when the common mode transient interference CMTI+ comes, the V+ and V-ends draw current from the ground end GND, at the moment, the V1+ and V1-draw current from the resistor RCM1 and the resistor RCM2, and partial current is also drawn from two paths of the NMOS tube M0 and the NMOS tube M1, so that the voltage of the V1+ and the V1-is relieved, and the excessive negative change of the V1+ and the V1-is prevented.
When the common mode transient interference CMTI-, v+ and V-sink current to the ground terminal GND, at this time, the two branches of the NMOS tube M0 and the NMOS tube M1 share part of the current, so as to prevent the common mode current from being too large, resulting in too high input common mode voltage VCM, and ensure that the first differential amplifier 300 can work normally.
In one embodiment, referring to FIG. 3, the common mode transient detection module 700 includes a first comparator, a second comparator, an OR gate, and an inverter;
the output end of each of the first comparator and the second comparator is connected to the input end of the OR gate, and the output end of the OR gate is connected to the output end of the inverter.
The input common-mode voltage of the first differential amplifier 300 is respectively connected with the non-inverting input end of the first comparator and the inverting input end of the second comparator, the inverting input end of the first comparator is connected with a fixed positive value vref+, and the non-inverting input end of the second comparator is connected with a fixed negative value vref-.
The common mode transient detection module 700 is capable of detecting a common mode Voltage (VCM) generated by common mode transient disturbance signals (cmti+ and CMTI-) and comparing the common mode Voltage (VCM) with two positive and negative reference voltages by a comparator; if the circuit experiences CMTII+, and VCM is a negative value, comparing with the negative reference voltage (vref-) of the comparator, and outputting a high level when the voltage is smaller than the negative reference voltage; the circuit experiences CMTI-, when VCM is positive, and the comparator outputs a high level when it is greater than the positive reference voltage (vref +) compared to the positive reference voltage (vref +).
The output of the two comparators is high as long as one of the outputs is high, and the control signal output by the module is high, which represents that the common mode transient interference signal is detected.
In operation, when the common mode transient disturbance signal CMTI+ is coming, the common mode voltage VCM becomes negative, and the larger CMTI+ is, the more negative the VCM is. vref-is a fixed negative value representing the VCM value at CMTI+1 (e.g. + 100V/ns). When VCM is less than vref-, the comparator outputs a high level.
When the common mode transient disturbance signal CMTI-comes, the VCM will become positive and the larger the CMTI-the more positive the VCM. vref+ is a fixed positive value representing the VCM value at CMTI-1 (e.g., -100V/ns). When VCM is greater than vref+, the comparator outputs a high level.
In the signal transmission process, as long as one of the two comparators outputs a high level, V_detect+ outputs a high level, and V_detect-outputs a low level; otherwise, the opposite signal is output.
In one embodiment, referring to fig. 4, the pulse shielding module 800 includes an NMOS transistor M7, an NMOS transistor M8, an NMOS transistor M9, an NMOS transistor M10, an NMOS transistor M11, an NMOS transistor M12, an NMOS transistor M13, an NMOS transistor M14, an NMOS transistor M15, a PMOS transistor M0, a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M3, a PMOS transistor M4, a PMOS transistor M5, and a PMOS transistor M6;
the source electrodes of the NMOS tube M7, the NMOS tube M8, the NMOS tube M10, the NMOS tube M11, the NMOS tube M12 and the NMOS tube M14 are grounded to the GND;
the grid electrode of the NMOS tube M7 is respectively connected with the drain electrode of the NMOS tube M8 and the grid electrode of the NMOS tube M;
the source electrode of the NMOS tube M9 is connected with the drain electrode of the NMOS tube M8, and the grid electrode of the NMOS tube M9 is connected with a high level V_detect+;
the grid electrode of the NMOS tube M10 is respectively connected with the drain electrode of the NMOS tube M11 and the grid electrode of the NMOS tube M12;
the drain electrode of the NMOS tube M12 is connected with the source electrode of the NMOS tube M13;
the drain electrode of the NMOS tube M14 is connected with the source electrode of the NMOS tube M15, and the grid electrode of the NMOS tube M14 is connected with a high level V_detect+;
The sources of the PMOS tube P0, the PMOS tube P1, the PMOS tube P2, the PMOS tube P3 and the PMOS tube P6 are respectively connected with the power supply voltage VDD;
The drain electrode of the PMOS tube P0 is respectively connected with the grid electrode of the PMOS tube P0, the drain electrode of the NMOS tube M9 and the grid electrode of the PMOS tube P1;
The drain electrode of the PMOS tube P1 is connected with the drain electrode of the NMOS tube M10;
The drain electrode of the PMOS tube P2 is respectively connected with the grid electrode of the PMOS tube P2, the drain electrode of the NMOS tube M11 and the grid electrode of the PMOS tube P3;
the drain electrode of the PMOS tube P3 is connected with the source electrode of the PMOS tube P4;
The drain electrode of the PMOS tube P4 is connected with the drain electrode of the NMOS tube M13, and the grid electrode of the PMOS tube P4 is connected with the grid electrode of the NMOS tube M13;
the grid electrode of the PMOS tube P6 is connected with a high level V_detect+, and the drain electrode of the PMOS tube P6 is connected with the source electrode of the PMOS tube P5;
The drain electrode of the PMOS tube P5 is connected with the drain electrode of the NMOS tube M15, and the grid electrode of the PMOS tube P5 is connected with the grid electrode of the NMOS tube M15;
the demodulated output signal cmp_out is connected between the gate of the PMOS transistor P4 and the gate of the NMOS transistor M13, and between the gate of the PMOS transistor P5 and the gate of the NMOS transistor M15, respectively.
Specifically, the capacitor further includes a capacitor c_blank, one end of the capacitor c_blank is connected between the drain of the PMOS transistor P4 and the drain of the NMOS transistor M13, and between the drain of the PMOS transistor P5 and the drain of the NMOS transistor M15, and the other end is grounded to the ground GND.
Specifically, the circuit also comprises a schmitt trigger, a first inverter unit and a second inverter unit which are sequentially connected with one end of the capacitor C_blank, wherein the second inverter unit outputs a pulse shielding signal V_blank.
When the pulse shielding module 800 normally transmits signals, only small delay is generated on the demodulated signals, when the common mode transient state module detects common mode transient state interference signals, the output control signals start to switch the delay of the circuit, a new delay branch is opened, the delay branch in normal transmission is closed, and the shielding time in common mode transient state interference is increased.
V_detect+ is low and V_detect-is high during normal signal transmission and low common mode transient interference; at this time, the NMOS tube M9 is turned off, no current flows through the NMOS tube M10, and the PMOS tube P3 and the NMOS tube M12 are turned off; the NMOS transistor M14 and the PMOS transistor P6 are turned on, the demodulated output signal cmp_out is transmitted through the NMOS transistor M15 and the PMOS transistor P12, the circuits I1 and I0 of the branch are large enough, and the time for charging the capacitor c_blank is short, so that the demodulated signal can be transmitted to the output stage with low delay under normal transmission or low common mode transient interference.
When the chip experiences high common mode transient interference, V_detect+ is high level, and V_detect-is low level; at this time, the NMOS transistor M14 and the PMOS transistor P6 are turned off, the NMOS transistor M9 is turned on, the NMOS transistor M10, the NMOS transistor M12 and the PMOS transistor P3 have currents flowing therethrough, the demodulated output signal cmp_out is transmitted through the NMOS transistor M13 and the PMOS transistor P4, the currents of the NMOS transistor M12 and the PMOS transistor P3 can be regulated by the sizes of the dimensional ratios M and n, and the delay time required to bear the maximum CNMOS transistor MTI is controlled, wherein the currents of the NMOS transistor M12 and the PMOS transistor P3 are smaller than the currents of I1 and I2.
The circuit can ensure that the chip can normally transmit signals under low CMTIs (for example, less than 80V/ns) by setting proper current capability of the output stage of the transmitting end (because the receiving end draws current from the transmitting end when the CMTIs are experienced, if the current is too large, the current capability of the output stage of the transmitting end is insufficient to transmit abnormal carrier signals), a special first differential amplifier 300 structure and a current compensation module 500 when the common mode transient interference is low; when CMTI is high, enough masking time is added and signal transmission is normal.
Referring to fig. 5, a waveform diagram during common mode transient signal transmission is shown, and it can be seen from the diagram that when signals are normally transmitted, when the common mode transient is high, a demodulated waveform is turned over by mistake, and at this time, a pulse shielding circuit starts to switch delay time, and the time of the false turning over is shielded; when the common mode transient state is low and the signal is normally transmitted, the pulse shielding circuit switches the low-delay branch circuit, and the transmission delay between the output waveform and the input waveform is kept low.
Therefore, the isolation driving receiving circuit can enable signals to keep low-delay transmission signals under normal transmission and low common mode transient interference; under high common mode transient interference, CMTI of the circuit is improved by sacrificing a portion of the transmission delay.
Finally, it should be noted that the above-mentioned embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention, and all such modifications and equivalents are intended to be encompassed in the scope of the claims of the present invention.
Claims (9)
1. An isolation driving receiving circuit for improving common mode transient immunity, which is applied to an isolation chip, is characterized by comprising: the device comprises a modulation transmitting module, an isolation capacitor, a first differential amplifier, a second differential amplifier, a current compensation module, a demodulation module, a common mode transient detection module and a pulse shielding module;
the modulation transmitting module is used for converting an input single-ended signal into a high-frequency differential carrier signal;
The input end of the first differential amplifier is connected with the output end of the modulation transmitting module through the isolation capacitor, the output end of the first differential amplifier is connected with the input end of the second differential amplifier, and the differential carrier signal sequentially passes through the first differential amplifier and the second differential amplifier for amplification after passing through the isolation capacitor;
The current compensation module is connected with the first differential amplifier and is used for providing compensation current for the first differential amplifier when the chip experiences common mode transient interference from low to high; and reducing the current input to the first differential amplifier to reduce the input common mode voltage of the first differential amplifier when the chip experiences high-to-low common mode transient disturbances;
The input end and the output end of the demodulation module are respectively connected with the output end of the second differential amplifier and the input end of the pulse shielding module,
The demodulation module is used for demodulating the output signal of the second differential amplifier and converting the output signal into a single-ended input signal of the transmitting end;
The input end of the pulse shielding module is connected with the output end of the demodulation module, and the pulse shielding module is also connected with the isolation capacitor through the common mode transient detection module;
the common mode transient detection module is used for generating a control signal according to the detected common mode transient interference signal, and the pulse shielding module can receive the control signal and control transmission shielding delay through switching.
2. The isolated drive receive circuit of claim 1, wherein the modulation transmit module employs OOK modulation.
3. The isolated drive receiving circuit for improving common mode transient immunity according to claim 1, wherein the first differential amplifier comprises an NMOS transistor M3, an NMOS transistor M4, an NMOS transistor M5, an NMOS transistor M6, a resistor RCM1, a resistor RCM2;
The drains of the NMOS tube M5 and the NMOS tube M6 are correspondingly connected with the grid of the NMOS tube M and are respectively connected to the power supply voltage VDD;
The source electrode of the NMOS tube M5 is connected to the differential signal input end V1-, and the source electrode of the NMOS tube M6 is connected to the differential signal input end V1+;
the drains of the NMOS tube M3 and the NMOS tube M4 are respectively connected with common mode signal input ends V < 2+ > and V < 2 > -and are connected to a power supply voltage VDD through loads;
the grid electrode of the NMOS tube M3 is connected to the grid electrode of the NMOS tube M5, and the source electrode of the NMOS tube M3 is connected to the differential signal input end V1+;
the grid electrode of the NMOS tube M4 is connected to the grid electrode of the NMOS tube M6, and the source electrode of the NMOS tube M4 is connected to the differential signal input end V1-;
The differential signal input terminal v1+ is grounded to the ground terminal GND through the resistor RCM 1;
the differential signal input terminal V1 is grounded to the ground GND through the resistor RCM 2.
4. The isolated drive receive circuit of claim 1, wherein the current compensation module comprises a first compensation module and a second compensation module;
the first compensation module comprises an NMOS tube M0, a resistor R1 and a resistor R2;
The drain electrode and the source electrode of the NMOS tube M0 are respectively connected to a differential signal input end V1+ and a ground end GND of the first differential amplifier, the grid electrode of the NMOS tube M0 is connected between one end of a resistor R1 and one end of a resistor R2, the other end of the resistor R1 is grounded, and the other end of the resistor R2 is connected with the differential signal input end V1+;
the second compensation module comprises an NMOS tube M1, a resistor R3 and a resistor R4;
The drain electrode and the source electrode of the NMOS tube M1 are respectively connected to a differential signal input end V1-and a ground end GND of the first differential amplifier, the grid electrode of the NMOS tube M1 is connected between one end of a resistor R3 and one end of a resistor R4, the other end of the resistor R3 is grounded, and the other end of the resistor R4 is connected with the differential signal input end V1-.
5. The isolated drive receive circuit of claim 1 or 4, wherein the common mode transient detection module comprises a first comparator, a second comparator, an or gate, and an inverter;
the output end of each of the first comparator and the second comparator is connected to the input end of the OR gate, and the output end of the OR gate is connected to the output end of the inverter.
6. The isolated drive receiving circuit according to claim 5, wherein the input common-mode voltage of the first differential amplifier is connected to the non-inverting input terminal of the first comparator and the inverting input terminal of the second comparator, respectively, the inverting input terminal of the first comparator is connected to a fixed positive value vref+ and the non-inverting input terminal of the second comparator is connected to a fixed negative value vref-.
7. The isolation driving receiving circuit for improving the common mode transient immunity according to claim 1, wherein the pulse shielding module comprises an NMOS tube M7, an NMOS tube M8, an NMOS tube M9, an NMOS tube M10, an NMOS tube M11, an NMOS tube M12, an NMOS tube M13, an NMOS tube M14, an NMOS tube M15, a PMOS tube M0, a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, a PMOS tube M5, and a PMOS tube M6;
the source electrodes of the NMOS tube M7, the NMOS tube M8, the NMOS tube M10, the NMOS tube M11, the NMOS tube M12 and the NMOS tube M14 are grounded to the GND;
the grid electrode of the NMOS tube M7 is respectively connected with the drain electrode of the NMOS tube M8 and the grid electrode of the NMOS tube M;
the source electrode of the NMOS tube M9 is connected with the drain electrode of the NMOS tube M8, and the grid electrode of the NMOS tube M9 is connected with a high level V_detect+;
the grid electrode of the NMOS tube M10 is respectively connected with the drain electrode of the NMOS tube M11 and the grid electrode of the NMOS tube M12;
the drain electrode of the NMOS tube M12 is connected with the source electrode of the NMOS tube M13;
the drain electrode of the NMOS tube M14 is connected with the source electrode of the NMOS tube M15, and the grid electrode of the NMOS tube M14 is connected with a high level V_detect+;
The sources of the PMOS tube P0, the PMOS tube P1, the PMOS tube P2, the PMOS tube P3 and the PMOS tube P6 are respectively connected with the power supply voltage VDD;
The drain electrode of the PMOS tube P0 is respectively connected with the grid electrode of the PMOS tube P0, the drain electrode of the NMOS tube M9 and the grid electrode of the PMOS tube P1;
The drain electrode of the PMOS tube P1 is connected with the drain electrode of the NMOS tube M10;
The drain electrode of the PMOS tube P2 is respectively connected with the grid electrode of the PMOS tube P2, the drain electrode of the NMOS tube M11 and the grid electrode of the PMOS tube P3;
the drain electrode of the PMOS tube P3 is connected with the source electrode of the PMOS tube P4;
The drain electrode of the PMOS tube P4 is connected with the drain electrode of the NMOS tube M13, and the grid electrode of the PMOS tube P4 is connected with the grid electrode of the NMOS tube M13;
the grid electrode of the PMOS tube P6 is connected with a high level V_detect+, and the drain electrode of the PMOS tube P6 is connected with the source electrode of the PMOS tube P5;
The drain electrode of the PMOS tube P5 is connected with the drain electrode of the NMOS tube M15, and the grid electrode of the PMOS tube P5 is connected with the grid electrode of the NMOS tube M15;
the demodulated output signal cmp_out is connected between the gate of the PMOS transistor P4 and the gate of the NMOS transistor M13, and between the gate of the PMOS transistor P5 and the gate of the NMOS transistor M15, respectively.
8. The isolated driving receiver circuit according to claim 7, further comprising a capacitor c_blank, wherein one end of the capacitor c_blank is connected between the drain of the PMOS transistor P4 and the drain of the NMOS transistor M13, and between the drain of the PMOS transistor P5 and the drain of the NMOS transistor M15, respectively, and the other end is grounded to GND.
9. The isolated drive receiving circuit for improving common mode transient immunity according to claim 8, further comprising a schmitt trigger, a first inverter unit and a second inverter unit connected in sequence with one end of the capacitor c_blank, wherein the output of the second inverter unit is a pulse shielding signal v_blank.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104319996A (en) * | 2014-10-30 | 2015-01-28 | 武汉大学 | Synchronous rectification step-down converter chip with high-precision current detection function |
| CN111446935A (en) * | 2020-05-20 | 2020-07-24 | 苏州纳芯微电子股份有限公司 | Differential signal amplifying circuit, digital isolator and digital receiver |
| CN112947182A (en) * | 2021-02-05 | 2021-06-11 | 电子科技大学 | Control circuit for improving common-mode transient anti-interference degree of negative transconductance oscillator |
| CN113067567A (en) * | 2021-03-31 | 2021-07-02 | 江苏中科汉韵半导体有限公司 | Ultrahigh-voltage insulation isolation SiC MOSFET gate drive circuit |
| CN114050818A (en) * | 2021-10-11 | 2022-02-15 | 北京芯可鉴科技有限公司 | Digital isolator and chip |
| CN115314011A (en) * | 2022-08-30 | 2022-11-08 | 成都振芯科技股份有限公司 | Amplifier with feedforward compensation |
| CN116015276A (en) * | 2022-12-26 | 2023-04-25 | 浙江大学 | Digital capacitance isolator |
| US20240039769A1 (en) * | 2022-07-27 | 2024-02-01 | Kinetic Technologies International Holdings Lp | Systems and methods for improving common mode transient immunity in silicon digital isolators using capacitive barrier for galvanic isolation |
-
2024
- 2024-07-25 CN CN202411002186.4A patent/CN118554894B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104319996A (en) * | 2014-10-30 | 2015-01-28 | 武汉大学 | Synchronous rectification step-down converter chip with high-precision current detection function |
| CN111446935A (en) * | 2020-05-20 | 2020-07-24 | 苏州纳芯微电子股份有限公司 | Differential signal amplifying circuit, digital isolator and digital receiver |
| CN112947182A (en) * | 2021-02-05 | 2021-06-11 | 电子科技大学 | Control circuit for improving common-mode transient anti-interference degree of negative transconductance oscillator |
| CN113067567A (en) * | 2021-03-31 | 2021-07-02 | 江苏中科汉韵半导体有限公司 | Ultrahigh-voltage insulation isolation SiC MOSFET gate drive circuit |
| CN114050818A (en) * | 2021-10-11 | 2022-02-15 | 北京芯可鉴科技有限公司 | Digital isolator and chip |
| US20240039769A1 (en) * | 2022-07-27 | 2024-02-01 | Kinetic Technologies International Holdings Lp | Systems and methods for improving common mode transient immunity in silicon digital isolators using capacitive barrier for galvanic isolation |
| CN115314011A (en) * | 2022-08-30 | 2022-11-08 | 成都振芯科技股份有限公司 | Amplifier with feedforward compensation |
| CN116015276A (en) * | 2022-12-26 | 2023-04-25 | 浙江大学 | Digital capacitance isolator |
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