CN114050818A - Digital isolator and chip - Google Patents
Digital isolator and chip Download PDFInfo
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- CN114050818A CN114050818A CN202111182262.0A CN202111182262A CN114050818A CN 114050818 A CN114050818 A CN 114050818A CN 202111182262 A CN202111182262 A CN 202111182262A CN 114050818 A CN114050818 A CN 114050818A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
Abstract
The invention relates to the technical field of isolators, and provides a digital isolator and a chip. The digital isolator includes: the modulation transmitting module is used for converting the received input signal into a fully differential signal; the isolation capacitor module is connected with the modulation sending module and used for transmitting the fully differential signal; the active common-mode filtering module is connected with the isolation capacitor module and is used for filtering common-mode transient pulses in the process that the isolation capacitor module transmits the fully differential signals; and the receiving demodulation module is connected with the isolation capacitor module and used for demodulating and outputting the fully differential signal after the common-mode transient pulse is filtered. According to the invention, the modulation sending module is used for converting the input signal into the fully differential signal, and the active common mode filtering module is used for filtering the common mode transient pulse in the fully differential signal transmission process, so that the common mode transient pulse suppression capability of the digital isolator is improved.
Description
Technical Field
The invention relates to the technical field of isolators, in particular to a digital isolator and a chip.
Background
Digital isolators can be classified into optical isolators, magnetic isolators, and capacitive isolators, depending on the isolation medium. The capacitive isolator adopts a capacitive isolation technology, can be well compatible with a standard CMOS (complementary metal oxide semiconductor) process, and has the advantages of high transmission rate, low time delay, long service life, high voltage resistance and the like.
In general, a capacitive isolator includes a transmitting end (i.e., a modulation module), a receiving end (i.e., a demodulation module), and an isolation capacitance module. The transmitting end modulates the transmission signal into a signal which can pass through the isolation capacitor module, and the receiving end demodulates the signal which passes through the isolation capacitor module into the transmission signal. The isolation capacitor module is connected with the sending end and the receiving end.
Common Mode Transient Immunity (CMTI) is one of the important indicators of digital isolators. The common mode transient immunity CMTI represents the ability of the isolator to withstand rapid changes in the potential difference between its grounds, i.e., without causing bit errors when the common mode changes rapidly. A high common mode transient immunity represents a robust isolation channel. Because the sending end and the receiving end of the isolator are in different voltage domains, signals are transmitted from the voltage domain of the sending end to the voltage domain of the receiving end, common-mode transient pulses can be generated at the receiving end, different voltage rising rates can generate common-mode transient pulses with different sizes, the common-mode transient pulses generate the influence of a common-mode slip mode at the receiving end, and the receiving end misjudgment is caused. To avoid false determination, the common mode transient pulse suppression capability of the isolator needs to be improved.
Disclosure of Invention
The invention aims to provide a digital isolator to improve the common-mode transient pulse suppression capability of the digital isolator.
In order to achieve the above object, the present invention provides a digital isolator comprising:
the modulation transmitting module is used for converting the received input signal into a fully differential signal;
the isolation capacitor module is connected with the modulation sending module and used for transmitting the fully differential signal;
the active common-mode filtering module is connected with the isolation capacitor module and is used for filtering common-mode transient pulses in the process that the isolation capacitor module transmits the fully differential signals;
and the receiving demodulation module is connected with the isolation capacitor module and used for demodulating and outputting the fully differential signal after the common-mode transient pulse is filtered.
Further, the active common mode filtering module includes: the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor, a first PMOS transistor and a second PMOS transistor; the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the first NMOS tube is connected with the source electrode of the first PMOS tube and is grounded, the source electrode of the second NMOS tube is connected with the source electrode of the second PMOS tube and is grounded, and the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube.
Further, the isolation capacitor module comprises a first isolation capacitor and a second isolation capacitor; the drain electrode of the first NMOS tube is connected with the negative electrode of the first isolation capacitor, the grid electrode of the first NMOS tube is connected with the drain electrode, and the drain electrode of the second NMOS tube is connected with the negative electrode of the second isolation capacitor; the drain electrode of the first PMOS tube is connected with the negative electrode of the first isolation capacitor, the grid electrode of the first PMOS tube is connected with the drain electrode, and the drain electrode of the second PMOS tube is connected with the negative electrode of the second isolation capacitor.
Further, when the common mode transient pulse output by the first isolation capacitor and the second isolation capacitor is greater than or equal to a threshold voltage: the grid end voltage of the first NMOS tube and the grid end voltage of the second NMOS tube are greater than or equal to threshold voltage, the first NMOS tube and the second NMOS tube are conducted, and the common mode transient pulse is transmitted to the ground; the absolute value of the gate end voltage of the first PMOS tube and the gate end voltage of the second PMOS tube are larger than or equal to the threshold voltage, the first PMOS tube and the second PMOS tube are conducted, and the common mode transient pulse is transmitted to the ground.
Further, the receiving and demodulating module comprises a preamplifier module, and the preamplifier module comprises a first sampling resistor and a second sampling resistor; the drain electrode and the grid electrode of the first PMOS tube are connected with the positive end of the first sampling resistor, the drain electrode of the second PMOS tube is connected with the positive end of the second sampling resistor, and the negative end of the first sampling resistor and the negative end of the second sampling resistor are grounded.
Further, when there is no common mode transient pulse or the common mode transient pulse output by the first isolation capacitor and the second isolation capacitor is smaller than a threshold voltage: the positive end voltage of the first sampling resistor and the positive end voltage of the second sampling resistor are both smaller than the threshold voltages of the first NMOS tube, the second NMOS tube, the first PMOS tube and the second PMOS tube, and the first NMOS tube, the second NMOS tube, the first PMOS tube and the second PMOS tube are in a cut-off state.
Further, the active common mode filtering module includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor; the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube and the source electrode of the fifth NMOS tube, the drain electrode of the third NMOS tube is connected with the grid electrode of the fifth NMOS tube, and the drain electrode of the fifth NMOS tube is connected to a first power supply end; the source electrode of the third NMOS tube is connected with the source electrode of the third PMOS tube and is grounded, and the source electrode of the fourth NMOS tube is connected with the source electrode of the fourth PMOS tube and is grounded; the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube, the drain electrode of the third PMOS tube is connected with the grid electrode of the fifth PMOS tube, and the drain electrode of the fifth PMOS tube is connected to a second power supply end.
Further, when a common-mode transient pulse is input into the fifth NMOS transistor and a first power supply end inputs gate end voltages of the third NMOS transistor and the fourth NMOS transistor to be greater than a threshold voltage, the third NMOS transistor and the fourth NMOS transistor are turned on, and the common-mode transient pulse is transmitted to the ground; when the common mode transient pulse is input into the fifth PMOS tube and the absolute value of the gate end voltage input into the third PMOS tube and the gate end voltage input into the fourth PMOS tube by the second power supply end is larger than the threshold voltage, the third PMOS tube and the fourth PMOS tube are conducted, and the common mode transient pulse is transmitted to the ground.
Further, the preamplifier module further comprises a positive input end, a negative input end, a sixth NMOS tube, a seventh NMOS tube, a first coupling capacitor, a second coupling capacitor, a first current source load and a second current source load; the positive input end is connected with the negative electrode of a first isolation capacitor of the isolation capacitor module, and the negative input end is connected with the negative electrode of a second isolation capacitor of the isolation capacitor module; the source electrode of the sixth NMOS tube and the positive electrode of the first coupling capacitor are connected with the positive input end, the source electrode of the seventh NMOS tube and the positive electrode of the second coupling capacitor are connected with the negative input end, the grid electrode of the sixth NMOS tube is connected with the negative electrode of the second coupling capacitor, the grid electrode of the seventh NMOS tube is connected with the negative electrode of the first coupling capacitor, the drain electrode of the sixth NMOS tube is connected with the negative end of the first current source load, and the drain electrode of the seventh NMOS tube is connected with the negative end of the second current source load.
Further, the receiving and demodulating module further includes: the envelope comparator is used for demodulating the fully differential signal amplified by the preamplifier module and restoring the fully differential signal into an input signal received by the modulation sending module; and the leading edge blanking circuit is used for eliminating the glitches in the restored input signal.
Further, the modulation transmitting module comprises: the first inverter, the second inverter, the third inverter, the first AND gate, the second AND gate, the first driver and the second driver; the input end of the first phase inverter is connected with the oscillator, and the input end of the second phase inverter is connected with the input signal end; the output end of the first phase inverter and the output end of the second phase inverter are connected with the input end of the first AND gate, the output end of the first AND gate is connected with the input end of the first driver, the input end of the second phase inverter is connected with the input end of the second AND gate through the third phase inverter, the output end of the first phase inverter is connected with the other input end of the second AND gate, the output end of the second AND gate is connected with the input end of the second driver, and the output end of the first driver and the output end of the second driver output full differential signals to the isolation capacitor module.
The invention also provides a chip which comprises the digital isolator.
According to the digital isolator, the modulation and transmission module is used for converting the input signal into the fully differential signal, the active common mode filtering module is used for filtering the common mode transient pulse in the fully differential signal transmission process, and the receiving and demodulation module is used for demodulating the fully differential signal after the common mode transient pulse is filtered, so that the common mode transient pulse suppression capability of the digital isolator is improved.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIG. 1 is a block diagram of a digital isolator provided by an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of an active common mode filter module according to an embodiment of the present invention;
fig. 3 is a circuit diagram of an active common mode filter module according to a second embodiment of the present invention;
fig. 4 is a circuit diagram of a receiving and demodulating module according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a preamplifier circuit of the receiving and demodulating module according to an embodiment of the invention;
fig. 6 is a schematic circuit diagram of a modulation and transmission module according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a CMTI of a digital isolator according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
The terms "first," "second," "third," and the like herein are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance. "connected" as used herein is intended to mean an electrical power connection or a signal connection between two components; "coupled" may be a direct connection between two elements, an indirect connection between two elements through an intermediary (e.g., a wire), or an indirect connection between three elements.
FIG. 1 is a block diagram of a digital isolator provided by an embodiment of the present invention. As shown in fig. 1, the digital isolator according to the embodiment of the present invention includes: the device comprises a modulation transmitting module, an isolation capacitor module, an active common mode filtering module and a receiving and demodulating module. The modulation transmitting module is used for converting an input signal into a fully differential signal. The isolation capacitor module is connected with the modulation sending module and used for transmitting the fully differential signal. The active common mode filtering module is connected with the isolation capacitor module and is used for filtering common mode transient pulses in the process that the isolation capacitor module transmits the fully differential signals. And the receiving demodulation module is connected with the isolation capacitor module and used for demodulating and outputting the fully differential signal after the common-mode transient pulse is filtered.
Example one
Fig. 2 is a circuit diagram of an active common mode filter module according to an embodiment of the present invention. As shown in fig. 2, the active common mode filter module of this embodiment includes: a first NMOS transistor NM1, a second NMOS transistor NM2, a first PMOS transistor PM1, and a second PMOS transistor PM 2. The grid of the first NMOS transistor NM1 is connected with the grid of the second NMOS transistor NM2, the source of the first NMOS transistor NM1 is connected with the source of the first PMOS transistor PM1 and grounded, the source of the second NMOS transistor NM2 is connected with the source of the second PMOS transistor PM2 and grounded, and the grid of the first PMOS transistor PM1 is connected with the grid of the second PMOS transistor PM 2.
Fig. 2 shows a circuit configuration of an isolation capacitance module including a first isolation capacitance C1 and a second isolation capacitance C2. The first isolation capacitor C1 and the second isolation capacitor C2 utilize the intermetallic parasitic capacitance to provide high withstand voltage through the intermetallic medium. The drain of the first NMOS transistor NM1 is connected to the negative terminal of the first isolation capacitor C1, the gate of the first NMOS transistor NM1 is connected to the drain thereof, and the drain of the second NMOS transistor NM2 is connected to the negative terminal of the second isolation capacitor C2. The drain of the first PMOS transistor PM1 is connected to the cathode of the first isolation capacitor C1, the gate of the first PMOS transistor PM1 is connected to the drain thereof, and the drain of the second PMOS transistor PM2 is connected to the cathode of the second isolation capacitor C2.
The principle of the active common mode filter module provided by this embodiment for suppressing the common mode transient pulse is as follows: when the common mode transient pulse output by the first isolation capacitor C1 and the second isolation capacitor C2 is greater than or equal to a Threshold Voltage Vth (Gate Threshold Voltage, Gate turn-on Voltage of the MOS transistor, also referred to as Threshold Voltage, Threshold Voltage or Threshold Voltage), that is, the common mode transient pulse is greater than or equal to the Threshold Voltage Vth of the first NMOS transistor NM1, the second NMOS transistor NM2, the first PMOS transistor PM1 and the second PMOS transistor PM2, at this time, the Gate terminal voltages of the first NMOS transistor NM1 and the second NMOS transistor NM2 are greater than or equal to the Threshold Voltage, the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned on, the common mode transient pulses output by the first isolation capacitor C1 and the second isolation capacitor C2 are transmitted to the ground in the same direction, and the common mode transient pulse in the process of transmitting the full differential signal by the isolation capacitor module is filtered. In addition, when the common mode transient pulse output by the first isolation capacitor C1 and the second isolation capacitor C2 is greater than or equal to the threshold voltage, the absolute value of the gate terminal voltage of the first PMOS transistor PM1 and the second PMOS transistor PM2 is greater than or equal to the threshold voltage Vth, at this time, the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned on, the common mode transient pulse output by the first isolation capacitor C1 and the second isolation capacitor C2 is transmitted to the ground, and the common mode transient pulse in the process of transmitting the full differential signal by the isolation capacitor module is filtered.
For a clearer description of the principle of the active common mode filter module for suppressing the common mode transient pulse, fig. 2 also shows a partial circuit structure of the preamplifier module of the receiving demodulation module, which includes a first sampling resistor R1 and a second sampling resistor R2. The drain and the gate of the first PMOS transistor PM1 are connected to the positive terminal of the first sampling resistor R1, the drain of the second PMOS transistor PM2 is connected to the positive terminal of the second sampling resistor R2, and the negative terminals of the first sampling resistor R1 and the second sampling resistor R2 are grounded. When there is no common mode transient pulse or the common mode transient pulse output by the first isolation capacitor C1 and the second isolation capacitor C2 is smaller than the threshold voltage, the positive terminal voltage of the first sampling resistor R1 determines the gate bias voltage of the first NMOS transistor NM1 and the first PMOS transistor PM1, and the positive terminal voltage of the second sampling resistor R2 determines the gate bias voltage of the second NMOS transistor NM2 and the second PMOS transistor PM 2. At this time, the positive terminal voltage of the first sampling resistor R1 and the positive terminal voltage of the second sampling resistor R2 are both smaller than the threshold voltages of the first NMOS transistor NM1, the second NMOS transistor NM2, the first PMOS transistor PM1 and the second PMOS transistor PM2, the first NMOS transistor NM1, the second NMOS transistor NM2, the first PMOS transistor PM1 and the second PMOS transistor PM2 are in a cut-off state, and no current passes through the active common mode filtering module. And the MOS tube with specific parameters can be selected to filter specific common mode transient pulse, and if smaller common mode transient pulse is to be filtered, the MOS tube with smaller threshold voltage is selected.
When the active common mode filter module does not work, the fully differential signal output by the isolation capacitor module is directly transmitted to the receiving demodulation module; when the active common mode filter module works, the full differential signal output by the isolation capacitor module is transmitted to the receiving demodulation module after the active common mode filter module filters the common mode transient pulse. The first NMOS transistor NM1 and the second NMOS transistor NM2 of the active common-mode filtering module are structurally symmetrical to the first PMOS transistor PM1 and the second PMOS transistor PM2, common-mode positive pulse signals and common-mode negative pulse signals can be filtered, and meanwhile the influence on parasitic capacitance of input pair transistors of the receiving demodulation module is small.
Fig. 4 is a circuit diagram of a receiving and demodulating module according to an embodiment of the present invention. As shown in fig. 4, the receiving and demodulating module of the present embodiment includes: a preamplifier module PREAMP, an envelope comparator COMP and a leading edge blanking circuit LEB. The input end of the preamplifier module PREAMP is connected with the first isolation capacitor C1 and the second isolation capacitor C2 of the isolation capacitor module, the output end of the preamplifier module PREAMP is connected with the input end of the envelope comparator COMP, and the output end of the envelope comparator COMP is connected with the leading edge blanking circuit LEB. The pre-amplifier module amplifies the fully differential signal transmitted by the isolation capacitor module and outputs the amplified fully differential signal to the envelope comparator; and the envelope comparator demodulates the amplified fully differential signal, restores the demodulated fully differential signal into an input signal received by the modulation transmitting module and outputs the input signal to the leading edge blanking circuit. The leading edge blanking circuit is used for eliminating burrs in the restored input signal.
The envelope comparator COMP is a three-port comparator having two positive input terminals and one negative input terminal. The fully differential signal output by the preamplifier module PREAMP is input to two positive input terminals of the envelope comparator COMP, and the reference voltage Vref is input to a negative input terminal of the envelope comparator COMP. The envelope comparator COMP restores the fully differential signal to the input signal using the OOK modulation and demodulation method.
Fig. 5 is a schematic diagram of a preamplifier circuit of a receiving and demodulating module according to an embodiment of the invention. As shown in fig. 5, the preamplifier module of the present embodiment includes a positive input terminal, a negative input terminal, a sixth NMOS tube NM6, a seventh NMOS tube NM7, a first coupling capacitor C3, a second coupling capacitor C4, a first sampling resistor R1, a second sampling resistor R2, a first current source load L1, and a second current source load L2. The positive input end is connected with the negative electrode of the first isolation capacitor C1 of the isolation capacitor module, and the negative input end is connected with the negative electrode of the second isolation capacitor C2 of the isolation capacitor module. The source of the sixth NMOS transistor NM6, the positive terminal of the first sampling resistor R1, and the positive terminal of the first coupling capacitor C3 are connected to the positive input terminal, the source of the seventh NMOS transistor NM7, the positive terminal of the second sampling resistor R2, and the positive terminal of the second coupling capacitor C4 are connected to the negative input terminal, the gate of the sixth NMOS transistor NM6 is connected to the negative terminal of the second coupling capacitor C4, the gate of the seventh NMOS transistor NM7 is connected to the negative terminal of the first coupling capacitor C3, the drain of the sixth NMOS transistor NM6 is connected to the negative terminal of the first current source load L1, and the drain of the seventh NMOS transistor NM7 is connected to the negative terminal of the second current source load L2. The positive terminal of the first current source load L1 and the positive terminal of the second current source load L2 are connected to a first power supply terminal VDD (not shown in fig. 5), the drain of the sixth NMOS transistor NM6 serves as a positive output terminal VOUT + of the fully differential signal, and the drain of the seventh NMOS transistor NM7 serves as a negative output terminal VOUT-of the fully differential signal.
The fully differential signal is respectively input to the first coupling capacitor C3 and the second coupling capacitor C4, coupled to the seventh NMOS transistor NM7 through the first coupling capacitor C3, and coupled to the sixth NMOS transistor NM6 through the second coupling capacitor C4, and simultaneously, the fully differential signal is directly input to the source of the sixth NMOS transistor NM6 and the source of the seventh NMOS transistor NM 7. The sixth NMOS tube NM6 and the seventh NMOS tube NM7 are used as input gemel tubes, a fully differential grid cross coupling method is adopted, the Bias voltage of the sixth NMOS tube NM6 is provided by the Bias1, the Bias voltage of the seventh NMOS tube NM7 is provided by the Bias2, the equivalent transconductance Gm of the amplifier is doubled, differential mode gain is improved, and meanwhile common mode gain is counteracted. The preamplifier module of the embodiment adopts a fully differential gate cross coupling method to improve the gain and improve the common-mode transient immunity performance of the isolator.
Fig. 6 is a circuit diagram of a modulation transmitting module according to an embodiment of the present invention. As shown in fig. 6, the modulation and transmission module of the present embodiment includes a first inverter U1, a second inverter U2, a third inverter U3, a first and gate M1, a second and gate M2, a first driver D1, and a second driver D2. The input end of the first inverter U1 is connected to the oscillator osc, and the input end of the second inverter U2 is connected to the input signal terminal VIN. The output end of the first inverter U1 and the output end of the second inverter U2 are connected to the input end of the first and gate M1, the output end of the first and gate M1 is connected to the input end of the first driver D1, the input end of the second inverter U2 is connected to the input end of the second and gate M2 through the third inverter U3, the output end of the first inverter U1 is connected to the other input end of the second and gate M2, the output end of the second and gate M2 is connected to the input end of the second driver D2, and the output end (VOUT +) of the first driver D1 and the output end (VOUT-) of the second driver D2 output fully differential signals to the isolation capacitor module.
The modulation sending module adopts an OOK modulation scheme, and simultaneously converts input signals into fully differential signals for transmission, and the fully differential signals can greatly improve the common mode rejection ratio.
FIG. 7 is a schematic diagram of a CMTI of a digital isolator according to an embodiment of the present invention. In fig. 7, VCM represents the excitation of the voltage difference between different voltage domains, VIN represents the input signal, and VOUT represents the output signal. Because the digital isolator is in different voltage domains, signals are transmitted from the voltage domain at one side to the voltage domain at the other side, common-mode transient pulses can be generated at a receiving end, common-mode transient pulses with different sizes can be generated at different voltage rising rates, and the common-mode transient pulses can generate differential mode influence so as to cause error codes and even damage circuits. The VCM is excited with a voltage difference as in fig. 7 to equate to a common mode transient pulse. As shown in fig. 7, when the voltage domain (i.e. the voltage difference excitation VCM) at both ends of the digital isolator rises and falls at a certain rate, the high level signal VIN is input, the output signal VOUT is also at a high level, and the error code of the output signal VOUT is within a required range, i.e. the common mode transient impulse suppresses the voltage domain variation satisfying such a rate, indicating that the digital isolator has good common mode transient immunity.
Example two
In the digital isolator provided in the second embodiment, except for the active common mode filtering module, the modulation and transmission module, the isolation capacitor module, and the receiving and demodulation module are the same as those in the first embodiment, and can be understood by referring to fig. 2, fig. 4, fig. 5, fig. 6, and the corresponding related description and effects in the first embodiment, which are not repeated herein.
Fig. 3 is a circuit diagram of an active common mode filter module according to a second embodiment of the present invention. As shown in fig. 3, the active common mode filter module of this embodiment includes: a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a third PMOS transistor PM3, a fourth PMOS transistor PM4, and a fifth PMOS transistor PM 5. A gate of the third NMOS transistor NM3 is connected to the gate of the fourth NMOS transistor NM4 and the source of the fifth NMOS transistor NM5, a drain of the third NMOS transistor NM3 is connected to the gate of the fifth NMOS transistor NM5, and a drain of the fifth NMOS transistor NM5 is connected to a first power terminal VDD. The source of the third NMOS transistor NM3 is connected to the source of the third PMOS transistor PM3 and grounded, and the source of the fourth NMOS transistor NM4 is connected to the source of the fourth PMOS transistor PM4 and grounded. The gate of the third PMOS transistor PM3 is connected to the gate of the fourth PMOS transistor PM4 and the source of the fifth PMOS transistor PM5, the drain of the third PMOS transistor PM3 is connected to the gate of the fifth PMOS transistor PM5, and the drain of the fifth PMOS transistor PM5 is connected to a second power supply terminal VSS. The gates of the fifth NMOS transistor NM5 and the fifth PMOS transistor PM5 are connected to the isolation capacitor module.
When a common mode transient pulse is input to the fifth NMOS transistor NM5 and a first power terminal VDD is input to gate terminals of the third and fourth NMOS transistors NM3 and NM4 and is greater than a threshold voltage, the third and fourth NMOS transistors NM3 and NM4 are turned on, and the common mode transient pulse is transmitted to ground. When a common mode transient pulse is input to the fifth PMOS transistor PM5, and the absolute value of the gate terminal voltage of the second power supply terminal VSS input to the third PMOS transistor PM3 and the fourth PMOS transistor PM4 is greater than a threshold voltage, the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are conducted, and the common mode transient pulse is transmitted to the ground.
Specifically, when no common-mode transient pulse signal is output from the isolation capacitor module, the positive terminal voltage of the sampling resistor of the preamplifier module determines the gate bias voltage of the fifth NMOS transistor NM5 and the fifth PMOS transistor PM5, and when the positive terminal voltage of the sampling resistor is less than twice the threshold voltage Vth of the NMOS transistor and the PMOS transistor, that is, the gate-source voltages of the fifth NMOS transistor NM5 and the fifth PMOS transistor PM5 are both less than Vth, the preamplifier module is in an off state, and no current passes through the active common-mode filter module. When a common-mode transient positive pulse signal is output from the isolation capacitor module, the grid of the fifth NMOS tube NM5 has a larger positive voltage, the grid-source voltage of the fifth NMOS tube NM5 is greater than Vth, and meanwhile, VDD is connected to the grid-source voltages of the third NMOS tube NM3 and the fourth NMOS tube NM4 and is greater than Vth, so that the third NMOS tube NM3 and the fourth NMOS tube NM4 are conducted, and common-mode large currents output by the isolation capacitor module and having the same size and direction are transmitted to the ground, so that the common-mode transient positive pulse is filtered. When a common-mode transient negative pulse signal is output from the isolation capacitor module, the grid electrode of the fifth PMOS tube PM5 has a large negative voltage, the absolute value of the grid-source voltage of the fifth PMOS tube PM5 is greater than Vth, meanwhile, the absolute value of the grid-end voltage of VSS connected to the third PMOS tube PM3 and the absolute value of the grid-end voltage of the fourth PMOS tube is greater than Vth, the third PMOS tube PM3 and the fourth PMOS tube are conducted, common-mode large currents output by the isolation capacitor module in the same size and direction are transmitted to the ground, and the common-mode transient negative pulse is filtered.
The active common-mode filtering module provided by the second embodiment is suitable for common-mode transient pulse suppression of the digital isolator under the high-frequency working condition.
According to the digital isolator provided by the embodiment of the invention, the input signal is converted into the fully differential signal through the modulation and transmission module, the active common mode filtering module is used for filtering the common mode transient pulse in the transmission process of the fully differential signal, and the receiving and demodulation module is used for demodulating the fully differential signal after the common mode transient pulse is filtered, so that the common mode transient pulse suppression capability of the digital isolator is improved.
The embodiment of the invention also provides a chip which comprises the digital isolator.
While the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solution of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications are within the scope of the embodiments of the present invention. It should be noted that the technical features described in the above embodiments can be combined in any suitable way without contradiction, and should be regarded as the disclosure of the embodiments of the present invention as long as the technical features do not depart from the idea of the embodiments of the present invention.
Claims (12)
1. A digital isolator, comprising:
the modulation transmitting module is used for converting the received input signal into a fully differential signal;
the isolation capacitor module is connected with the modulation sending module and used for transmitting the fully differential signal;
the active common-mode filtering module is connected with the isolation capacitor module and is used for filtering common-mode transient pulses in the process that the isolation capacitor module transmits the fully differential signals;
and the receiving demodulation module is connected with the isolation capacitor module and used for demodulating and outputting the fully differential signal after the common-mode transient pulse is filtered.
2. The digital isolator according to claim 1, wherein the active common mode filtering module comprises: the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor, a first PMOS transistor and a second PMOS transistor;
the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the first NMOS tube is connected with the source electrode of the first PMOS tube and is grounded, the source electrode of the second NMOS tube is connected with the source electrode of the second PMOS tube and is grounded, and the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube.
3. The digital isolator of claim 2, wherein the isolation capacitance module comprises a first isolation capacitance and a second isolation capacitance;
the drain electrode of the first NMOS tube is connected with the negative electrode of the first isolation capacitor, the grid electrode of the first NMOS tube is connected with the drain electrode, and the drain electrode of the second NMOS tube is connected with the negative electrode of the second isolation capacitor;
the drain electrode of the first PMOS tube is connected with the negative electrode of the first isolation capacitor, the grid electrode of the first PMOS tube is connected with the drain electrode, and the drain electrode of the second PMOS tube is connected with the negative electrode of the second isolation capacitor.
4. The digital isolator according to claim 3, wherein when the common mode transient pulse output by the first isolation capacitor and the second isolation capacitor is greater than or equal to a threshold voltage:
the grid end voltage of the first NMOS tube and the grid end voltage of the second NMOS tube are greater than or equal to threshold voltage, the first NMOS tube and the second NMOS tube are conducted, and the common mode transient pulse is transmitted to the ground;
the absolute value of the gate end voltage of the first PMOS tube and the gate end voltage of the second PMOS tube are larger than or equal to the threshold voltage, the first PMOS tube and the second PMOS tube are conducted, and the common mode transient pulse is transmitted to the ground.
5. The digital isolator of claim 3, wherein the receive demodulation module comprises a preamplifier module comprising a first sampling resistor and a second sampling resistor;
the drain electrode and the grid electrode of the first PMOS tube are connected with the positive end of the first sampling resistor, the drain electrode of the second PMOS tube is connected with the positive end of the second sampling resistor, and the negative end of the first sampling resistor and the negative end of the second sampling resistor are grounded.
6. The digital isolator according to claim 5, wherein when there is no common mode transient pulse or the common mode transient pulses output by the first and second isolation capacitors are less than a threshold voltage:
the positive end voltage of the first sampling resistor and the positive end voltage of the second sampling resistor are both smaller than the threshold voltages of the first NMOS tube, the second NMOS tube, the first PMOS tube and the second PMOS tube, and the first NMOS tube, the second NMOS tube, the first PMOS tube and the second PMOS tube are in a cut-off state.
7. The digital isolator according to claim 1, wherein the active common mode filtering module comprises: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor;
the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube and the source electrode of the fifth NMOS tube, the drain electrode of the third NMOS tube is connected with the grid electrode of the fifth NMOS tube, and the drain electrode of the fifth NMOS tube is connected to a first power supply end;
the source electrode of the third NMOS tube is connected with the source electrode of the third PMOS tube and is grounded, and the source electrode of the fourth NMOS tube is connected with the source electrode of the fourth PMOS tube and is grounded;
the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube, the drain electrode of the third PMOS tube is connected with the grid electrode of the fifth PMOS tube, and the drain electrode of the fifth PMOS tube is connected to a second power supply end.
8. The digital isolator of claim 7,
when a common mode transient pulse is input into the fifth NMOS tube and gate end voltages input into the third NMOS tube and the fourth NMOS tube by a first power supply end are larger than a threshold voltage, the third NMOS tube and the fourth NMOS tube are conducted, and the common mode transient pulse is transmitted to the ground;
when the common mode transient pulse is input into the fifth PMOS tube and the absolute value of the gate end voltage input into the third PMOS tube and the gate end voltage input into the fourth PMOS tube by the second power supply end is larger than the threshold voltage, the third PMOS tube and the fourth PMOS tube are conducted, and the common mode transient pulse is transmitted to the ground.
9. The digital isolator according to claim 5, wherein the preamplifier module further comprises a positive input terminal, a negative input terminal, a sixth NMOS transistor, a seventh NMOS transistor, a first coupling capacitor, a second coupling capacitor, a first current source load, and a second current source load;
the positive input end is connected with the negative electrode of a first isolation capacitor of the isolation capacitor module, and the negative input end is connected with the negative electrode of a second isolation capacitor of the isolation capacitor module;
the source electrode of the sixth NMOS tube and the positive electrode of the first coupling capacitor are connected with the positive input end, the source electrode of the seventh NMOS tube and the positive electrode of the second coupling capacitor are connected with the negative input end, the grid electrode of the sixth NMOS tube is connected with the negative electrode of the second coupling capacitor, the grid electrode of the seventh NMOS tube is connected with the negative electrode of the first coupling capacitor, the drain electrode of the sixth NMOS tube is connected with the negative end of the first current source load, and the drain electrode of the seventh NMOS tube is connected with the negative end of the second current source load.
10. The digital isolator according to claim 5, wherein said receive demodulation module further comprises:
the envelope comparator is used for demodulating the fully differential signal amplified by the preamplifier module and restoring the fully differential signal into an input signal received by the modulation sending module;
and the leading edge blanking circuit is used for eliminating the glitches in the restored input signal.
11. The digital isolator according to claim 1, wherein said modulation transmission module comprises: the first inverter, the second inverter, the third inverter, the first AND gate, the second AND gate, the first driver and the second driver;
the input end of the first phase inverter is connected with the oscillator, and the input end of the second phase inverter is connected with the input signal end;
the output end of the first phase inverter and the output end of the second phase inverter are connected with the input end of the first AND gate, the output end of the first AND gate is connected with the input end of the first driver, the input end of the second phase inverter is connected with the input end of the second AND gate through the third phase inverter, the output end of the first phase inverter is connected with the other input end of the second AND gate, the output end of the second AND gate is connected with the input end of the second driver, and the output end of the first driver and the output end of the second driver output full differential signals to the isolation capacitor module.
12. A chip comprising the digital isolator of any one of claims 1-11.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111182262.0A CN114050818A (en) | 2021-10-11 | 2021-10-11 | Digital isolator and chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111182262.0A CN114050818A (en) | 2021-10-11 | 2021-10-11 | Digital isolator and chip |
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|---|---|
| CN114050818A true CN114050818A (en) | 2022-02-15 |
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|---|---|---|---|
| CN202111182262.0A Pending CN114050818A (en) | 2021-10-11 | 2021-10-11 | Digital isolator and chip |
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| CN (1) | CN114050818A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115549670A (en) * | 2022-04-25 | 2022-12-30 | 圣邦微电子（北京）股份有限公司 | Digital isolator |
| CN116707516A (en) * | 2023-06-21 | 2023-09-05 | 深圳锐来博微电子有限公司 | Active receiving circuit and isolation chip |
-
2021
- 2021-10-11 CN CN202111182262.0A patent/CN114050818A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115549670A (en) * | 2022-04-25 | 2022-12-30 | 圣邦微电子（北京）股份有限公司 | Digital isolator |
| CN115549670B (en) * | 2022-04-25 | 2023-09-05 | 圣邦微电子（北京）股份有限公司 | digital isolator |
| CN116707516A (en) * | 2023-06-21 | 2023-09-05 | 深圳锐来博微电子有限公司 | Active receiving circuit and isolation chip |
| CN116707516B (en) * | 2023-06-21 | 2024-02-13 | 深圳锐来博微电子有限公司 | Active receiving circuit and isolation chip |
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