CN116707516A - Active receiving circuit and isolation chip - Google Patents
Active receiving circuit and isolation chip Download PDFInfo
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- CN116707516A CN116707516A CN202310744121.6A CN202310744121A CN116707516A CN 116707516 A CN116707516 A CN 116707516A CN 202310744121 A CN202310744121 A CN 202310744121A CN 116707516 A CN116707516 A CN 116707516A
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- 238000002955 isolation Methods 0.000 title claims abstract description 114
- 239000003990 capacitor Substances 0.000 claims abstract description 114
- 230000005669 field effect Effects 0.000 claims description 125
- 230000002708 enhancing effect Effects 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 3
- 230000008054 signal transmission Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 9
- 238000004088 simulation Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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Abstract
The invention discloses an active receiving circuit and an isolation chip, which comprises: the first isolation capacitor, the second isolation capacitor, the first active device and the second active device; one end of the first isolation capacitor is connected with a first differential signal, and the other end of the first isolation capacitor is connected with the first active device; one end of the second isolation capacitor is connected with a second differential signal, and the other end of the second isolation capacitor is connected with the second active device; wherein the first active device comprises two active resistors and the second active device comprises two active resistors; the invention forms the common mode reference by the voltage division of the first active device and the second active device, so that the common mode reference is not required to be additionally provided, and the subsequent amplifying and demodulating operations are convenient. And when the isolating chip generates overlarge common-mode interference, the common-mode current is compensated to ensure the normal transmission of signals.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an active receiving circuit and an isolation chip.
Background
In many applications, in view of noise isolation and electrical safety, an isolation chip is required, and the isolation chip is generally divided into a transmitting end, a receiving end and an isolation device. The transmitting end modulates the input signal (driving or control signal, etc.), drives the signal, etc., and after passing through the isolation device, the receiving end needs to receive, amplify, demodulate the isolation signal, etc.
In the prior art, in a receiving-end circuit, a passive resistor is used as a load to perform receiving and amplifying operations on a signal passing through an isolation device, as shown in fig. 1, on one hand, an additional common-mode voltage reference VB needs to be provided at a connection end of two passive resistors, so that subsequent operations such as amplifying and demodulating can be performed conveniently. On the other hand, the input common mode range of the receiving end circuit in the prior art is limited, and when the transient common mode noise is excessively generated, voltage saturation can be caused to cause signal loss.
Accordingly, the prior art is still in need of improvement and development.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to an active receiving circuit and an isolation chip, so as to solve the problems of providing an additional common-mode voltage reference and causing voltage saturation to lose signals when transient common-mode noise is excessively generated in the prior art.
The technical scheme of the invention is as follows:
an active receive circuit comprising: the first isolation capacitor, the second isolation capacitor, the first active device and the second active device;
one end of the first isolation capacitor is connected with a first differential signal, and the other end of the first isolation capacitor is connected with the first active device; one end of the second isolation capacitor is connected with a second differential signal, and the other end of the second isolation capacitor is connected with the second active device; wherein the first active device comprises two active resistors and the second active device comprises two active resistors;
the first isolation capacitor and the second isolation capacitor are used for enhancing isolation withstand voltage; the first active device and the second active device are used for voltage division and compensating common mode current when common mode interference is generated.
According to the further arrangement of the invention, the first active device comprises a first field effect transistor and a second field effect transistor;
the source electrode of the first field effect tube is connected with a power supply voltage and is connected with the second active device, and the grid electrode of the first field effect tube is connected with the other end of the first isolation capacitor and the drain electrode of the first field effect tube respectively;
the source electrode of the second field effect tube is grounded and connected with the second active device, and the grid electrode of the second field effect tube is respectively connected with the drain electrode of the second field effect tube and the drain electrode of the first field effect tube.
According to a further arrangement of the invention, the second active device comprises a third field effect transistor and a fourth field effect transistor;
the source electrode of the third field effect tube is connected with a power supply voltage and is connected with the first active device, and the grid electrode of the third field effect tube is respectively connected with the other end of the second isolation capacitor and the drain electrode of the third field effect tube;
the source electrode of the fourth field effect tube is grounded and connected with the first active device, and the grid electrode of the fourth field effect tube is respectively connected with the drain electrode of the fourth field effect tube and the drain electrode of the third field effect tube.
According to a further arrangement of the invention, the first active device further comprises a first resistor and a second resistor;
one end of the first resistor is connected with the grid electrode of the first field effect tube, and the other end of the first resistor is connected with the other end of the first isolation capacitor and the drain electrode of the first field effect tube respectively;
one end of the second resistor is connected with the drain electrode of the first field effect tube and the drain electrode of the second field effect tube, and the other end of the second resistor is connected with the grid electrode of the second field effect tube.
According to a further arrangement of the invention, the second active device further comprises a third resistor and a fourth resistor;
one end of the third resistor is connected with the grid electrode of the third field effect transistor, and the other end of the third resistor is connected with the other end of the second isolation capacitor and the drain electrode of the fourth field effect transistor respectively;
one end of the fourth resistor is connected with the drain electrode of the third field effect transistor and the drain electrode of the fourth field effect transistor, and the other end of the fourth resistor is connected with the grid electrode of the fourth field effect transistor.
According to a further arrangement of the invention, the first active device further comprises a first capacitor and a second capacitor;
one end of the first capacitor is connected with a power supply voltage and is connected with the second active device, and the other end of the first capacitor is connected with the grid electrode of the first field effect tube and one end of the first resistor respectively;
one end of the second capacitor is connected with the grid electrode of the second field effect transistor and the other end of the second resistor respectively, and the other end of the second capacitor is grounded.
According to a further arrangement of the invention, the second active device further comprises a third capacitor and a fourth capacitor;
one end of the third capacitor is connected with a power supply voltage and is connected with the first active device, and the other end of the third capacitor is connected with the grid electrode of the third field effect transistor and one end of the third resistor respectively;
one end of the fourth capacitor is connected with the grid electrode of the fourth field effect transistor and the other end of the fourth resistor respectively, and the other end of the fourth capacitor is grounded.
In a further arrangement of the invention, the first field effect transistor is a P-type field effect transistor, and the second field effect transistor is an N-type field effect transistor.
In a further arrangement of the invention, the third field effect transistor is a P-type field effect transistor, and the fourth field effect transistor is an N-type field effect transistor.
The invention also provides an isolation chip which comprises the active receiving circuit, the transmitting circuit and the signal demodulation circuit;
the transmitting circuit is connected with the active receiving circuit and is used for processing an input signal and outputting a first differential signal and a second differential signal to the active receiving circuit;
the active receiving circuit is connected with the signal demodulation circuit and is used for suppressing common-mode interference on the first differential signal and the second differential signal and outputting a common-mode signal to the active receiving circuit;
the active receiving circuit is used for amplifying and demodulating the common mode signal.
The invention provides an active receiving circuit and an isolation chip, comprising: the first isolation capacitor, the second isolation capacitor, the first active device and the second active device; one end of the first isolation capacitor is connected with a first differential signal, and the other end of the first isolation capacitor is connected with the first active device; one end of the second isolation capacitor is connected with a second differential signal, and the other end of the second isolation capacitor is connected with the second active device; wherein the first active device comprises two active resistors and the second active device comprises two active resistors; the first isolation capacitor and the second isolation capacitor are used for enhancing isolation withstand voltage; the first active device and the second active device are used for voltage division and compensating common mode current when common mode interference is generated. According to the invention, the first active device and the second active device are used for dividing the voltage to form the common mode reference, so that the common mode reference is not required to be additionally provided, and the subsequent amplifying and demodulating operations are convenient. And compensating common mode current when the first active device and the second active device generate excessive common mode interference in the isolation chip so as to ensure normal transmission of signals.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained from the structures shown in these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a prior art isolated receiving circuit.
Fig. 2 is a block diagram of an embodiment of an active receiving circuit in the present invention.
Fig. 3 is a circuit diagram of a second embodiment of an active receiving circuit in the present invention.
Fig. 4 is a circuit diagram of a third embodiment of an active receiving circuit in the present invention.
Fig. 5 is a circuit diagram of a fourth embodiment of an active receiving circuit in the present invention.
Fig. 6 is a block diagram of a isolated chip of the present invention.
Fig. 7 is a simulation of a isolated chip in the present invention.
Detailed Description
The invention provides an active receiving circuit and an isolation chip, which are used for making the purposes, technical schemes and effects of the invention clearer and clearer, and the invention is further described in detail below by referring to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In the description and claims, unless the context specifically defines the terms "a," "an," "the," and "the" include plural referents. If there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature.
It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein includes all or any element and all combination of one or more of the associated listed items.
It will be understood by those skilled in the art that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs unless defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
Referring to fig. 2 to 5, the present invention provides a preferred embodiment of an active receiving circuit and an isolation chip.
As shown in fig. 2, the present invention provides an active receiving circuit, comprising: a first isolation capacitor X1, a second isolation capacitor X2, a first active device 100, and a second active device 200; one end of the first isolation capacitor X1 is connected to a first differential signal V1, and the other end A1 of the first isolation capacitor X1 is connected to the first active device 100; one end of the second isolation capacitor X2 is connected to a second differential signal V2, and the other end A2 of the second isolation capacitor X2 is connected to the second active device 200; wherein the first active device 100 comprises two active resistors and the second active device 200 comprises two active resistors; the first isolation capacitor X1 and the second isolation capacitor X2 are used for enhancing isolation withstand voltage; the first active device 100 and the second active device 200 are used for dividing voltage and compensating common mode current when common mode interference is generated.
Specifically, as shown in fig. 2, fig. 2 is a structural diagram of the first embodiment. The capacitance value of the first isolation capacitor X1 is the same as that of the second isolation capacitor X2, so that the differential structure of the isolation chip is stabilized, and the isolation withstand voltage is enhanced. The first end of the first active device 100 is connected to the power supply voltage VCC, the second end of the first active device 100 is grounded, the third end of the first active device 100 is connected to the other end A1 of the first isolation capacitor X1, the first end of the second active device 200 is connected to the power supply voltage VCC, the second end of the second active device 200 is grounded, and the third end of the second active device 200 is connected to the other end A2 of the second isolation capacitor X2. Wherein the first active device 100 comprises two active resistors and the second active device 200 comprises two active resistors; the first active device 100 performs voltage division through the power supply voltage VCC to form a common mode reference, and the second active device 200 performs voltage division through the power supply voltage VCC to form a common mode reference, so that no additional common mode voltage reference is required to be provided, and further the subsequent amplifying and demodulating operations are facilitated.
The first active device 100 and the second active device 200 perform the same function, taking the first differential signal V1 input to the first active device 100 through the first isolation capacitor X1 as an example, when the isolated chip is not interfered by the common mode, the third terminal of the first active device 100 normally outputs the first differential signal V1. When the isolation chip is subjected to excessively strong common mode interference, the first active device 100 injects common mode current into the other end A1 of the first isolation capacitor X1, the first active device 100 and the second active device 200 form a differential structure, and symmetrical spike signals in differential form are generated at the other end A1 of the first isolation capacitor X1 and the other end A2 of the second isolation capacitor X2 so as to ensure normal transmission of signals.
In one embodiment, as shown in fig. 3, fig. 3 is a circuit diagram of a second embodiment, where the first active device 100 includes a first fet Q1 and a second fet Q2; the source electrode of the first field effect transistor Q1 is connected to the power supply voltage VCC and is connected to the second active device 200, and the gate electrode of the first field effect transistor Q1 is connected to the other end A1 of the first isolation capacitor X1 and the drain electrode of the first field effect transistor Q1, respectively; the source electrode of the second field effect transistor Q2 is grounded and connected to the second active device 200, and the gate electrode of the second field effect transistor Q2 is connected to the drain electrode of the second field effect transistor Q2 and the drain electrode of the first field effect transistor Q1, respectively. The second active device 200 includes a third fet Q3 and a fourth fet Q4; the source electrode of the third field effect transistor Q3 is connected to the power supply voltage VCC and is connected to the first active device 100, and the gate electrode of the third field effect transistor Q3 is connected to the other end A2 of the second isolation capacitor X2 and the drain electrode of the third field effect transistor Q3 respectively; the source electrode of the fourth field effect transistor Q4 is grounded and connected to the first active device 100, and the gate electrode of the fourth field effect transistor Q4 is connected to the drain electrode of the fourth field effect transistor Q4 and the drain electrode of the third field effect transistor Q3, respectively.
Specifically, the first field effect transistor Q1 is a P-type field effect transistor, the second field effect transistor Q2 is an N-type field effect transistor, the third field effect transistor Q3 is a P-type field effect transistor, and the fourth field effect transistor Q4 is an N-type field effect transistor. The first active device 100 and the second active device 200 have the same function, taking the first active device 100 as an example, the source electrode of the first field effect transistor Q1 is connected to the power supply voltage VCC, the drain electrode of the first field effect transistor Q1 is respectively connected to the drain electrode of the second field effect transistor Q2 and one end of the first isolation capacitor X1, so that the power supply voltage VCC is divided by the first field effect transistor Q1 and the second field effect transistor Q2 to form a common mode reference, thereby realizing that no additional common mode reference is needed, facilitating the subsequent amplifying and demodulating operations, the first field effect transistor Q1 and the second field effect transistor Q2 further provide an amplifying function to the first differential signal V1, and the third field effect transistor Q3 and the fourth field effect transistor Q4 further provide an amplifying function to the second differential signal V2. The dc bias point at the other end A1 of the first isolation capacitor X1 may be set according to the sizes of the first field effect transistor Q1 and the second field effect transistor Q2. The dc bias point at the other end A2 of the second isolation capacitor X2 may be set according to the sizes of the third fet Q3 and the fourth fet Q4.
Because when the isolation chip has overlarge common-mode interference, a positive-end or negative-end common-mode voltage is generated at the other end A1 of the first isolation capacitor X1, if the bias current at the other end A1 of the first isolation capacitor X1 is smaller at this moment, the positive-end common-mode voltage is larger than the power supply voltage VCC, the device stress is larger than the damage component, and the negative-end common-mode voltage is smaller than the ground voltage, so that circuit logic is disordered, and therefore, when the isolation chip has no common-mode interference, the first field-effect transistor Q1 and the second field-effect transistor Q2 are cut off, and the other end A1 of the first isolation capacitor X1 normally outputs a first differential signal V1. When the isolation chip has excessive positive-end common-mode interference, the second field effect transistor Q2 is conducted, and common-mode current of the isolation chip is poured into the other end A1 of the first isolation capacitor X1, so that normal transmission of signals is ensured. When the isolation chip has excessive negative terminal common mode interference, the first field effect transistor Q1 is conducted, and common mode current of the isolation chip is poured into the other end A1 of the first isolation capacitor X1, so that normal transmission of signals is ensured.
In one embodiment, as shown in fig. 4, fig. 4 is a circuit diagram of a third embodiment, where the first active device 100 further includes a first resistor R1 and a second resistor R2; one end of the first resistor R1 is connected with the grid electrode of the first field effect tube Q1, and the other end of the first resistor R1 is respectively connected with the other end A1 of the first isolation capacitor X1 and the drain electrode of the first field effect tube Q1; one end of the second resistor R2 is connected with the drain electrode of the first field effect tube Q1 and the drain electrode of the second field effect tube Q2, and the other end of the second resistor R2 is connected with the gate electrode of the second field effect tube Q2. The second active device 200 further includes a third resistor R3 and a fourth resistor R4; one end of the third resistor R3 is connected with the grid electrode of the third field effect transistor Q3, and the other end of the third resistor R3 is connected with the other end A2 of the second isolation capacitor X2 and the drain electrode of the fourth field effect transistor Q4 respectively; one end of the fourth resistor R4 is connected to the drain of the third fet Q3 and the drain of the fourth fet Q4, and the other end of the fourth resistor R4 is connected to the gate of the fourth fet Q4.
Specifically, the first active device 100 and the second active device 200 have the same function, and taking the first active device 100 as an example, the first resistor R1 is added between the gate of the first field effect transistor Q1 and the drain of the first field effect transistor Q1, and the bandwidth of the isolation chip is extended by the combined action of the parasitic capacitance of the first field effect transistor Q1 and the first resistor R1.
In one embodiment, as shown in fig. 5, fig. 5 is a circuit diagram of a fourth embodiment, where the first active device 100 further includes a first capacitor C1 and a second capacitor C2; one end of the first capacitor C1 is connected to the power supply voltage VCC and is connected to the second active device 200, and the other end of the first capacitor C1 is connected to the gate of the first field effect transistor Q1 and one end of the first resistor R1, respectively; one end of the second capacitor C2 is connected to the gate of the second field effect transistor Q2 and the other end of the second resistor R2, and the other end of the second capacitor C2 is grounded. The second active device 200 further includes a third capacitor C3 and a fourth capacitor C4; one end of the third capacitor C3 is connected to the power supply voltage VCC and is connected to the first active device 100, and the other end of the third capacitor C3 is connected to the gate of the third field effect transistor Q3 and one end of the third resistor R3, respectively; one end of the fourth capacitor C4 is connected to the gate of the fourth field effect transistor Q4 and the other end of the fourth resistor R4, and the other end of the fourth capacitor C4 is grounded.
Specifically, the first active device 100 and the second active device 200 have the same function, and taking the first active device 100 as an example, the first resistor R1 and the first capacitor C1 are added between the gate of the first field effect transistor Q1 and the drain of the first field effect transistor Q1, and the bandwidth of the isolation chip is further extended by the combined action of the first capacitor C1 and the first resistor R1.
The present invention also provides an isolation chip, as shown in fig. 6, comprising an active receiving circuit 20, a transmitting circuit 10 and a signal demodulating circuit 30 as described above; the transmitting circuit 10 is connected to the active receiving circuit 20, and is configured to process an input signal and output a first differential signal V1 and the second differential signal V2 to the active receiving circuit 20; the active receiving circuit 20 is connected to the signal demodulating circuit 30, and is configured to suppress common-mode interference of the first differential signal V1 and the second differential signal V2, and output a common-mode signal to the active receiving circuit 20; the active receiving circuit 20 is used for amplifying and demodulating the common mode signal. In particular, the embodiment of an active receiving circuit is described in detail herein and will not be described in detail herein.
To verify the superiority of the active receiving circuit of this embodiment, simulation experiments and test experiments were performed in this implementation, and simulation results are shown in fig. 7, specifically:
in fig. 7, rectangular waves are input signals, that is, the first differential signal input to the first isolation capacitor and the second differential signal input to the second isolation capacitor, respectively. In fig. 7, the gray thin line is the signal output by the first isolation capacitor, and the black appears as the signal output by the second isolation capacitor, so that it can be seen from fig. 7 that the peak signals in symmetrical differential form are generated on both the rising edge and the falling edge of the input signal, so as to facilitate the subsequent amplification and signal recovery circuit processing.
In summary, the active receiving circuit and the isolation chip provided by the present invention include: the first isolation capacitor, the second isolation capacitor, the first active device and the second active device; one end of the first isolation capacitor is connected with a first differential signal, and the other end of the first isolation capacitor is connected with the first active device; one end of the second isolation capacitor is connected with a second differential signal, and the other end of the second isolation capacitor is connected with the second active device; the first active device is composed of two active resistors, and the second active device is composed of two active resistors; the first isolation capacitor and the second isolation capacitor are used for enhancing isolation withstand voltage; the first active device and the second active device are used for voltage division and compensating common mode current when common mode interference is generated. According to the invention, the first active device and the second active device are used for dividing the voltage to form the common mode reference, so that the common mode reference is not required to be additionally provided, and the subsequent amplifying and demodulating operations are convenient. And compensating common mode current when the first active device and the second active device generate excessive common mode interference in the isolation chip so as to ensure normal transmission of signals.
It is to be understood that the invention is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.
Claims (10)
1. An active receive circuit, comprising: the first isolation capacitor, the second isolation capacitor, the first active device and the second active device;
one end of the first isolation capacitor is connected with a first differential signal, and the other end of the first isolation capacitor is connected with the first active device; one end of the second isolation capacitor is connected with a second differential signal, and the other end of the second isolation capacitor is connected with the second active device; wherein the first active device comprises two active resistors and the second active device comprises two active resistors;
the first isolation capacitor and the second isolation capacitor are used for enhancing isolation withstand voltage; the first active device and the second active device are used for voltage division and compensating common mode current when common mode interference is generated.
2. The active receive circuit of claim 1, wherein the first active device comprises a first field effect transistor and a second field effect transistor;
the source electrode of the first field effect tube is connected with a power supply voltage and is connected with the second active device, and the grid electrode of the first field effect tube is connected with the other end of the first isolation capacitor and the drain electrode of the first field effect tube respectively;
the source electrode of the second field effect tube is grounded and connected with the second active device, and the grid electrode of the second field effect tube is respectively connected with the drain electrode of the second field effect tube and the drain electrode of the first field effect tube.
3. The active receive circuit of claim 2, wherein the second active device comprises a third field effect transistor and a fourth field effect transistor;
the source electrode of the third field effect tube is connected with a power supply voltage and is connected with the first active device, and the grid electrode of the third field effect tube is respectively connected with the other end of the second isolation capacitor and the drain electrode of the third field effect tube;
the source electrode of the fourth field effect tube is grounded and connected with the first active device, and the grid electrode of the fourth field effect tube is respectively connected with the drain electrode of the fourth field effect tube and the drain electrode of the third field effect tube.
4. The active receive circuit of claim 2, wherein the first active device further comprises a first resistor and a second resistor;
one end of the first resistor is connected with the grid electrode of the first field effect tube, and the other end of the first resistor is connected with the other end of the first isolation capacitor and the drain electrode of the first field effect tube respectively;
one end of the second resistor is connected with the drain electrode of the first field effect tube and the drain electrode of the second field effect tube, and the other end of the second resistor is connected with the grid electrode of the second field effect tube.
5. The active receive circuit of claim 3, wherein the second active device further comprises a third resistor and a fourth resistor;
one end of the third resistor is connected with the grid electrode of the third field effect transistor, and the other end of the third resistor is connected with the other end of the second isolation capacitor and the drain electrode of the fourth field effect transistor respectively;
one end of the fourth resistor is connected with the drain electrode of the third field effect transistor and the drain electrode of the fourth field effect transistor, and the other end of the fourth resistor is connected with the grid electrode of the fourth field effect transistor.
6. The active receive circuit of claim 4, wherein the first active device further comprises a first capacitance and a second capacitance;
one end of the first capacitor is connected with a power supply voltage and is connected with the second active device, and the other end of the first capacitor is connected with the grid electrode of the first field effect tube and one end of the first resistor respectively;
one end of the second capacitor is connected with the grid electrode of the second field effect transistor and the other end of the second resistor respectively, and the other end of the second capacitor is grounded.
7. The active receive circuit of claim 5, wherein the second active device further comprises a third capacitor and a fourth capacitor;
one end of the third capacitor is connected with a power supply voltage and is connected with the first active device, and the other end of the third capacitor is connected with the grid electrode of the third field effect transistor and one end of the third resistor respectively;
one end of the fourth capacitor is connected with the grid electrode of the fourth field effect transistor and the other end of the fourth resistor respectively, and the other end of the fourth capacitor is grounded.
8. The active receiver circuit of claim 2, wherein the first fet is a P-type fet and the second fet is an N-type fet.
9. The active receiver circuit of claim 3, wherein the third fet is a P-type fet and the fourth fet is an N-type fet.
10. An isolated chip comprising the active receiving circuit, the transmitting circuit and the signal demodulating circuit of any one of claims 1-9;
the transmitting circuit is connected with the active receiving circuit and is used for processing an input signal and outputting a first differential signal and a second differential signal to the active receiving circuit;
the active receiving circuit is connected with the signal demodulation circuit and is used for suppressing common-mode interference on the first differential signal and the second differential signal and outputting a common-mode signal to the active receiving circuit;
the active receiving circuit is used for amplifying and demodulating the common mode signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310744121.6A CN116707516B (en) | 2023-06-21 | 2023-06-21 | Active receiving circuit and isolation chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310744121.6A CN116707516B (en) | 2023-06-21 | 2023-06-21 | Active receiving circuit and isolation chip |
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| CN116707516B CN116707516B (en) | 2024-02-13 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109495103A (en) * | 2017-11-30 | 2019-03-19 | 成都英思嘉半导体技术有限公司 | A kind of IC being integrated with DC isolation and its application |
| CN111446935A (en) * | 2020-05-20 | 2020-07-24 | 苏州纳芯微电子股份有限公司 | Differential signal amplifying circuit, digital isolator and digital receiver |
| CN114050818A (en) * | 2021-10-11 | 2022-02-15 | 北京芯可鉴科技有限公司 | Digital isolator and chip |
| CN115694466A (en) * | 2022-11-10 | 2023-02-03 | 西安电子科技大学芜湖研究院 | Interference suppression circuit and digital isolation circuit |
-
2023
- 2023-06-21 CN CN202310744121.6A patent/CN116707516B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109495103A (en) * | 2017-11-30 | 2019-03-19 | 成都英思嘉半导体技术有限公司 | A kind of IC being integrated with DC isolation and its application |
| CN111446935A (en) * | 2020-05-20 | 2020-07-24 | 苏州纳芯微电子股份有限公司 | Differential signal amplifying circuit, digital isolator and digital receiver |
| CN114050818A (en) * | 2021-10-11 | 2022-02-15 | 北京芯可鉴科技有限公司 | Digital isolator and chip |
| CN115694466A (en) * | 2022-11-10 | 2023-02-03 | 西安电子科技大学芜湖研究院 | Interference suppression circuit and digital isolation circuit |
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| CN116707516B (en) | 2024-02-13 |
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