CN115694466A - Interference suppression circuit and digital isolation circuit - Google Patents
Interference suppression circuit and digital isolation circuit Download PDFInfo
- Publication number
- CN115694466A CN115694466A CN202211406728.5A CN202211406728A CN115694466A CN 115694466 A CN115694466 A CN 115694466A CN 202211406728 A CN202211406728 A CN 202211406728A CN 115694466 A CN115694466 A CN 115694466A
- Authority
- CN
- China
- Prior art keywords
- pmos
- nmos
- tube
- drain electrode
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Logic Circuits (AREA)
Abstract
The invention discloses an interference suppression circuit and a digital isolation circuit, wherein the interference suppression circuit is arranged at a receiving end of the digital isolation circuit and is connected between an output end of an isolator and a preamplifier; the interference suppression circuit includes: the interference suppression circuit comprises a pair of NMOS transistors and a pair of PMOS transistors, wherein when the output signal of the isolator comprises transient pulse higher than common mode level, the pair of NMOS transistors are closed, and the pair of PMOS transistors are opened to reduce the first state of the transient pulse, when the output signal of the isolator comprises transient pulse lower than the common mode level, the pair of NMOS transistors are opened, and the pair of PMOS transistors are closed to improve the second state of the transient pulse, and when the output signal of the isolator is the common mode level, the pair of NMOS transistors and the pair of PMOS transistors are both closed. The circuit of the invention can effectively inhibit common mode transient interference.
Description
Technical Field
The present invention relates to the field of analog integrated circuits, and in particular, to an interference suppression circuit and a digital isolation circuit.
Background
Isolation refers to electrical separation between various functional circuits in a system, so that signals are not transmitted between the functional circuits through a direct conduction path, but a high-voltage domain and a low-voltage domain are separated through a physical layer, and thus, under the condition that different circuits can have different potentials, the mutual influence of the circuits at two ends is reduced to the maximum extent. At present, a capacitive coupling method is commonly used, and a corresponding capacitive isolation type driving circuit includes a transmitting end (a modulation module on a low-voltage side), a receiving end (a demodulation module on a high-voltage side) and an isolation capacitor, where the transmitting end modulates a transmission signal into a signal that can pass through the isolation capacitor module, the receiving end demodulates the signal that passes through the isolation capacitor module into a transmission signal, and the isolation capacitor module connects the transmitting end and the receiving end.
With the intelligentization of industrial and communication equipment, the demand of the market for digital isolators is increasing day by day, and the performance requirements are higher and higher. Therefore, one of the problems to be solved in designing the digital isolator is common mode transient interference. Currently, a differential circuit is generally used to improve common-mode transient interference of a digital isolator, which mainly reduces common-mode interference through two resistors in the circuit, but the working range of the differential circuit is small, and when a common-mode voltage exceeds the working range of the differential circuit, communication failure still occurs.
Therefore, how to effectively suppress the common mode transient interference in the digital isolation circuit becomes an urgent problem to be solved.
Disclosure of Invention
Therefore, in order to solve the above problems occurring in the prior art, the present application provides an interference suppression circuit and a digital isolation circuit.
According to a first aspect, the present invention provides an interference suppression circuit, disposed at a receiving end of a digital isolation circuit, and connected between an output end of an isolator and a preamplifier; the interference suppression circuit includes:
the interference suppression circuit comprises a pair of NMOS transistors and a pair of PMOS transistors, wherein when the output signal of the isolator comprises transient pulses higher than a common mode level, the pair of NMOS transistors are closed, and the pair of PMOS transistors are opened so as to reduce the first state of the transient pulses, and when the output signal of the isolator comprises transient pulses lower than the common mode level, the pair of NMOS transistors are opened, the pair of PMOS transistors are closed so as to improve the second state of the transient pulses, and when the output signal of the isolator is the common mode level, the pair of NMOS transistors and the pair of PMOS transistors are closed.
Furthermore, the pair of NMOS transistors comprises an NMOS transistor M1 and an NMOS transistor M3, and the pair of PMOS transistors comprises a PMOS transistor M2 and a PMOS transistor M4;
the grid electrodes of the NMOS tube M1 and the PMOS tube M2 are both connected to a reference voltage, the drain electrode of the NMOS tube M1 is connected to the high-level output end of the driving power supply, the source electrode of the NMOS tube M2 is connected to the source electrode of the PMOS tube M2 and is connected to the positive-phase input end and the positive-phase output end, and the drain electrode of the PMOS tube M2 is grounded;
the grid electrodes of the NMOS tube M3 and the PMOS tube M4 are both connected to a reference voltage, the drain electrode of the NMOS tube M3 is connected to the high-level output end of the driving power supply, the source electrode of the NMOS tube M4 is connected to the source electrode of the PMOS tube M4, the inverted input end is connected to the output end, and the drain electrode of the PMOS tube M4 is grounded.
Further, a first capacitor is further arranged between the source electrode of the NMOS transistor M1 and the positive phase input end, and a second capacitor is further arranged between the source electrode of the NMOS transistor M3 and the negative phase input end.
According to a second aspect, the present invention further provides a digital isolation circuit, which includes a sending end circuit, an isolator, and a receiving end circuit, where the receiving end circuit includes a preamplifier, a demodulation circuit, and the interference suppression circuit in any of the above embodiments of the first aspect, and the interference suppression circuit, the preamplifier, and the demodulation circuit are connected in sequence.
Further, the demodulation circuit includes:
a PMOS transistor M13 having a gate connected to the output terminal V of the first bias voltage BIAS1 Source connected to high level output terminal V of driving power supply DD ；
PMOS transistor M14, PMOS transistor M15 and PMOS transistor M16, their source electrode all is connected with the drain electrode of PMOS transistor M13, the grid of PMOS transistor M14 is connected to the inverting input V IN The grid of the PMOS tube M15 is connected to the positive input V IP Grid connection of PMOS transistor M16To a common mode level V REF ；
PMOS transistor M17 and PMOS transistor M18, their gates are connected to each other, and their sources are connected to the high-level output end V of the driving power supply DD ；
PMOS transistor M19 and PMOS transistor M20, the gates of which are connected to each other and to the output terminal V of the second bias voltage BIAS2 The source electrode of the PMOS tube M19 is connected with the drain electrode of the PMOS tube M17, and the source electrode of the PMOS tube M20 is connected with the drain electrode of the PMOS tube M18;
NMOS transistors M21 and M22 with their gates connected to each other and to the output terminal V of the third bias voltage BIAS3 The drain electrode of the NMOS tube M21 is connected with the drain electrode of the PMOS tube M19 and the grid electrode of the PMOS tube M17, and the drain electrode of the NMOS tube M22 is connected with the drain electrode of the PMOS tube M20;
NMOS transistor M23 and NMOS transistor M24, the gates of which are connected to each other and to the output terminal V of the fourth bias voltage BIAS4 The sources of the two are connected to the low level output end V of the driving power supply SS The drain electrode of the NMOS tube M23 is connected with the source electrode of the NMOS tube M21, the drain electrode of the PMOS tube M14 and the drain electrode of the PMOS tube M15, and the drain electrode of the NMOS tube M24 is connected with the source electrode of the NMOS tube M22 and the drain electrode of the PMOS tube M16;
the gates of the PMOS transistor M25 and the NMOS transistor M26 are connected to each other and connected between the drain of the PMOS transistor M20 and the drain of the NMOS transistor M22, and the drains of the PMOS transistor M25 and the NMOS transistor are connected to each other and receive the output signal DE MOD The source electrode of the PMOS tube M25 is connected to the high-level output end V of the driving power supply DD The source electrode of the NMOS tube M26 is connected to the low level output end V of the driving power supply SS 。
The technical scheme provided by the invention has the following advantages:
1. the interference suppression circuit provided by the invention comprises an interference suppression circuit comprising a pair of NMOS (N-channel metal oxide semiconductor) tubes and a pair of PMOS (P-channel metal oxide semiconductor) tubes, and the interference suppression circuit is arranged in such a way that the NMOS tubes are closed and the PMOS tubes are opened when the output signal of the isolator comprises transient pulses higher than a common mode level, so that the pulse amplitude of the transient pulses is reduced, the NMOS tubes are opened and the PMOS tubes are closed when the output signal of the isolator comprises transient pulses lower than the common mode level, so that the pulse amplitude of the transient pulses is increased, and finally, the common mode transient interference is effectively suppressed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of an interference suppression circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a digital isolation circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a demodulation circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are merely for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Example 1
Fig. 1 shows a schematic structural diagram of an interference suppression circuit in an embodiment of the present invention, specifically, as shown in fig. 2, the interference suppression circuit is disposed at a receiving end of a digital isolation circuit and is connected between an output end of an isolator and a preamplifier (the preamplifier in fig. 2 is the preamplifier), and as shown in fig. 2, the disposition of the interference suppression circuit does not affect the disposition of other circuits (such as a sending end circuit, a receiving end demodulation circuit, a receiving end amplification circuit, etc.) of the digital isolation circuit.
Specifically, the interference suppression circuit comprises a pair of NMOS transistors and a pair of PMOS transistors, and the interference suppression circuit has a first state that the pair of NMOS transistors are closed and the pair of PMOS transistors are opened to reduce transient pulses when the output signal of the isolator comprises transient pulses higher than a common mode level, a second state that the pair of NMOS transistors are opened and the pair of PMOS transistors are closed to improve the transient pulses when the output signal of the isolator comprises transient pulses lower than the common mode level, and a third state that the pair of NMOS transistors and the pair of PMOS transistors are closed when the output signal of the isolator is the common mode level.
Specifically, as shown in fig. 2, the signal subjected to common mode transient interference suppression by the interference suppression circuit is normally transmitted to the preamplifier and demodulator circuit for demodulation.
Taking an example that a pair of NMOS transistors refers to NMOS transistor M1 and NMOS transistor M3, and a pair of PMOS transistors refers to PMOS transistor M2 and PMOS transistor M4 for specific description, as shown in fig. 1, the gates of NMOS transistor M1, PMOS transistor M2, NMOS transistor M3, and PMOS transistor M4 are all connected to a reference voltage V REF (ii) a The drain electrode of the NMOS tube M1 is connected to the high-level output end V of the driving power supply DD The source electrode of the NMOS tube M1 is connected to the source electrode of the PMOS tube M2 and connected to the positive-phase input V IP Positive phase output V OP The drain electrode of the PMOS tube M2 is grounded; the drain electrode of the NMOS tube M3 is connected to the high level output end V of the driving power supply DD The source electrode of the NMOS tube M3 is connected to the source electrode of the PMOS tube M4 and connected with the inverted input V IN Output and output inverted output V ON And the drain electrode of the PMOS tube M4 is grounded.
Specifically, a reference voltage V is set REF At a common mode level, then at the input signal (V) IP And V IN ) At normal constant common mode level, NThe MOS transistor M1, the PMOS transistor M2, the NMOS transistor M3 and the PMOS transistor M4 are all closed, and signals (V) are output OP And V ON ) Same as the input signal; when the input signal is a pulse higher than the common mode level, the NMOS tube M1 and the NMOS tube M3 are closed, the PMOS tube M2 and the PMOS tube M4 are opened, and the pulse amplitude is reduced; when the input signal is a pulse lower than the common mode level, the NMOS transistor M1 and the NMOS transistor M3 are opened, the PMOS transistor M2 and the PMOS transistor M4 are closed, and the pulse amplitude is increased; finally, an effective suppression of common mode transient disturbances is achieved, both in the presence of transient pulses above and below the common mode level.
In a specific implementation manner of this embodiment, the source of the NMOS transistor M1 and the positive-phase input terminal V may also be provided IP A first capacitor C1 is arranged between the NMOS transistor M3 and the inverted input end V IN A second capacitor C2 is also provided in between.
The interference suppression correction circuit in this embodiment includes a pair of NMOS transistors and a pair of PMOS transistors, and when the output signal of the isolator includes a transient pulse higher than the common mode level, the pair of NMOS transistors is turned off and the pair of PMOS transistors is turned on, so as to reduce the pulse amplitude of the transient pulse, and when the output signal of the isolator includes a transient pulse lower than the common mode level, the pair of NMOS transistors is turned on and the pair of PMOS transistors is turned off, so as to increase the pulse amplitude of the transient pulse, and finally, effective suppression of the common mode transient interference is achieved.
Example 2
Fig. 2 is a schematic diagram showing a digital isolation circuit in an embodiment of the present invention, as shown in fig. 1, a transmitting end circuit, an isolator, and a receiving end circuit, where the receiving end circuit includes a preamplifier, a demodulation circuit, and the interference suppression circuit in the above example 1; and the interference suppression circuit, the preamplifier and the demodulation circuit are connected in sequence.
Fig. 3 shows a schematic structural diagram of a receiving-end demodulation circuit in an embodiment of the present invention. As shown in fig. 3, the demodulation circuit may include: a PMOS transistor M13 having a gate connected to the output terminal V of the first bias voltage BIAS1 Source connected to high level output terminal V of driving power supply DD (ii) a PMOS transistor M14, PMOS transistor M15 and PMOS transistor M16, the source electrodes of which are connected with the drain electrode of PMOS transistor M13, and the grid electrode of PMOS transistor M14 is connected to the inverting input V IN The grid of the PMOS tube M15 is connected to the positive input V IP The grid of the PMOS tube M16 is connected to the common mode level V REF (ii) a PMOS transistor M17 and PMOS transistor M18, their gates are connected to each other, and their sources are connected to the high-level output end V of the driving power supply DD (ii) a PMOS transistor M19 and PMOS transistor M20, the gates of which are connected to each other and to the output terminal V of the second bias voltage BIAS2 The source electrode of the PMOS tube M19 is connected with the drain electrode of the PMOS tube M17, and the source electrode of the PMOS tube M20 is connected with the drain electrode of the PMOS tube M18; NMOS transistor M21 and NMOS transistor M22, the gates of which are connected to each other and to the output terminal V of the third bias voltage BIAS3 The drain electrode of the NMOS tube M21 is connected with the drain electrode of the PMOS tube M19 and the grid electrode of the PMOS tube M17, and the drain electrode of the NMOS tube M22 is connected with the drain electrode of the PMOS tube M20; NMOS transistor M23 and NMOS transistor M24, the gates of which are connected to each other and to the output terminal V of the fourth bias voltage BIAS4 The sources of the two are connected to the low level output end V of the driving power supply SS The drain electrode of the NMOS tube M23 is connected with the source electrode of the NMOS tube M21, the drain electrode of the PMOS tube M14 and the drain electrode of the PMOS tube M15, and the drain electrode of the NMOS tube M24 is connected with the source electrode of the NMOS tube M22 and the drain electrode of the PMOS tube M16; the gates of the PMOS transistor M25 and the NMOS transistor M26 are connected to each other and connected between the drain of the PMOS transistor M20 and the drain of the NMOS transistor M22, and the drains of the PMOS transistor M25 and the NMOS transistor are connected to each other and receive the output signal DE MOD The source electrode of the PMOS tube M25 is connected to the high-level output end V of the driving power supply DD The source electrode of the NMOS tube M26 is connected to the low level output end V of the driving power supply SS 。
The digital isolation circuit in the embodiment realizes effective suppression of common-mode transient interference through the interference suppression circuit, and has high common-mode transient interference rejection capability.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. This need not be, nor should it be exhaustive of all embodiments. And obvious variations or modifications therefrom are intended to be within the scope of the invention.
Claims (5)
1. An interference suppression circuit is characterized in that the interference suppression circuit is arranged at a receiving end of a digital isolation circuit and is connected between an output end of an isolator and a preamplifier; the interference suppression circuit includes:
the interference suppression circuit comprises a pair of NMOS transistors and a pair of PMOS transistors, wherein the pair of NMOS transistors is closed and the pair of PMOS transistors is opened when the output signal of the isolator comprises transient pulses higher than a common mode level so as to reduce the first state of the transient pulses, the pair of NMOS transistors is opened and the pair of PMOS transistors is closed when the output signal of the isolator comprises transient pulses lower than the common mode level so as to improve the second state of the transient pulses, and the output signal of the isolator is the third state that the pair of NMOS transistors and the pair of PMOS transistors are closed when the output signal of the isolator is the common mode level.
2. The jammer suppression circuit of claim 1, wherein the pair of NMOS transistors comprises NMOS transistor M1 and NMOS transistor M3, and the pair of PMOS transistors comprises PMOS transistor M2 and PMOS transistor M4;
the grid electrodes of the NMOS tube M1 and the PMOS tube M2 are both connected to a reference voltage, the drain electrode of the NMOS tube M1 is connected to the high-level output end of the driving power supply, the source electrode of the NMOS tube M2 is connected to the source electrode of the PMOS tube M2 and is connected to the positive-phase input end and the positive-phase output end, and the drain electrode of the PMOS tube M2 is grounded;
the grid electrodes of the NMOS tube M3 and the PMOS tube M4 are also connected to the reference voltage, the drain electrode of the NMOS tube M3 is connected to the high-level output end of the driving power supply, the source electrode of the NMOS tube M3 is connected to the source electrode of the PMOS tube M4, the source electrode of the PMOS tube M4 is connected to the inverting input end and the inverting output end, and the drain electrode of the PMOS tube M4 is grounded.
3. The interference suppression circuit according to claim 2, wherein a first capacitor is further disposed between the source of the NMOS transistor M1 and the non-inverting input terminal, and a second capacitor is further disposed between the source of the NMOS transistor M3 and the inverting input terminal.
4. A digital isolation circuit comprising a transmitting side circuit, an isolator, and a receiving side circuit, said receiving side circuit comprising a preamplifier, a demodulation circuit, and the interference suppression circuit of any of claims 1-4, said interference suppression circuit, said preamplifier, and said demodulation circuit being connected in series.
5. The digital isolation circuit of claim 4, wherein the demodulation circuit comprises:
a PMOS transistor M13 having a gate connected to the output terminal V of the first bias voltage BIAS1 The source electrode is connected to the high level output end V of the driving power supply DD ；
PMOS transistor M14, PMOS transistor M15 and PMOS transistor M16, their source electrode all with the drain electrode of PMOS pipe M13 is connected, the grid of PMOS pipe M14 is connected to inverting input V IN The grid of the PMOS tube M15 is connected to the positive phase input V IP The grid of the PMOS tube M16 is connected to a common mode level V REF ；
PMOS transistor M17 and PMOS transistor M18, their gates are connected to each other, and their sources are connected to the high level output end V of the drive power supply DD ；
PMOS transistor M19 and PMOS transistor M20, the gates of which are connected to each other and to the output terminal V of the second bias voltage BIAS2 The source electrode of the PMOS tube M19 is connected with the drain electrode of the PMOS tube M17, and the source electrode of the PMOS tube M20 is connected with the drain electrode of the PMOS tube M18;
NMOS transistor M21 and NMOS transistor M22, the gates of which are connected to each other and to the output terminal V of the third bias voltage BIAS3 The drain electrode of the NMOS tube M21 is connected with the drain electrode of the PMOS tube M19 and the gate electrode of the PMOS tube M17, and the drain electrode of the NMOS tube M22 is connected with the drain electrode of the PMOS tube M20;
NMOS transistor M23 and NMOS transistor M24, bothAre connected to each other and to an output terminal V of a fourth bias voltage BIAS4 The sources of the two are connected to the low-level output end V of the driving power supply SS The drain electrode of the NMOS transistor M23 is connected to the source electrode of the NMOS transistor M21, the drain electrode of the PMOS transistor M14, and the drain electrode of the PMOS transistor M15, and the drain electrode of the NMOS transistor M24 is connected to the source electrode of the NMOS transistor M22 and the drain electrode of the PMOS transistor M16;
the grid electrodes of the PMOS tube M25 and the NMOS tube M26 are mutually connected and connected between the drain electrode of the PMOS tube M20 and the drain electrode of the NMOS tube M22, and the drain electrodes of the PMOS tube M25 and the NMOS tube M22 are mutually connected and connected to output a signal DE MOD The source electrode of the PMOS tube M25 is connected to the high-level output end V of the driving power supply DD The source electrode of the NMOS tube M26 is connected to the low level output end V of the driving power supply SS 。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211406728.5A CN115694466A (en) | 2022-11-10 | 2022-11-10 | Interference suppression circuit and digital isolation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211406728.5A CN115694466A (en) | 2022-11-10 | 2022-11-10 | Interference suppression circuit and digital isolation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115694466A true CN115694466A (en) | 2023-02-03 |
Family
ID=85051751
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211406728.5A Pending CN115694466A (en) | 2022-11-10 | 2022-11-10 | Interference suppression circuit and digital isolation circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115694466A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116707516A (en) * | 2023-06-21 | 2023-09-05 | 深圳锐来博微电子有限公司 | Active receiving circuit and isolation chip |
-
2022
- 2022-11-10 CN CN202211406728.5A patent/CN115694466A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116707516A (en) * | 2023-06-21 | 2023-09-05 | 深圳锐来博微电子有限公司 | Active receiving circuit and isolation chip |
| CN116707516B (en) * | 2023-06-21 | 2024-02-13 | 深圳锐来博微电子有限公司 | Active receiving circuit and isolation chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110417360B (en) | Low-noise amplifier for bioelectricity detection | |
| CN101188406B (en) | Low frequency analog circuit | |
| US20060001504A1 (en) | High bandwidth high gain receiver equalizer | |
| US10637695B1 (en) | High-speed low-voltage serial link receiver and method thereof | |
| US10673606B1 (en) | High-speed full-duplex transceiver and method thereof | |
| CN115694466A (en) | Interference suppression circuit and digital isolation circuit | |
| CN106330104A (en) | Fully differential amplifier circuit with high accuracy and high dynamic range | |
| CN104579260B (en) | Hysteresis comparator for radio frequency identification | |
| CN113419595B (en) | Digital isolator and common mode interference suppression circuit thereof | |
| CN213402947U (en) | Low-voltage differential signal receiving circuit | |
| EP0234107A2 (en) | Field-effect transistor circuits | |
| CN111555739B (en) | Demodulation method and circuit of signal isolation system | |
| US7843236B2 (en) | Low voltage differential signal receiver | |
| CN113114142A (en) | Rail-to-rail operational amplifier and interface circuit | |
| CN114221641B (en) | Rapid comparator circuit for wide common-mode input voltage | |
| US11929719B2 (en) | Super source follower | |
| US4638259A (en) | CMOS differential amplifier stage with bulk isolation | |
| US12028028B2 (en) | Isolation circuit systems and methods thereof | |
| CN105450181A (en) | Slew rate enhanced operational amplifier suitable for restraining electromagnetic interference | |
| CN102045033B (en) | Amplifier with single-ended input and differential output | |
| CN111835304B (en) | Transconductance operational amplifier for analog front end of sensor | |
| CN210405236U (en) | Differential amplifier with high common-mode dynamic range and constant PVT | |
| CN110492852B (en) | Differential input structure capable of improving operational amplifier performance | |
| US10528324B2 (en) | Virtual hybrid for full duplex transmission | |
| CN115833755A (en) | Signal demodulation circuit and digital isolation circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |