CN105450181A - Slew rate enhanced operational amplifier suitable for restraining electromagnetic interference - Google Patents

Abstract

The invention discloses a slew rate enhanced operational amplifier suitable for restraining electromagnetic interference. The operational amplifier consists of seventeen MOS (Metal Oxide Semiconductor) transistors, namely, first to eleventh PMOS (P-channel Metal Oxide Semiconductor) transistors M0, M1a, M1b, M2a, M2b, M5, M6, M7, M8, M9 and M10 and first to sixth NMOS (N-channel Metal Oxide Semiconductor) transistors M3a, M3b, M4a, M4b, M11 and M12, wherein differential-mode signals Vin+ and Vin- are input through gate electrode input ends Vp of the second to third PMOS transistors M1a and M1b, and gate electrode input ends Vn of the fourth to fifth PMOS transistors M2a and M2b respectively; spurious signals are filtered through amplification of a Recycling folded cascode amplification stage and an electromagnetic interference restraining stage; meanwhile, a slew rate is increased; and a signal is output through a high-gain output end Vout. Through adoption of the operational amplifier in a low-voltage and low-power-consumption mixed signal circuit, an electromagnetic interference restraining ability specific to signals can be enhanced while the slew rate is increased.

Description

Be applicable to the Slew Rate enhancement mode operational amplifier suppressing electromagnetic interference

Technical field

The present invention relates to operational amplifier and Electromagnetic Interference Suppressing Techniques, particularly relate to a kind of low-power consumption Slew Rate enhancement mode single stage operational amplifier.

Background technology

Along with the development of modern CMOS composite signal integrated circuits, analog module and digital circuit blocks on the same substrate integrated, two kinds of circuit modules easily produce coupling effect and the crosstalk of signal.But analog circuit is very responsive to coupling effect, because this can worsen the signal of analog circuit internal circuit, thus cause error and erroneous judgement.Minimum for coupling effect being reduced to, the suppression circuit of research electromagnetic interference (EMI) has very important significance.In analog module, the application of operational amplifier widely, so the EMI of research amplifier suppresses circuit just to have realistic meaning.Because low-voltage and low-power dissipation high gain operational amplifier is more easily subject to the impact of electromagnetic interference, produce the drift of performance parameter.In order to while raising bandwidth sum Slew Rate, the EMI rejection ability of circuit also can be improved.

Summary of the invention

In order to overcome above-mentioned prior art Problems existing, the present invention proposes a kind of Slew Rate enhancement mode operational amplifier being applicable to electromagnetic interference and suppressing, based on original Recyclingfoldedcascode (loop collapsing cascade) amplifier, while raising gain and Slew Rate, adopt the nonlinear interaction of RC to improve the rejection ability of EMI, finally realize amplifier, under designated parameter condition, there is good small-signal behaviour and large signal characteristic.

The present invention proposes a kind of Slew Rate enhancement mode operational amplifier being applicable to electromagnetic interference and suppressing, described operational amplifier comprises the first to the 11 PMOS transistor M0, M1a, M1b, M2a, M2b, M5, M6, M7, M8, M9, M10 and first to the 6th nmos pass transistor M3a, M3b, M4a, M4b, M11, M12 totally ten seven MOS transistor; Wherein:

The first, the source electrode of the 6th, the 7th PMOS transistor M0, M5, M6 meets power supply VDD jointly; The substrate termination power supply VDD of all PMOS transistor M0, M1a, M1b, M2a, M2b, M5, M6, M7, M8, M9, M10; The Substrate ground GND of first to the 6th nmos pass transistor M3a, M3b, M4a, M4b, M11, M12; The source electrode of first to fourth nmos pass transistor M3a, M3b, M4a, M4b and one end common ground GND of first, second electric capacity C1, C2;

The grid of the first PMOS transistor M0 meets the first bias voltage Vb1, and drain electrode connects the source electrode of the second to the 5th PMOS transistor M1a, M1b, M2a, M2b; The grid of the second to the 3rd PMOS transistor M1a, M1b meets input Vp; The grid of the 4th to the 5th PMOS transistor M2a, M2b meets input Vn;

One end of the drain electrode of the second PMOS transistor M1a, the drain electrode of the first nmos pass transistor M3a, the 3rd electric capacity Cb1 connects the drain electrode of the tenth PMOS transistor M9 jointly; One end of the drain electrode of the 4th PMOS transistor M2a, the drain electrode of the 3rd nmos pass transistor M4a, the 4th electric capacity Cb2 connects the drain electrode of the 11 nmos pass transistor M10 jointly;

One end of the drain electrode of the 3rd PMOS transistor M1b, the grid of the 4th nmos pass transistor M4b, the second resistance R2 connects the drain electrode of the 6th nmos pass transistor M12 jointly; One end of the drain electrode of the 5th PMOS transistor M2b, the grid of the second nmos pass transistor M3b, the first resistance R1 connects the drain electrode of the 5th nmos pass transistor M11 jointly; The source electrode of the 5th nmos pass transistor M11 connects the drain electrode of the second nmos pass transistor M3b; The source electrode of the 6th nmos pass transistor M12 connects the drain electrode of the 4th nmos pass transistor M4b;

The upper end of grid first electric capacity C1 of the first nmos pass transistor M3a, the lower end of the 3rd electric capacity Cb1 connect the other end of the first resistance R1 jointly; The other end of the grid of the 3rd nmos pass transistor M4a, the other end of the second electric capacity C2, the 4th electric capacity Cb2 connects the other end of the second resistance R2 jointly;

Six, the grid of the 7th PMOS transistor M5, M6 connects the drain electrode of the 8th PMOS transistor M7 and the source electrode of the tenth PMOS transistor M9 jointly; Ten, the grid of the 11 PMOS transistor M9, M10 meets the 4th bias voltage Vb4 jointly; Eight, the grid of the 9th PMOS transistor M7, M8 meets the 3rd bias voltage Vb3 jointly; The drain electrode of the 6th PMOS transistor M5 connects the source electrode of the 8th PMOS transistor M7; The drain electrode of the 7th PMOS transistor M6 connects the source electrode of the 9th PMOS transistor M8; The drain electrode of the 9th PMOS transistor M8, the source electrode of the 11 PMOS transistor M10 meet output end vo ut jointly;

Choose the second to the 3rd PMOS transistor M1a, the gate input Vp and the 4th of M1b is to the 5th PMOS transistor M2a, the gate input Vn of M2b, input difference mode signal Vin+ and Vin-respectively, pass through: comprise the second to the 5th PMOS transistor M1a, M1b, M2a, the transconductance input stage gm1 of M2b, comprise second, 4th to the 6th nmos pass transistor M3b, M4b, M11, the cascode level of M12, and comprise the 6th to the 11 PMOS transistor M5, M6, M7, M8, M9, the amplification of the loop collapsing cascade amplifying stage that the plus and blowup level of M10 is formed jointly, then pass through by four electric capacity C1, C2, Cb1, Cb2 and two resistance R1, the electromagnetic interference killer stage that R2 is formed, filter spurious signal, utilizing first to the 6th nmos pass transistor M3a, M3b, M4a, M4b, M11, M12 to strengthen Slew Rate simultaneously, then through comprising transistor M5 ~ M10 output stage, being outputed signal by high voltage amplitude of oscillation output end vo ut.

Compared with prior art, the present invention is in low-voltage and low-power dissipation mixed signal circuit, and this operational amplifier while enhancing Slew Rate, can improve the electromagnetic interference rejection ability to signal.

Accompanying drawing explanation

Fig. 1 is the circuit diagram of the Slew Rate enhancement mode operational amplifier for electromagnetic interference suppression that the present invention proposes.

Embodiment

Below in conjunction with the drawings and the specific embodiments, be described in further detail technical scheme of the present invention.

The embodiment of the present invention specifically describes: the gate input Vp and the 4th to the gate input Vn of the 5th PMOS transistor M2a, M2b choosing the second to the 3rd PMOS transistor M1a, M1b, input difference mode signal Vin+ and Vin-respectively, through the amplification of Recyclingfoldedcascode amplifying stage, then spurious signal is filtered through electromagnetic interference killer stage, the enhancing Slew Rate of current mirror, then outputs signal through too high voltages amplitude of oscillation output end vo ut simultaneously.While final realization maintains the stability of amplifier, under equal consumption conditions, improve the object of the Slew Rate of EMI rejection ability and boster.

Described amplifier is made up of Recyclingfoldedcascode amplifying stage, electromagnetic interference killer stage, output stage.Recyclingfoldedcascode amplifying stage comprises transconductance input stage gm1 (comprising the second to the 5th PMOS transistor M1a, M1b, M2a, M2b), cascode level (comprising the second, the 4th to the 6th nmos pass transistor M3b, M4b, M11, M12) and plus and blowup level (comprising the 6th to the 11 PMOS transistor M5, M6, M7, M8, M9, M10), and electromagnetic interference killer stage comprises four electric capacity C1, C2, Cb1, Cb2 and two resistance R1, R2 and transistor M3a, M3b, M4a and M4b.Output stage comprises transistor M5-M10.

Claims (1)

1. one kind is applicable to the Slew Rate enhancement mode operational amplifier suppressing electromagnetic interference, it is characterized in that, described operational amplifier comprises the first to the 11 PMOS transistor M0, M1a, M1b, M2a, M2b, M5, M6, M7, M8, M9, M10 and first to the 6th nmos pass transistor M3a, M3b, M4a, M4b, M11, M12 totally ten seven MOS transistor; Wherein:

The first, the source electrode of the 6th, the 7th PMOS transistor M0, M5, M6 meets power supply VDD jointly; The substrate termination power supply VDD of all PMOS transistor M0, M1a, M1b, M2a, M2b, M5, M6, M7, M8, M9, M10; The Substrate ground GND of first to the 6th nmos pass transistor M3a, M3b, M4a, M4b, M11, M12; The source electrode of first to fourth nmos pass transistor M3a, M3b, M4a, M4b and one end common ground GND of first, second electric capacity C1, C2;

The grid of the first PMOS transistor M0 meets the first bias voltage Vb1, and drain electrode connects the source electrode of the second to the 5th PMOS transistor M1a, M1b, M2a, M2b; The grid of the second to the 3rd PMOS transistor M1a, M1b meets input Vp; The grid of the 4th to the 5th PMOS transistor M2a, M2b meets input Vn;

One end of the drain electrode of the second PMOS transistor M1a, the drain electrode of the first nmos pass transistor M3a, the 3rd electric capacity Cb1 connects the drain electrode of the tenth PMOS transistor M9 jointly; One end of the drain electrode of the 4th PMOS transistor M2a, the drain electrode of the 3rd nmos pass transistor M4a, the 4th electric capacity Cb2 connects the drain electrode of the 11 nmos pass transistor M10 jointly;

One end of the drain electrode of the 3rd PMOS transistor M1b, the grid of the 4th nmos pass transistor M4b, the second resistance R2 connects the drain electrode of the 6th nmos pass transistor M12 jointly; One end of the drain electrode of the 5th PMOS transistor M2b, the grid of the second nmos pass transistor M3b, the first resistance R1 connects the drain electrode of the 5th nmos pass transistor M11 jointly; The source electrode of the 5th nmos pass transistor M11 connects the drain electrode of the second nmos pass transistor M3b; The source electrode of the 6th nmos pass transistor M12 connects the drain electrode of the 4th nmos pass transistor M4b;

The upper end of grid first electric capacity C1 of the first nmos pass transistor M3a, the lower end of the 3rd electric capacity Cb1 connect the other end of the first resistance R1 jointly; The other end of the grid of the 3rd nmos pass transistor M4a, the other end of the second electric capacity C2, the 4th electric capacity Cb2 connects the other end of the second resistance R2 jointly;

Six, the grid of the 7th PMOS transistor M5, M6 connects the drain electrode of the 8th PMOS transistor M7 and the source electrode of the tenth PMOS transistor M9 jointly; Ten, the grid of the 11 PMOS transistor M9, M10 meets the 4th bias voltage Vb4 jointly; Eight, the grid of the 9th PMOS transistor M7, M8 meets the 3rd bias voltage Vb3 jointly; The drain electrode of the 6th PMOS transistor M5 connects the source electrode of the 8th PMOS transistor M7; The drain electrode of the 7th PMOS transistor M6 connects the source electrode of the 9th PMOS transistor M8; The drain electrode of the 9th PMOS transistor M8, the source electrode of the 11 PMOS transistor M10 meet output end vo ut jointly;

Choose the second to the 3rd PMOS transistor M1a, the gate input Vp and the 4th of M1b is to the 5th PMOS transistor M2a, the gate input Vn of M2b, input difference mode signal Vin+ and Vin-respectively, pass through: comprise the second to the 5th PMOS transistor M1a, M1b, M2a, the transconductance input stage gm1 of M2b, comprise second, 4th to the 6th nmos pass transistor M3b, M4b, M11, the cascode level of M12, and comprise the 6th to the 11 PMOS transistor M5, M6, M7, M8, M9, the amplification of the loop collapsing cascade amplifying stage that the plus and blowup level of M10 is formed jointly, then pass through by four electric capacity C1, C2, Cb1, Cb2 and two resistance R1, the electromagnetic interference killer stage that R2 is formed, filter spurious signal, utilizing first to the 6th nmos pass transistor M3a, M3b, M4a, M4b, M11, M12 to strengthen Slew Rate simultaneously, then through comprising transistor M5 ~ M10 output stage, being outputed signal by high voltage amplitude of oscillation output end vo ut.