CN107241086A - A kind of Fully-differential low-power-consumptiolow-noise comparator of high tension apparatus work at lower voltages - Google Patents
A kind of Fully-differential low-power-consumptiolow-noise comparator of high tension apparatus work at lower voltages Download PDFInfo
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- CN107241086A CN107241086A CN201710518378.4A CN201710518378A CN107241086A CN 107241086 A CN107241086 A CN 107241086A CN 201710518378 A CN201710518378 A CN 201710518378A CN 107241086 A CN107241086 A CN 107241086A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
Abstract
The invention discloses a kind of Fully-differential low-power-consumptiolow-noise comparator of high tension apparatus work at lower voltages, it includes preposition fully-differential amplifier, current limliting phase inverter and regeneration positive feed-back latch, preposition fully-differential amplifier includes the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube and the 4th NMOS tube, second PMOS and the 3rd PMOS interconnect and form negative resistance, the resistance of itself and the first PMOS and the 4th PMOS is cancelled out each other so that the gain of preamplifier is greatly improved；Current limliting phase inverter is used to carry out the output signal of preposition fully-differential amplifier two grades of amplifications；The analog signal that regeneration positive feed-back latch is used to export current limliting phase inverter is converted to data signal.The present invention is realized increases the gain of preamplifier under low current conditions, improves the regeneration positive feedback speed of rearmounted latch, and realizes the high-speed, high precision signal transacting under the conditions of low supply voltage and low quiescent current.
Description
Technical field
The present invention relates to the comparator circuit that high tension apparatus is applied to low voltage circuit, more particularly to a kind of high tension apparatus work
Make Fully-differential low-power-consumptiolow-noise comparator at lower voltages.
Background technology
In the prior art, conventional full-difference CMOS clock control comparator circuit structure refer to Fig. 1 to Fig. 3, in order to
Reduce quiescent dissipation, be generally made up of a preamplifier and a rearmounted latch, wherein preamplifier be used for will be defeated
Enter the difference amplification of signal and reference voltage, in order to realize high ratio compared with the multiplication factor of preamplifier is general left in 10dB
The right side, and the signal after amplification is realized quick upset by rearmounted latch by the regeneration positive feedback of clock control, is compared with producing
Device output result.Several cmos clocks control comparator cited by Fig. 1 to Fig. 3, under normal process and normal power voltage
Can work, but when 5V mesohighs cmos device be used for 2.4V low supply voltage environment when, easily there arises a problem that：It is first
First, because the VTH value of 5V devices can exceed 1V, source substrate bias effect is added, causes preamplifier under low supply voltage
Can occur failure or gain is very low；Meanwhile, manufacturing cost is higher, secondly, the regeneration of rearmounted latch at low supply voltages
Positive feedback weakens, and causes comparator output switching activity very slow.Influenceed by both of these case, cause conventional clock control comparator
It is difficult to normal work under the conditions of large-drive-current.
The content of the invention
The technical problem to be solved in the present invention is, is operated in view of the shortcomings of the prior art there is provided a kind of high tension apparatus
Fully-differential low-power-consumptiolow-noise comparator under low-voltage, the gain of preamplifier is increased to realize under low current conditions, is improved
The regeneration positive feedback speed of rearmounted latch, and realize high-speed, high precision under the conditions of low supply voltage and low quiescent current
Signal transacting.
In order to solve the above technical problems, the present invention is adopted the following technical scheme that.
A kind of Fully-differential low-power-consumptiolow-noise comparator of high tension apparatus work at lower voltages, it includes preposition fully differential amplification
Device, current limliting phase inverter and regeneration positive feed-back latch, wherein：The preposition fully-differential amplifier includes the first PMOS,
Two PMOSs, the 3rd PMOS, the 4th PMOS, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube and the 4th NMOS tube,
The emitter stage of first PMOS, the emitter stage of the second PMOS, the hair of the emitter stage of the 3rd PMOS and the 4th PMOS
Emitter-base bandgap grading is all connected to high potential, the grid of second PMOS, the drain electrode of the 3rd PMOS, the drain electrode of the 4th PMOS and
The grid of four PMOSs be connected after as preposition fully-differential amplifier the first output end, the grid of first PMOS,
The drain electrode of first PMOS, the drain electrode of the second PMOS are amplified after being connected with the grid of the 3rd PMOS as preposition fully differential
Second output end of device, the drain electrode of second NMOS tube and the drain electrode of the 4th NMOS tube are all connected to preposition fully-differential amplifier
The first output end, the drain electrode and the drain electrode of the 3rd NMOS tube of first NMOS tube are all connected to preposition fully-differential amplifier
Second output end, the grid of first NMOS tube and the grid of the second NMOS tube are respectively used to receive input voltage signal, institute
State the grid of the 3rd NMOS tube and the grid of the 4th NMOS tube is respectively used to access reference voltage signal, first NMOS tube
Source electrode, the source electrode of the second NMOS tube, the source electrode of the source electrode of the 3rd NMOS tube and the 4th NMOS tube are all connected to low potential；The limit
Stream phase inverter is connected to the first output end and the second output end of preposition fully-differential amplifier, and the current limliting phase inverter is used for preceding
The output signal for putting fully-differential amplifier carries out two grades of amplifications；The regeneration positive feed-back latch is connected to the of current limliting phase inverter
One output end and the second output end, the analog signal that the regeneration positive feed-back latch is used to export current limliting phase inverter are converted to
Data signal.
Preferably, the preposition fully-differential amplifier also includes the first current limliting NMOS tube and the second current limliting NMOS tube, institute
State the source electrode of the first NMOS tube and the source electrode of the second NMOS tube is all connected to the drain electrode of the first current limliting NMOS tube, the described 3rd
The source electrode of NMOS tube and the source electrode of the 4th NMOS tube are all connected to the drain electrode of the second current limliting NMOS tube, the first current limliting NMOS tube
Source electrode and the source electrode of the second current limliting NMOS tube be all connected to low potential, the grid and the second current limliting of the first current limliting NMOS tube
The grid of NMOS tube is used to access Current limited Control signal.
Preferably, the current limliting phase inverter includes the 5th PMOS, the 6th PMOS, the 5th NMOS tube and the 6th NMOS
Pipe, the source electrode of the 5th PMOS and the source electrode of the 6th PMOS are all connected to high potential, the grid of the 5th PMOS
Be all connected to the first output end of preposition fully-differential amplifier with the grid of the 5th NMOS tube, the grid of the 6th PMOS and
The grid of 6th NMOS tube is all connected to the second output end of preposition fully-differential amplifier, the source electrode of the 5th NMOS tube and
The source electrode of six NMOS tubes is all connected to low potential, after the drain electrode of the 5th PMOS and the drain electrode of the 5th NMOS tube are connected with each other
As the first output end of current limliting phase inverter, make after the drain electrode of the 6th PMOS and the drain electrode interconnection of the 6th NMOS tube
For the second output end of current limliting phase inverter.
Preferably, the current limliting phase inverter also includes the 3rd current limliting NMOS tube, the source electrode of the 5th NMOS tube and
The source electrode of six NMOS tubes is all connected to the drain electrode of the 3rd current limliting NMOS tube, and the source electrode of the 3rd current limliting NMOS tube connects low electricity
Position, the grid of the 3rd current limliting NMOS tube is used to access Current limited Control signal.
Preferably, the regeneration positive feed-back latch includes the 7th PMOS, the 8th PMOS, the 9th PMOS, the
Seven NMOS tubes and the 8th NMOS tube, the source electrode of the 7th PMOS are connected to high potential, and the grid of the 7th PMOS is used
In access reseting controling signal, the source electrode of the 8th PMOS and the source electrode of the 9th PMOS are all connected to the 7th PMOS
Drain electrode, the source electrode of the 7th NMOS tube and the source electrode of the 8th NMOS tube are all connected to low potential, the leakage of the 8th PMOS
Pole, the drain electrode of the 7th NMOS tube, the grid of the grid of the 9th PMOS and the 8th NMOS tube are all connected to the of current limliting phase inverter
One output end, grid, the grid of the 7th NMOS tube, the drain electrode of the 9th PMOS and the 8th NMOS tube of the 8th PMOS
Drain electrode be all connected to the second output end of current limliting phase inverter.
In the Fully-differential low-power-consumptiolow-noise comparator of high tension apparatus work disclosed by the invention at lower voltages, the first NMOS tube,
Second NMOS tube, the 3rd NMOS tube and the 4th NMOS tube, and the first PMOS, the second PMOS, the 3rd PMOS and the 4th
PMOS constitutes preposition fully-differential amplifier, wherein the first NMOS tube, the second NMOS tube, the 3rd NMOS tube and the 4th NMOS tube
Be amplifier fully differential input to pipe, and the first PMOS, the second PMOS, the 3rd PMOS and the 4th PMOS composition are put
The output loading of big device.Negative resistance is formed due to the second PMOS and the 3rd PMOS interactive connection, itself and the first PMOS
Cancelled out each other with the resistance of the 4th PMOS so that the gain of preamplifier is greatly improved compared to existing technologies, herein
On the basis of, by being operated in amplification region and further improving signal gain as the current limliting phase inverter of second level amplifier, then
High-speed, high precision processing of the 5V devices under 2.4V low supply voltages and low quiescent current is realized using positive feed-back latch is regenerated.
Based on above-mentioned principle, the beneficial effect of the present invention compared to existing technologies is that the present invention is realized under low current conditions
Increase the gain of preamplifier, improve the regeneration positive feedback speed of rearmounted latch, reduce manufacturing cost, and realize
High-speed, high precision signal transacting under the conditions of low supply voltage and low quiescent current.
Brief description of the drawings
Fig. 1 is full-difference CMOS clock control comparator circuit schematic diagram one in the prior art.
Fig. 2 is full-difference CMOS clock control comparator circuit schematic diagram two in the prior art.
Fig. 3 is full-difference CMOS clock control comparator circuit schematic diagram three in the prior art.
Fig. 4 is the Fully-differential low-power-consumptiolow-noise comparator circuit schematic diagram that high tension apparatus of the present invention works at lower voltages.
Embodiment
The present invention is described in more detail with reference to the accompanying drawings and examples.
The invention discloses a kind of Fully-differential low-power-consumptiolow-noise comparator of high tension apparatus work at lower voltages, as shown in figure 4,
It includes preposition fully-differential amplifier 1, current limliting phase inverter 2 and regeneration positive feed-back latch 3, wherein：
The preposition fully-differential amplifier 1 include the first PMOS MP0, the second PMOS MP1, the 3rd PMOS MP2,
4th PMOS MP3, the first NMOS tube MNA, the second NMOS tube MNB, the 3rd NMOS tube MNC and the 4th NMOS tube MND, described
One PMOS MP0 emitter stage, the second PMOS MP1 emitter stage, the 3rd PMOS MP2 emitter stage and the 4th PMOS
MP3 emitter stage is all connected to high potential VDDA, the second PMOS MP1 grid, the 3rd PMOS MP2 drain electrode,
Four PMOS MP3 drain electrode is exported after being connected with the 4th PMOS MP3 grid as the first of preposition fully-differential amplifier 1
End, grid, the first PMOS MP0 drain electrode, the second PMOS MP1 drain electrode and the 3rd PMOS of the first PMOS MP0
Pipe MP2 grid be connected after as preposition fully-differential amplifier 1 the second output end, the drain electrode of the second NMOS tube MNB
Drain electrode with the 4th NMOS tube MND is all connected to the first output end of preposition fully-differential amplifier 1, the first NMOS tube MNA
Drain electrode and the 3rd NMOS tube MNC drain electrode be all connected to the second output end of preposition fully-differential amplifier 1, the first NMOS
Pipe MNA grid and the second NMOS tube MNB grid are respectively used to receive input voltage signal, the 3rd NMOS tube MNC's
Grid and the 4th NMOS tube MND grid are respectively used to access reference voltage signal, the source electrode of the first NMOS tube MNA, the
Two NMOS tube MNB source electrode, the 3rd NMOS tube MNC source electrode and the 4th NMOS tube MND source electrode is all connected to low potential VSSA；
The current limliting phase inverter 2 is connected to the first output end and the second output end of preposition fully-differential amplifier 1, the limit
Flowing phase inverter 2 is used to carry out the output signal of preposition fully-differential amplifier 1 two grades of amplifications；
The regeneration positive feed-back latch 3 is connected to the first output end and the second output end of current limliting phase inverter 2, it is described again
The analog signal that raw positive feed-back latch 3 is used to export current limliting phase inverter 2 is converted to data signal.
In the Fully-differential low-power-consumptiolow-noise comparator of above-mentioned high tension apparatus work at lower voltages, the first NMOS tube MNA, second
NMOS tube MNB, the 3rd NMOS tube MNC and the 4th NMOS tube MND, and the first PMOS MP0, the second PMOS MP1, the 3rd
PMOS MP2 and the 4th PMOS MP3 constitutes preposition fully-differential amplifier, wherein the first NMOS tube MNA, the second NMOS tube
MNB, the 3rd NMOS tube MNC and the 4th NMOS tube MND are that the fully differential of amplifier is inputted to pipe, and the first PMOS MP0, second
PMOS MP1, the 3rd PMOS MP2 and the 4th PMOS MP3 constitute the output loading of amplifier.Due to the second PMOS MP1
Interconnected with the 3rd PMOS MP2 and form negative resistance, its resistance phase with the first PMOS MP0 and the 4th PMOS MP3
Mutually offset so that the gain of preamplifier is greatly improved for (such as Fig. 1) compared with prior art, on this basis, passes through work
Make in amplification region and further improve signal gain as the current limliting phase inverter 2 of second level amplifier, recycle regeneration positive and negative
Feedback latch 3 realizes high-speed, high precision processing of the 5V devices under 2.4V low supply voltages and low quiescent current.Based on above-mentioned original
Reason, the beneficial effect of the present invention compared to existing technologies is that the present invention is realized before increasing under low current conditions and put
The gain of big device, improves the regeneration positive feedback speed of rearmounted latch, reduces manufacturing cost, and realize in low power supply
Voltage and the high-speed, high precision signal transacting under the conditions of low quiescent current.
In preferred scheme of the present invention, it is assumed that NMOS is identical with PMOS internal resistance, then the gain of preposition fully-differential amplifier
Estimation is as follows：
By contrast, the gain of preamplifier is in prior art (by taking Fig. 1 as an example)：
By contrast, the preposition at least order of magnitude greater left side of fully-differential amplifier ratio of gains prior art of the present invention
It is right.
As a kind of preferred embodiment, in order to play a part of current limliting and reduction power consumption, the preposition fully-differential amplifier 1 is also
Include the first current limliting NMOS tube MN0 and the second current limliting NMOS tube MN1, the source electrode and the 2nd NMOS of the first NMOS tube MNA
Pipe MNB source electrode is all connected to the first current limliting NMOS tube MN0 drain electrode, the source electrode and the 4th NMOS of the 3rd NMOS tube MNC
Pipe MND source electrode is all connected to the second current limliting NMOS tube MN1 drain electrode, the source electrode and second of the first current limliting NMOS tube MN0
Current limliting NMOS tube MN1 source electrode is all connected to low potential VSSA, the first current limliting NMOS tube MN0 grid and the second current limliting
NMOS tube MN1 grid is used to access Current limited Control signal.
In the present embodiment, the current limliting phase inverter 2 includes the 5th PMOS MP4, the 6th PMOS MP5, the 5th NMOS
Pipe MNE and the 6th NMOS tube MNF, the source electrode of the 5th PMOS MP4 and the 6th PMOS MP5 source electrode are all connected to high electricity
Position VDDA, the grid of the 5th PMOS MP4 and the 5th NMOS tube MNE grid are all connected to preposition fully-differential amplifier 1
The first output end, the grid of the 6th PMOS MP5 and the 6th NMOS tube MNF grid are all connected to preposition fully differential and put
Second output end of big device 1, the source electrode of the 5th NMOS tube MNE and the 6th NMOS tube MNF source electrode are all connected to low potential
VSSA, the 5th PMOS MP4 drain electrode and the 5th NMOS tube MNE drain electrode are used as current limliting phase inverter 2 after being connected with each other
First output end, the drain electrode of the 6th PMOS MP5 and the 6th NMOS tube MNF drain electrode are anti-phase as current limliting after being connected with each other
Second output end of device 2.
Further, the current limliting phase inverter 2 also includes the 3rd current limliting NMOS tube MN2, the 5th NMOS tube MNE's
Source electrode and the 6th NMOS tube MNF source electrode are all connected to the 3rd current limliting NMOS tube MN2 drain electrode, the 3rd current limliting NMOS tube
MN2 source electrode connection low potential VSSA, the 3rd current limliting NMOS tube MN2 grid are used to access Current limited Control signal.
In above-mentioned current limliting phase inverter 2, the 5th NMOS tube MNE, the 6th NMOS tube MNF, the 5th PMOS MP4, the 6th PMOS
Pipe MP5 and the 3rd current limliting NMOS tube MN2 partner and are biased in the phase inverter of amplification region, and this constitutes the second level to current limliting phase inverter
Amplifier, secondary amplification is made for the output signal to preposition fully-differential amplifier, meanwhile, the 3rd current limliting NMOS tube of bottom
MN2 also acts current limliting, reduces the effect of power consumption.
In preferred scheme of the present invention, it is assumed that NMOS and PMOS internal resistance and mutual conductance is all identical, then the amplification of current limliting phase inverter 2
Gain is estimated as：
A2≈(gmNE+gmP4)*(rO, P4//rO, NE)≈gm*ro：
As can be seen here, after dual-stage amplifier, total gain is substantially increased：
In the present embodiment, the regeneration positive feed-back latch 3 includes the 7th PMOS MP6, the 8th PMOS MP7, the
Nine PMOS MP8, the 7th NMOS tube MN4 and the 8th NMOS tube MN5, the source electrode of the 7th PMOS MP6 are connected to high potential
VDDA, the 7th PMOS MP6 grid are used to access reseting controling signal, the source electrode of the 8th PMOS MP7 and the
Nine PMOS MP8 source electrode is all connected to the 7th PMOS MP6 drain electrode, the source electrode and the 8th of the 7th NMOS tube MN4
NMOS tube MN5 source electrode is all connected to low potential VSSA, drain electrode, the 7th NMOS tube MN4 leakage of the 8th PMOS MP7
The grid of pole, the 9th PMOS MP8 grid and the 8th NMOS tube MN5 is all connected to the first output end of current limliting phase inverter 2, institute
State the 8th PMOS MP7 grid, the 7th NMOS tube MN4 grid, the 9th PMOS MP8 drain electrode and the 8th NMOS tube MN5
Drain electrode be all connected to the second output end of current limliting phase inverter 2.
Wherein, the 7th NMOS tube MN4, the 8th NMOS tube MN5, the 7th PMOS MP6, the 8th PMOS MP7 and the 9th
PMOS MP8 constitutes the latch with regeneration positive feedback function, the simulation that the latch is exported after can effectively two-stage be amplified
Signal, which accelerates upset, turns into data signal.
The Fully-differential low-power-consumptiolow-noise comparator of high tension apparatus work disclosed by the invention at lower voltages, its actual application
Refer to following examples.
Embodiment one
Fully differential high-precision low-power consumption comparator in the present embodiment, is mainly used in the high-speed ADC of fingerprint recognition chip
On, comparator during as Analog-digital Converter.Because ADC clock frequency is that in 12MHz to 20MHz, i.e. the clock cycle is big
About 50nsec to 83.33nsec, it is assumed that clock is 50% dutycycle, then the high-speed comparator in ADC just must be
The comparison from signal is completed in 25nsec to 41.67nsec, the processes such as upset latch are amplified to.It is particular in that, works as fingerprint
When identification chip uses 5V CMOS technology, its minimum power supply voltage, is about 2.4V, in this case, is put by multistage current limliting
Greatly, not only substantially increase the gain of signal and reduce the power consumption of high-speed transitions, and also greatly speeded up by the raising of gain
The reversal rate of latch etc..
Tested by actual emulation, the comparator that the present embodiment is proposed compared with prior art in comparator, same defeated
Learnt after entering the simulation data comparison of wave shape under signal conditioning, when at comparator two ends, input signal difference has 1mV saltus step, i.e.,
(VIP-VIN)-(VREFP-VREFNDuring)=± 1mV, comparator failure of the prior art, output result is not overturn, and this implementation
Example comparator but can normal work, output result can effectively overturn.
In addition, the output switching activity and time delay simulation result of the present embodiment comparator are shown：Under the various condition changes of PVT,
When input has 1mV difference, output result is turned to from clock (reset), the delay of upset is 2.2nsec to the maximum, but
When input has -1mV difference, output result is turned to from clock (reset), the delay of upset is 2.3nsec to the maximum, by
This is visible, and the processing speed of the present embodiment comparator is very high.
The Fully-differential low-power-consumptiolow-noise comparator of high tension apparatus work disclosed by the invention at lower voltages, it is realized in low electricity
Increase the gain of preamplifier under the conditions of stream, improve the regeneration positive feedback speed of rearmounted latch, and realize low
Supply voltage and the high-speed, high precision signal transacting under the conditions of low quiescent current.
Simply preferred embodiments of the present invention described above, are not intended to limit the invention, all technology models in the present invention
Interior done modification, equivalent substitution or improvement etc. are enclosed, be should be included in the range of of the invention protect.
Claims (5)
1. the Fully-differential low-power-consumptiolow-noise comparator of a kind of high tension apparatus work at lower voltages, it is characterised in that include preposition complete
Difference amplifier (1), current limliting phase inverter (2) and regeneration positive feed-back latch (3), wherein：：
The preposition fully-differential amplifier (1) includes the first PMOS (MP0), the second PMOS (MP1), the 3rd PMOS
(MP2), the 4th PMOS (MP3), the first NMOS tube (MNA), the second NMOS tube (MNB), the 3rd NMOS tube (MNC) and the 4th
NMOS tube (MND), the emitter stage of first PMOS (MP0), the emitter stage of the second PMOS (MP1), the 3rd PMOS
(MP2) emitter stage and the emitter stage of the 4th PMOS (MP3) is all connected to high potential (VDDA), second PMOS
(MP1) grid, the drain electrode of the 3rd PMOS (MP2), the grid of the drain electrode of the 4th PMOS (MP3) and the 4th PMOS (MP3)
Pole be connected after as preposition fully-differential amplifier (1) the first output end, the grid of first PMOS (MP0), first
Before drain electrode, the drain electrode of the second PMOS (MP1) of PMOS (MP0) are used as after being connected with the grid of the 3rd PMOS (MP2)
Put the second output end of fully-differential amplifier (1), the drain electrode of second NMOS tube (MNB) and the leakage of the 4th NMOS tube (MND)
Pole is all connected to the first output end of preposition fully-differential amplifier (1), the drain electrode of first NMOS tube (MNA) and the 3rd NMOS
The drain electrode of pipe (MNC) is all connected to the second output end of preposition fully-differential amplifier (1), the grid of first NMOS tube (MNA)
The grid of pole and the second NMOS tube (MNB) be respectively used to receive input voltage signal, the grid of the 3rd NMOS tube (MNC) and
The grid of 4th NMOS tube (MND) is respectively used to access reference voltage signal, the source electrode of first NMOS tube (MNA), second
The source electrode of the source electrode of NMOS tube (MNB), the source electrode of the 3rd NMOS tube (MNC) and the 4th NMOS tube (MND) is all connected to low potential
(VSSA)；
The current limliting phase inverter (2) is connected to the first output end and the second output end of preposition fully-differential amplifier (1), the limit
Flowing phase inverter (2) is used to carry out the output signal of preposition fully-differential amplifier (1) two grades of amplifications；
The regeneration positive feed-back latch (3) is connected to the first output end and the second output end of current limliting phase inverter (2), it is described again
Raw positive feed-back latch (3) is used to the analog signal that current limliting phase inverter (2) is exported being converted to data signal.
2. the Fully-differential low-power-consumptiolow-noise comparator of high tension apparatus work as claimed in claim 1 at lower voltages, it is characterised in that
The preposition fully-differential amplifier (1) also includes the first current limliting NMOS tube (MN0) and the second current limliting NMOS tube (MN1), described
The source electrode of first NMOS tube (MNA) and the source electrode of the second NMOS tube (MNB) are all connected to the leakage of the first current limliting NMOS tube (MN0)
Pole, the source electrode of the 3rd NMOS tube (MNC) and the source electrode of the 4th NMOS tube (MND) are all connected to the second current limliting NMOS tube
(MN1) source electrode of drain electrode, the source electrode of the first current limliting NMOS tube (MN0) and the second current limliting NMOS tube (MN1) is all connected to
The grid of low potential (VSSA), the grid of the first current limliting NMOS tube (MN0) and the second current limliting NMOS tube (MN1) is used to connect
Enter Current limited Control signal.
3. the Fully-differential low-power-consumptiolow-noise comparator of high tension apparatus work as claimed in claim 1 at lower voltages, it is characterised in that
The current limliting phase inverter (2) includes the 5th PMOS (MP4), the 6th PMOS (MP5), the 5th NMOS tube (MNE) and the 6th
NMOS tube (MNF), the source electrode of the 5th PMOS (MP4) and the source electrode of the 6th PMOS (MP5) are all connected to high potential
(VDDA), the grid of the 5th PMOS (MP4) and the grid of the 5th NMOS tube (MNE) are all connected to preposition fully differential amplification
Before first output end of device (1), the grid of the 6th PMOS (MP5) and the grid of the 6th NMOS tube (MNF) are all connected to
Put the second output end of fully-differential amplifier (1), the source electrode of the 5th NMOS tube (MNE) and the source of the 6th NMOS tube (MNF)
Pole is all connected to low potential (VSSA), and the drain electrode of the 5th PMOS (MP4) is mutually interconnected with the drain electrode of the 5th NMOS tube (MNE)
As the first output end of current limliting phase inverter (2) after connecing, the drain electrode of the 6th PMOS (MP5) and the 6th NMOS tube (MNF)
Drain electrode be connected with each other after as current limliting phase inverter (2) the second output end.
4. the Fully-differential low-power-consumptiolow-noise comparator of high tension apparatus work as claimed in claim 3 at lower voltages, it is characterised in that
The current limliting phase inverter (2) also includes the 3rd current limliting NMOS tube (MN2), the source electrode and the 6th of the 5th NMOS tube (MNE)
The source electrode of NMOS tube (MNF) is all connected to the drain electrode of the 3rd current limliting NMOS tube (MN2), the 3rd current limliting NMOS tube (MN2)
Source electrode connection low potential (VSSA), the grid of the 3rd current limliting NMOS tube (MN2) is used to access Current limited Control signal.
5. the Fully-differential low-power-consumptiolow-noise comparator of high tension apparatus work as claimed in claim 1 at lower voltages, it is characterised in that
It is described regeneration positive feed-back latch (3) include the 7th PMOS (MP6), the 8th PMOS (MP7), the 9th PMOS (MP8),
7th NMOS tube (MN4) and the 8th NMOS tube (MN5), the source electrode of the 7th PMOS (MP6) are connected to high potential (VDDA),
The grid of 7th PMOS (MP6) is used to access reseting controling signal, the source electrode and the 9th of the 8th PMOS (MP7)
The source electrode of PMOS (MP8) is all connected to the drain electrode of the 7th PMOS (MP6), the source electrode of the 7th NMOS tube (MN4) and
The source electrode of eight NMOS tubes (MN5) is all connected to low potential (VSSA), the drain electrode of the 8th PMOS (MP7), the 7th NMOS tube
(MN4) drain electrode, the grid of the 9th PMOS (MP8) and the grid of the 8th NMOS tube (MN5) is all connected to current limliting phase inverter (2)
The first output end, the grid of the 8th PMOS (MP7), the grid of the 7th NMOS tube (MN4), the 9th PMOS (MP8)
Drain electrode and the drain electrode of the 8th NMOS tube (MN5) be all connected to the second output end of current limliting phase inverter (2).
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| CN107944099A (en) * | 2017-11-10 | 2018-04-20 | 东南大学 | A kind of high-speed, high precision comparator circuit design |
| CN111130511A (en) * | 2018-10-30 | 2020-05-08 | 西安电子科技大学 | All-digital low-voltage low-power-consumption clock-controlled voltage comparator |
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| CN107944099A (en) * | 2017-11-10 | 2018-04-20 | 东南大学 | A kind of high-speed, high precision comparator circuit design |
| CN107944099B (en) * | 2017-11-10 | 2021-12-07 | 东南大学 | High-speed high-precision comparator circuit design |
| CN107800413A (en) * | 2017-11-20 | 2018-03-13 | 北京华大九天软件有限公司 | A kind of low imbalance high speed dynamic comparer |
| CN107800413B (en) * | 2017-11-20 | 2020-04-21 | 北京华大九天软件有限公司 | Low-offset high-speed dynamic comparator |
| CN111130511A (en) * | 2018-10-30 | 2020-05-08 | 西安电子科技大学 | All-digital low-voltage low-power-consumption clock-controlled voltage comparator |
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