CN112910452A - Low-offset low-power-consumption high-speed dynamic comparator and application thereof - Google Patents
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Abstract
The invention relates to a low-offset low-power-consumption high-speed dynamic comparator and application thereof, belonging to the field of semiconductor integrated circuit design, wherein the comparator comprises a pre-amplifying circuit, a latch and a phase inverter; the preamplifier comprises a clock control end, two input signals Vip and Vin and two output signals Vop and Von, wherein the preamplifier is connected with a direct-current power supply, Vop is a signal obtained by amplifying Vip through the preamplifier, and Von is a signal obtained by amplifying Vin through the preamplifier; the latch is connected to Vop and Von, and latches these two signals and transmits the output signal to the inverter, and the inverter shapes the voltage signal and supplies it to the next stage.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit design, and particularly relates to a low-offset low-power-consumption high-speed dynamic comparator.
Background
With the widespread application of modern communication and signal processing technologies, high-speed and low-power electronic devices become the mainstream of the market. The comparator is an important component of a plurality of circuits such as an analog-to-digital converter, an amplifier, a low dropout regulator and the like, and has important influence on the performance index of the system.
The traditional double-tail dynamic comparator is the simplest Latch structure, as shown in fig. 2, the main principle is that positive feedback of voltage is utilized to compare input signals, the illustrated pre-amplification stage and the Latch form the dynamic comparator together, a pre-stage amplifier pre-amplifies a differential input model Vin/Vip, and fn and fp are differential outputs. The Clkc signal and the Clkc1 signal are in opposite phases. When Clkc is low, it is reset stage, nodes fn, fp are precharged to the power supply voltage, Latch outputs Von, Vop are 0. When the Clkc point is higher, the regeneration stage, fn and fp start to discharge, and the speed of discharge is different due to the difference of input voltage. When the voltage at the fast end approaches the threshold value of the Latch input tube, the corresponding input tube is conducted and amplified. When the voltage of the output nodes Von and Vop rises to the threshold, the positive feedback starts to act, one end of the output is quickly raised to VDD by the positive feedback according to the discharge speed, and the other end of the output is pulled down to the ground. However, the open loop gain of the preamplifier with the structure is small, so that the precision of the dynamic comparator is low, the offset voltage is large, and meanwhile, the tail current and two opposite clock signals are introduced into the structure, so that the power consumption of the transistor is improved.
Disclosure of Invention
In order to solve the deficiencies of the prior art, the first objective of the present invention is to provide a low-offset low-power-consumption high-speed dynamic comparator, and the second objective is to provide an application of the dynamic comparator. The comparator has high precision, small offset voltage and low power consumption.
In order to achieve the purpose, the invention adopts the specific scheme that:
a low offset low power high speed dynamic comparator includes a preamplifier, a latch and an inverter;
the preamplifier includes: the clock control module I, a first differential signal input end, a second differential input end, an output node Di +, an output node Di-and a cross coupling module; the clock control module I receives a clock control signal CLK; the first differential signal input end is connected to a first differential input signal Vip through a third MOS transistor, and the second differential signal input end is connected to a second differential input signal Vin through a fourth MOS transistor; the cross coupling module comprises a fifth MOS tube, a sixth MOS tube, a seventh MOS tube and an eighth MOS tube; the output signal of the preamplifier is transmitted to a latch through an output node Di + and an output node Di-;
the source electrodes of the first MOS tube and the second MOS tube are connected with GND, and the grid electrodes of the first MOS tube and the second MOS tube are connected with a clock control signal; the drain electrode of the first MOS tube is connected with the source electrode of the third MOS tube, and the drain electrode of the second MOS tube is connected with the source electrode of the fourth MOS tube; the grid electrode of the third MOS tube is connected with the first differential input signal Vip, and the grid electrode of the fourth MOS tube is connected with the second differential input signal Vin; the drain electrode of the third MOS tube is connected with the source electrode of the fifth MOS tube, the source electrode of the sixth MOS tube and the grid electrode of the seventh MOS tube, and the drain electrode of the fourth MOS tube is connected with the source electrode of the seventh MOS tube, the source electrode of the eighth MOS tube and the grid electrode of the sixth MOS tube; the drain electrodes of the fifth MOS tube, the sixth MOS tube, the seventh MOS tube and the eighth MOS tube are connected with VDD; and the grids of the fifth MOS tube and the eighth MOS tube are connected with a clock control signal.
The latch includes: the clock control module II, the tail current module, the PMOS latch module, the NMOS latch module and the current control module; the clock control module II receives a clock control signal CLK through a seventeenth MOS tube; the tail current module comprises a ninth MOS tube and a twelfth MOS tube, and receives an output signal from the preamplifier through the grids of the ninth MOS tube and the twelfth MOS tube; the thirteenth MOS tube and the fourteenth MOS tube form a PMOS latch; the eleventh MOS transistor and the tenth MOS transistor form an NMOS latch; the fifteenth MOS tube and the sixteenth MOS tube form a current control module;
the source electrodes of the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube and the twelfth MOS tube are connected with GND; the grid electrode of the ninth MOS tube is connected with the grid electrode of the fifteenth MOS tube, and the grid electrode of the twelfth MOS tube is connected with the grid electrode of the sixteenth MOS tube; the drain electrode of the ninth MOS tube, the drain electrode and the grid electrode of the tenth MOS tube, the drain electrode and the grid electrode of the eleventh MOS tube, the drain electrode of the twelfth MOS tube, the drain electrode of the thirteenth MOS tube and the drain electrode of the fourteenth MOS tube are in cross-coupled connection; a source electrode of the thirteenth MOS tube, a source electrode of the fourteenth MOS tube, a source electrode and a drain electrode of the seventeenth MOS tube, a drain electrode of the fifteenth MOS tube and a drain electrode of the sixteenth MOS tube are mutually connected; the source electrode of the fifteenth MOS tube and the source electrode of the sixteenth MOS tube are connected with VDD; the grid electrode of the seventeenth MOS tube is connected with a clock control signal;
the inverter passes through an output node out+And out-Is connected with the phase lock device.
Specifically, in the preamplifier, the third MOS transistor and the fourth MOS transistor are NMOS transistors, and the first MOS transistor, the second MOS transistor and the fifth MOS transistor to the eighth MOS transistor are PMOS transistors.
In the latch, the ninth MOS transistor to the twelfth MOS transistor are NMOS transistors, and the thirteenth MOS transistor to the seventeenth MOS transistor are PMOS transistors.
Has the advantages that:
1: m5 and M8 tubes are added in the preamplifier, so that the gain of the amplifier is improved. The cross-coupled transistors M6 and M7 increase the speed of the comparator and reduce the effect of the increase in the load capacitance at the output of the first stage on the speed of the comparator.
2: and the M17 tubes are added, so that two groups of reset tubes are reduced, and the layout area is reduced, thereby reducing the power consumption.
3: a source electrode series tube M3-4 of the cross-coupled tube M1-2 is used as an independent current source at the left branch and the right branch to replace a tail current source in the traditional topology. The connection can form a low-resistance state grounding loop at the near-ground tail part, so that low-frequency noise flows out through the loop, and phase noise of introduced noise of the tail current source, which is superposed on different frequency domains in the resonant modulation process, is effectively reduced.
Drawings
FIG. 1 is a schematic diagram of a low offset, low power consumption, high speed dynamic comparator;
FIG. 2 is a circuit diagram of a conventional dynamic comparator;
FIG. 3 is a simulation diagram of a low offset, low power consumption, high speed dynamic comparator;
FIG. 4 is a circuit diagram of a low offset, low power consumption, high speed dynamic comparator;
fig. 5 is a graph of monte carlo offset voltage simulations.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. In the description of the present invention, the first MOS transistor is M1, the second MOS transistor is M2, and the third MOS transistor is M3 … …, and so on, for simplifying the description, M1, M2, and M3 … … are all used for description in the following schemes.
A low-offset low-power high-speed dynamic comparator comprises a preamplifier, a latch and an inverter, wherein as shown in figure 1, the preamplifier is connected with a direct-current power supply, an input signal Vip is amplified by the preamplifier to obtain a signal Vop, and an input signal Vin is amplified by the preamplifier to obtain a signal Von; the Vop and Von signals are input to a latch, which latches the two signals and transmits the output signal to an inverter, which shapes the voltage signal for the next stage.
The pre-amplifying circuit amplifies the input signal in the comparison stage, and the latch circuit performs positive feedback latch on the output result of the pre-amplifying circuit to obtain a comparison result; after the comparison result is obtained, an externally input comparison completion signal turns off a CMOS transmission gate in the pre-amplification circuit, the pre-amplification stage control circuit turns off a tail current tube in the pre-amplification circuit, and high-level or low-level setting is carried out on an output node of the pre-amplification circuit according to the comparison result, so that the latch circuit is guaranteed to keep the comparison result.
The circuit diagram of the dynamic comparator is shown in fig. 4.
The preamplifier includes: the clock control module I, the first differential signal input end, the second differential input end, the output node Di +, the output node Di-and the cross coupling module. The clock control module I is used for receiving a control clock signal CLK, and the first differential signal input end and the second differential signal input end are respectively used for accessing a first differential input signal Vip and a second differential input signal Vin. The cross-coupling module comprises MOS transistors such as M5-M8. M3-M4 tubes in the preamplifier are NMOS tubes, and M1-M2 tubes and M5-M8 tubes in the preamplifier are PMOS tubes.
In more detail, a current cancellation technique is used to obtain a larger gain, wherein M6 and M7 are cross-coupled to obtain a positive feedback amplifier, and as a result, the differential resistance thereof becomes negative, and the circuit structure has a current series negative feedback loop and a voltage parallel negative feedback loop. When the coefficient of positive feedback is smaller than the feedback coefficient, the whole loop shows negative feedback, the preposed operational amplifier shows the effect of the traditional operational amplifier, and has no hysteresis function; when the voltage parallel positive feedback coefficient is larger than the current series negative feedback coefficient, the whole loop shows positive feedback, the whole presents the characteristic of a positive feedback comparator, and the hysteresis effect is shown in the transmission function. The cross-coupled transistors M6 and M7 increase the speed of the comparator and reduce the effect of the increase in the load capacitance at the output of the first stage on the speed of the comparator.
The latch includes: the device comprises a clock control module II, a tail current module, a PMOS latch module, an NMOS latch module and a current control module. The clock control module is M17 and is used for receiving a clock signal CLK; the tail current modules are M9 and M12, and the gates of M9 and M12 are used for receiving the output signals from the preamplifier; m13 and M14 constitute PMOS latches, M11 and M10 constitute NMOS latches; m15 and M16 constitute a current control module. Wherein M9-M12 are NMOS transistors, and M13-M17 are PMOS transistors.
In more detail, the original reset tube is replaced by a P-channel metal oxide semiconductor (PMOS) tube M17, so that the charge reuse is realized, the delay time is shortened, and the power consumption is reduced. M9-M17 form a latch comparator; m17 is a reset tube; when the Clock (CLK) is at low level, M17 is conducted to make the voltages of two points M and N equal, so as to avoid the residual charges of two points M and N being unequal, thereby affecting the precision of the comparator. The SR latch circuit is a simplest latch consisting of four cross-coupled M10, M11, M13 and M14MOS tubes. The PMOS latch is arranged on the upper surface, the NMOS latch is arranged on the lower surface, and the two latches are in a symmetrical structure, so that the problem of offset voltage offset of the input of the comparator is solved.
In order to reduce noise and offset, the comparator divides the tail current tube of the second stage circuit of the traditional double-tail comparator into two transistors M9 and M12, and a pair of reset tubes M10 and M11 are added. This increases the parasitic capacitance at nodes DI + and DI-affecting the speed of the first stage circuit and thus the overall speed of the comparator.
The present embodiment provides two phases of reset and latch.
In a reset stage, CLK is at a low level, MOS transistors M1 and M2 are cut off, M5 and M8 are conducted, and a preamplifier charges a node Di (Di + and Di-) to VDD; m15 and M16 are turned off, M9 and M12 are turned on, nodes out and out are pulled down to zero potential (GND), the SR latch is in a holding state, and the output of the comparator keeps the previous state unchanged; the reset tube MP5 is turned on to equalize the voltage at the node M, N, and M10, M11, M13, and M14 are cross-coupled latches, and are all turned off at this time.
In the latch phase, CLK is high, MOS transistors M1 and M2 are turned on, M5 and M8 are turned off, and nodes Di-and Di + are discharged at different rates according to the difference of input signals Vip and Vin, and the time for discharging the node Di to VDD-VTHP is T1. MP6, MP7 charge node M, N, respectively, with current ID 2. At this time, M13, M14 are still turned off, Vout (Vout + and Vout-) is equal to GND, M9, M12 operate in the deep linear region, and the current is almost 0. When VM and VN are charged to | VTHP |, M13 and M14 are turned on, and the time when VM and VN reach | VTHP |, is recorded as T2. Nodes out + and out-are charged with currents ID 2-ID 3, noting that the time at which Vout reaches VTHN is T3. When Vout reaches VTHN, M5 and M6 start to conduct, and the latch constituted by M10 and M11, and M13 and M14 starts to operate. Since nodes Di-and Di + are discharged at different rates, there is necessarily a slight difference between VDi-and VDi + at the same time, which causes a voltage difference between Vout + and Vout-, denoted as Δ Vout, which is used as the initial voltage difference of the latch, and is rapidly amplified to VDD-GND, driving SR latch set 0 or 1, i.e. the output of the comparator. The time required for the latch regeneration process is denoted as T4. The corresponding time of the comparator is the sum of all times of T1, T2, T3, and T4.
The comparator is reset again, the CLK jumps to a low level, the MOS tubes M1 and M2 are cut off, M5 and M8 are conducted, and the node Di is charged to VDD; m15 and M16 are turned off, M9 and M12 are turned on, and nodes out + and out-are discharged to GND through M9 and M12; the voltages of the nodes M and N are equal because the reset tube M17 is conducted, and are discharged through the branches M13 and M14 and the branches M9 and M12 respectively; when the voltage at node M, N discharges to | VTHP |, M13, M14 turn off, ignoring the sub-threshold conduction characteristic, the voltage at M, N eventually remains constant at | VTHP |. When the comparator is in the regeneration state again, the comparator saves time T2 during the regeneration phase and avoids charging node M, N again, since the voltage at node M, N is already | VTHP |.
From the results of FIG. 3 and FIG. 5, it can be seen that the comparator has a faster response speed at 1GHz clock control signal and a smaller offset voltage when 200 Monte Carlo simulations are performed.
It should be noted that the above-mentioned embodiments illustrate rather than limit the scope of the invention, which is defined by the appended claims. It will be apparent to those skilled in the art that certain insubstantial modifications and adaptations of the present invention can be made without departing from the spirit and scope of the invention.
Claims (5)
1. A low-offset low-power-consumption high-speed dynamic comparator comprises a preamplifier, a latch and an inverter, and is characterized in that:
the preamplifier includes: the clock control module I, a first differential signal input end, a second differential input end, an output node Di +, an output node Di-and a cross coupling module; the clock control module I receives a control clock signal CLK; the first differential signal input end is connected to a first differential input signal Vip through a third MOS transistor, and the second differential signal input end is connected to a second differential input signal Vin through a fourth MOS transistor; the cross coupling module comprises a fifth MOS tube, a sixth MOS tube, a seventh MOS tube and an eighth MOS tube; the output signal of the preamplifier is transmitted to a latch through an output node Di + and an output node Di-;
the source electrodes of the first MOS tube and the second MOS tube are connected with GND, and the grid electrodes of the first MOS tube and the second MOS tube are connected with a clock control signal; the drain electrode of the first MOS tube is connected with the source electrode of the third MOS tube, and the drain electrode of the second MOS tube is connected with the source electrode of the fourth MOS tube; the grid electrode of the third MOS tube is connected with the first differential input signal Vip, and the grid electrode of the fourth MOS tube is connected with the second differential input signal Vin; the drain electrode of the third MOS tube is connected with the source electrode of the fifth MOS tube, the source electrode of the sixth MOS tube and the grid electrode of the seventh MOS tube, and the drain electrode of the fourth MOS tube is connected with the source electrode of the seventh MOS tube, the source electrode of the eighth MOS tube and the grid electrode of the sixth MOS tube; the drain electrodes of the fifth MOS tube, the sixth MOS tube, the seventh MOS tube and the eighth MOS tube are connected with VDD; the grid electrodes of the fifth MOS tube and the eighth MOS tube are connected with a clock control signal;
the latch includes: the clock control module II, the tail current module, the PMOS latch module, the NMOS latch module and the current control module; the clock control module II receives a clock signal CLK through a seventeenth MOS tube; the tail current module comprises a ninth MOS tube and a twelfth MOS tube, and receives an output signal from the preamplifier through the grids of the ninth MOS tube and the twelfth MOS tube; the thirteenth MOS tube and the fourteenth MOS tube form a PMOS latch; the eleventh MOS transistor and the tenth MOS transistor form an NMOS latch; the fifteenth MOS tube and the sixteenth MOS tube form a current control module;
the source electrodes of the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube and the twelfth MOS tube are connected with GND; the grid electrode of the ninth MOS tube is connected with the grid electrode of the fifteenth MOS tube, and the grid electrode of the twelfth MOS tube is connected with the grid electrode of the sixteenth MOS tube; the drain electrode of the ninth MOS tube, the drain electrode and the grid electrode of the tenth MOS tube, the drain electrode and the grid electrode of the eleventh MOS tube, the drain electrode of the twelfth MOS tube, the drain electrode of the thirteenth MOS tube and the drain electrode of the fourteenth MOS tube are in cross-coupled connection; a source electrode of the thirteenth MOS tube, a source electrode of the fourteenth MOS tube, a source electrode and a drain electrode of the seventeenth MOS tube, a drain electrode of the fifteenth MOS tube and a drain electrode of the sixteenth MOS tube are mutually connected; the source electrode of the fifteenth MOS tube and the source electrode of the sixteenth MOS tube are connected with VDD; the grid electrode of the seventeenth MOS tube is connected with a clock control signal;
the inverter passes through an output node out+And out-Is connected with the phase lock device.
2. A low offset, low power consumption and high speed dynamic comparator according to claim 1, wherein: in the preamplifier, the third MOS tube and the fourth MOS tube are NMOS tubes, and the first MOS tube, the second MOS tube and the fifth MOS tube-the eighth MOS tube are PMOS tubes.
3. A low offset, low power consumption and high speed dynamic comparator according to claim 1, wherein: in the latch, the ninth MOS tube to the twelfth MOS tube are NMOS tubes, and the thirteenth MOS tube to the seventeenth MOS tube are PMOS tubes.
4. Use of a low offset, low power consumption high speed dynamic comparator according to any of claims 1-3 in a semiconductor integrated circuit.
5. Use according to claim 4, characterized in that: the semiconductor integrated circuit is an analog-to-digital converter comprising a dynamic comparator as claimed in any one of claims 1 to 3.
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| WO2024041437A1 (en) * | 2022-08-26 | 2024-02-29 | 深圳市中兴微电子技术有限公司 | Differential latch circuit, switch driver, and digital-to-analog conversion circuit |
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