CN101841315A - High speed comparator - Google Patents

Abstract

The invention relates to a high speed comparator, which comprises a preamplifier unit, an emitter follower unit and a latch unit. In the circuit of the invention, one emitter follower unit is arranged between the preamplifier unit and the latch unit of the traditional comparator to play a buffer role so that the input voltage needed by the latch unit can reach in a short time and the work speed of the comparator is improved. The circuit of the invention has the advantages of high speed and stable transmission delay, effectively overcomes the defects of the low speed and unstable transmission delay of the traditional comparator and can be extensively applied to the A/D conversion field of high speed and high precision.

Description

A kind of high-speed comparator

Technical field

The present invention relates to a kind of high-speed comparator, particularly a kind of high-speed comparator that is used for the high-speed high-precision flow line A/D converter.Its direct applied field is the high-speed high-precision flow line A/D converter.

Background technology

In recent years, along with pipeline a/d converter gradually to the development of high-speed, high precision direction, more and more higher to the requirement of its inside electronic circuit, particularly comparator.In pipeline a/d converter, inner comparator need be amplified to the needed logic level of subsequent conditioning circuit to this grade simulation small signal, and the result that comparator latchs will deliver to MDAC module and this grade analog input subtraction.Usually the transmission delay of comparator has taken and can be used for the time that amplifier is set up in the MDAC module, has limited the speed of whole pipeline a/d converter.

Traditional comparator as shown in Figure 1, it be one the band preamplifier the tracking latched comparator.The time of latching of comparator is:

$t=\frac{C_L}{g_M}\×\ln \left[\frac{V_O\left(t\right)}{V_O(t=0)}\right]---\left(1\right)$

Wherein, V _o=V _o ⁺-V _o ^-, g _MFor latching the mutual conductance of inverter, C _LBe the output loading of comparator, V _O(t) for the needed logic level of subsequent conditioning circuit (owing to be CMOS technology, power taking source voltage V here _DD), V _O(t=0) for latching the initial voltage of phase.In order to try to achieve V _O(t=0) occurrence is established circuit and is adopted symmetric design, that is, and and N ₁, N ₂The breadth length ratio of grid get identical value, P ₁, P ₂The breadth length ratio of grid get identical value, P ₃, P ₄The breadth length ratio of grid get identical value, N ₅, N ₆The breadth length ratio of grid get identical value.

In the phase that resets, switch N ₄Conducting, the equivalent circuit diagram of latch is output as shown in Figure 2 at this moment:

$V_O=V_i\frac{g_{N1}}{g_{P1}}\frac{g_{P3}{R}_{N4}}{2-g_{N5}{R}_{N4}}---\left(2\right)$

This voltage is the initial voltage value that latchs phase, so, for latching phase, have:

$V_O(t=0)=V_i\frac{g_{N1}}{g_{P1}}\frac{g_{P3}{R}_{N4}}{2-g_{N5}{R}_{N4}}---\left(3\right)$

By formula (1), (2), (3) formula as can be known: 1) because the existence of negative resistance, it is big that output impedance becomes, and bandwidth reduces, and it is elongated to make that the latch unit of traditional comparator obtains time of needed initial voltage, and the operating rate of traditional comparator is reduced.2) initial voltage value of the latch unit of traditional comparator and P ₃Mutual conductance, N ₄Switch resistance relevant, change with the variation of technology and operating state, this can cause the instability of the propagation delay time of traditional comparator.

Summary of the invention

For not high, the propagation delay time problem of unstable of operating rate that overcomes traditional comparator, the invention provides a kind of high-speed comparator that is used for the high-speed high-precision flow line A/D converter, and circuit of the present invention is simple in structure, easy to use.

For achieving the above object, the present invention solves the problems of the technologies described above the technical scheme of being taked and is: a kind of high-speed comparator, and it contains:

A pre-amplifier unit comprises:

PMOS manages MP ₁, PMOS manages MP ₂, NMOS manages MN ₁, NMOS manages MN ₂, NMOS manages MN ₃, wherein, MN ₁Grid meet the positive input terminal V of high-speed comparator _i ^-, MN ₂Grid meet the negative input end V of high-speed comparator _i ^-, MN ₁, MN ₂Source electrode and MN ₃Drain electrode join MN ₃Grid meet bias voltage V _Bias, MN ₃Source ground V _SS, MP ₁Grid, drain electrode and MN ₁Drain electrode join, its tie point is the negative output terminal V of pre-amplifier unit ₁ ^-, MP ₂Grid, drain electrode and MN ₂Drain electrode join, its tie point is the positive output end V of pre-amplifier unit ₁ ⁺, MP ₁, MP ₂Source electrode all meet power supply V _DDWith

An emitter follower unit comprises:

PMOS manages MP ₃, NMOS manages MN ₄, NMOS manages MN ₅, NMOS manages MN ₆, NMOS manages MN ₇, wherein, MN ₄Grid meet the negative output terminal V of pre-amplifier unit ₁ ^-, MN ₅Grid meet the positive output end V of pre-amplifier unit ₁ ⁺, MN ₄, MN ₅Drain electrode and MP ₃Grid, the drain electrode link together MP ₃Source electrode meet power supply V _DD, MN ₄Source electrode and MN ₆Drain electrode join, its tie point is the negative output terminal V of emitter follower unit ₂ ^-, MN ₅Source electrode and MN ₇Drain electrode join, its tie point is the positive output end V of emitter follower unit ₂ ⁺, MN ₆, MN ₇Grid all meet bias voltage V _Bias, MN ₆, MN ₇Source grounding V _SSWith

A latch unit comprises:

PMOS manages MP ₄, PMOS manages MP ₅, inverter INV ₁, inverter INV ₂, NMOS manages MN ₈, NMOS manages MN ₉, NMOS manages MN ₁₀, NMOS manages MN ₁₁, wherein, MN ₈Drain electrode and the positive output end V of emitter follower unit ₂ ⁺Join MN ₉Drain electrode and the negative output terminal V of emitter follower unit ₂ ^-Join MN ₈, MN ₉Grid and INV ₁Input all join MP with input end of clock CLK ₄, MP ₅Source electrode and INV ₁Output, INV ₂Input link together MN ₁₀, MN ₁₁Source electrode and INV ₂Output join MP ₄, MN ₁₀Drain electrode and MP ₅, MN ₁₁Grid and MN ₉Source electrode link together, as high-speed comparator negative output terminal V _o ^-, MP ₅, MN ₁₁Drain electrode and MP ₄, MN ₁₀Grid and MN ₈Source electrode link together, as high-speed comparator positive output end V _o ⁺

Beneficial effect:

A kind of high-speed comparator of the present invention comprises a pre-amplifier unit, an emitter follower unit and a latch unit.Compare with traditional comparator, it has following characteristics:

1. circuit of the present invention has increased an emitter follower unit on the basis of conventional comparator circuit, as cushioning effect.Because the driving force of emitter follower unit own is strong, makes circuit of the present invention at the phase time that resets, have response faster, the needed input voltage of latch can reach in the shorter time, thereby has improved the operating rate of circuit of the present invention.

2. with respect to traditional comparator, circuit of the present invention has the more stable voltage that initially latchs, thereby can obtain more stable propagation delay time.Simultaneously, because the introducing of emitter follower unit, make the circuit of the present invention recoil effect of isolated latches better.

3. circuit of the present invention has been successfully applied in 14 125MSPS pipeline a/d converters, and its test result shows that this A/D converter satisfies the design objective requirement.And traditional comparator is difficult to satisfy the requirement that is used for high speed like this, high-precision A/D converter.

Therefore, circuit of the present invention has concurrently at a high speed and the stable advantage of propagation delay time, has overcome the not high and unsettled shortcoming of propagation delay time of traditional comparator speed effectively.

Description of drawings

Fig. 1 is the circuit diagram of traditional comparator;

Fig. 2 is latch and the small-signal equivalent circuit figure thereof in traditional comparator;

Fig. 3 is the circuit diagram of high-speed comparator of the present invention.

Embodiment

The specific embodiment of the present invention is not limited only to following description, is now further specified in conjunction with the accompanying drawings.

The circuit diagram of the concrete a kind of high-speed comparator implemented of the present invention as shown in Figure 3.It is made up of a pre-amplifier unit, an emitter follower unit and a latch unit.Pre-amplifier unit comprises: PMOS manages MP ₁, PMOS manages MP ₂, NMOS manages MN ₁, NMOS manages MN ₂, NMOS manages MN ₃, this pre-amplifier unit is used to obtain higher resolution, reduces the recoil effect of latch simultaneously.The emitter follower unit comprises: PMOS manages MP ₃, NMOS manages MN ₄, NMOS manages MN ₅, NMOS manages MN ₆, NMOS manages MN ₇, this emitter follower unit further reduces the recoil effect of latch.Latch unit comprises: PMOS manages MP ₄, PMOS manages MP ₅, inverter INV ₁, inverter INV ₂, NMOS manages MN ₈, NMOS manages MN ₉, NMOS manages MN ₁₀, NMOS manages MN ₁₁, this latch unit amplifies the output signal of emitter follower and latchs.

Concrete annexation among Fig. 3, interactively are identical with the summary of the invention part of this specification, no longer repeat herein.Its operation principle is as follows:

Circuit of the present invention is to have added an emitter follower unit as buffer memory between the preamplifier of traditional comparator and latch.In the phase that resets, promptly clock CLK is a high level, clock switch MN ₈, MN ₉Conducting, though latch is the load of emitter follower, this moment, clock made latch reset by inverter, each transistor MP of latch ₄, MP ₅, MN ₁₀, MN ₁₁Be in cut-off state, can not introduce negative impedance.Simultaneously, because the driving force of emitter follower own is strong, make circuit of the present invention respond resetting to have faster with respect to traditional comparator, the needed input voltage of latch can reach in the shorter time, has improved the operating rate of comparator.

As seen, in the phase that resets, each transistor MP of latch ₄, MP ₅, MN ₁₀, MN ₁₁Be in by state, the gain of emitter follower is 1, and the gain of entire circuit is only provided by preamplifier, because circuit of the present invention adopts symmetric design, i.e. M _N1, M _N2The breadth length ratio of grid get identical value, M _P1, M _P2The breadth length ratio of grid get identical value, can get entire circuit and be output as:

$V_O=V_i\frac{g_{\mathrm{MN}1}}{g_{\mathrm{MP}1}}---\left(4\right)$

Latching phase, clock CLK control switch MN ₈, MN ₉Disconnect being connected between latch and the emitter follower.Simultaneously, clock control is by inverter INV ₁, INV ₂Make latch work, the initial voltage of latch is the voltage that (4) formula provides:

$V_O(t=0)=V_i\frac{g_{\mathrm{MN}1}}{g_{\mathrm{MP}1}}---\left(5\right)$

The preamplifier of circuit of the present invention is consistent with the structural design of the preamplifier of traditional comparator, i.e. g _MN1=g _N1, g _MP1=g _P1Contrast (5) formula and (3) formula, as can be seen, circuit of the present invention has the more stable voltage that initially latchs, thereby has more stable propagation delay time.

From above analysis as seen, with respect to traditional comparator, circuit of the present invention has higher operating rate, more stable propagation delay time.Simultaneously, because the introducing of emitter follower unit in the circuit of the present invention, the high input impedance of emitter follower unit, low output impedance characteristic make circuit of the present invention have the recoil effect of better isolated latches.

During layout design, note reducing dead resistance and electric capacity as far as possible, note M _N1With M _N2Between, M _P1With M _P2Between, M _N4With M _N5Between, M _N6With M _N7Between, M _N8With M _N9Between, M _P4With M _P5Between, M _N10With M _N11Between coupling.

Inverter INV ₁, INV ₂Be custom circuit.

Circuit of the present invention has been successfully applied in 14 125MSPS pipeline a/d converters, test result shows, this A/D converter differential nonlinearity error (DNL) is 0.7LSB, integral non-linear error (INL) is 1.5LSB, at input clock 125MHz, under the condition of input signal 15MHz, the Spurious Free Dynamic Range of this A/D converter (SFDR) is to 86dB, satisfy the design objective requirement, and traditional comparator is difficult to satisfy so at a high speed, the requirement of high-precision A/D converter.

Manufacturing process of the present invention is general Si-gate N trap 0.35 μ m CMOS technology.

The basic parameter of the PMOS in the circuit of the present invention, NMOS pipe is:

The threshold voltage V of NMOS pipe _T: 0.5～0.7V;

The threshold voltage V of PMOS pipe _T:-0.65～-0.85V;

Gate oxide thickness 7.2nm～the 7.7nm of NMOS pipe, PMOS pipe.

In addition, M _P3The breadth length ratio of grid: 4 μ m/0.35 μ m～12 μ m/0.35 μ m;

M _N4, M _N5Grid get identical breadth length ratio: 0.8 μ m/0.35 μ m～1.5 μ m/0.35 μ m;

M _N6, M _N7Grid get identical breadth length ratio: 0.8 μ m/0.5 μ m～1.5 μ m/0.5 μ m;

M _N8, M _N9The breadth length ratio of grid: 0.8 μ m/0.35 μ m～1.5 μ m/0.35 μ m;

M _N10, M _N11The breadth length ratio of grid: 5 μ m/0.35 μ m～10 μ m/0.35 μ m;

M _P4, M _P5The breadth length ratio of grid: 5 μ m/0.35 μ m～10 μ m/0.35 μ m;

M _N1, M _N2, M _P1, M _P2, M _N4, M _N5, M _P3Grid long: 0.35 μ m.

Claims (1)

1. high-speed comparator is characterized in that it contains:

A pre-amplifier unit comprises:

PMOS manages MP ₁, PMOS manages MP ₂, NMOS manages MN ₁, NMOS manages MN ₂, NMOS manages MN ₃, wherein, MN ₁Grid meet the positive input terminal V of high-speed comparator _i ^-, MN ₂Grid meet the negative input end V of high-speed comparator _i ^-, MN ₁, MN ₂Source electrode and MN ₃Drain electrode join MN ₃Grid meet bias voltage V _Bias, MN ₃Source ground V _SS, MP ₁Grid, drain electrode and MN ₁Drain electrode join, its tie point is the negative output terminal V of pre-amplifier unit ₁ ^-, MP ₂Grid, drain electrode and MN ₂Drain electrode join, its tie point is the positive output end V of pre-amplifier unit ₁ ⁺, MP ₁, MP ₂Source electrode all meet power supply V _DDWith

An emitter follower unit comprises:

PMOS manages MP ₃, NMOS manages MN ₄, NMOS manages MN ₅, NMOS manages MN ₆, NMOS manages MN ₇, wherein, MN ₄Grid meet the negative output terminal V of pre-amplifier unit ₁ ^-, MN ₅Grid meet the positive output end V of pre-amplifier unit ₁ ⁺, MN ₄, MN ₅Drain electrode and MP ₃Grid, the drain electrode link together MP ₃Source electrode meet power supply V _DD, MN ₄Source electrode and MN ₆Drain electrode join, its tie point is the negative output terminal V of emitter follower unit ₂ ^-, MN ₅Source electrode and MN ₇Drain electrode join, its tie point is the positive output end V of emitter follower unit ₂ ⁺, MN ₆, MN ₇Grid all meet bias voltage V _Bias, MN ₆, MN ₇Source grounding V _SSWith

A latch unit comprises:

PMOS manages MP ₄, PMOS manages MP ₅, inverter INV ₁, inverter INV ₂, NMOS manages MN ₈, NMOS manages MN ₉, NMOS manages MN ₁₀, NMOS manages MN ₁₁, wherein, MN ₈Drain electrode and the positive output end V of emitter follower unit ₂ ⁺Join MN ₉Drain electrode and the negative output terminal V of emitter follower unit ₂ ^-Join MN ₈, MN ₉Grid and INV ₁Input all join MP with input end of clock CLK ₄, MP ₅Source electrode and INV ₁Output, INV ₂Input link together MN ₁₀, MN ₁₁Source electrode and INV ₂Output join MP ₄, MN ₁₀Drain electrode and MP ₅, MN ₁₁Grid and MN ₉Source electrode link together, as high-speed comparator negative output terminal V _o ^-, MP ₅, MN ₁₁Drain electrode and MP ₄, MN ₁₀Grid and MN ₈Source electrode link together, as high-speed comparator positive output end V _o ⁺

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