CN107565966B - Comparator applied to high-speed assembly line ADC - Google Patents
Comparator applied to high-speed assembly line ADC Download PDFInfo
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Abstract
The invention discloses a comparator applied to a high-speed assembly line ADC (analog to digital converter), which comprises a switched capacitor sampling front-end circuit, a pre-amplification stage circuit and a capacitor storage latch output stage circuit, wherein the switched capacitor sampling front-end circuit comprises a sampling circuit, a sampling circuit and a sampling circuit; the sampling front end of the switched capacitor samples and inputs an input signal and a reference voltage; the pre-amplification stage circuit performs large prevention on the input signal obtained by sampling, meanwhile, the large prevention circuit is not directly connected with the output of rail-to-rail voltage change, kickback noise can be reduced to a certain extent, and the influence of the kickback noise can also be reduced by a cross coupling structure adopted in the pre-amplification stage; the capacitor storage latch output stage circuit utilizes two phase inverters connected end to form a positive feedback loop, a tiny comparison result stored on a capacitor is amplified and latched for output, and two NMOS tubes MN3 and MN4 in the stage are turned off when rail-to-rail voltage changes are generated in the regeneration stage of a comparator, so that the input end is isolated from the rail-to-rail output changes, and the influence of kickback noise is greatly eliminated.
Description
Technical Field
The invention relates to the field of CMOS integrated circuit design, in particular to comparator design.
Background
With the widespread use of integrated circuit chips, digital communication is receiving more and more attention, and analog-to-digital converters (ADCs) as key modules for converting analog signals into digital signals are becoming more and more fields of continuous optimization and innovation for designers. Among different types of ADCs, pipelined ADCs are gradually emerging from a wide variety of ADCs with their high speed, high accuracy, and low power consumption. The comparator is used as a performance module for realizing the high-speed pipeline ADC, and is indispensable for designing the high performance of the ADC.
The comparator mainly comprises an A-B latch comparator and a dynamic comparator. The A-B latch comparator has high precision and small kickback noise, but has low speed and static power consumption; the dynamic comparator has the advantages of high speed and low power consumption, but the kickback noise is high; offset voltages are present in both comparators. The offset voltage of the comparator can be greatly reduced by a digital correction technology adopted in the pipeline ADC, and the kickback noise can seriously influence the setup time of the operational amplifier, so that the speed of the pipeline ADC is limited to be increased.
Disclosure of Invention
The invention provides a comparator which can greatly control the influence of kickback noise and is applied to a high-speed assembly line ADC (analog to digital converter), aiming at the design requirements of the low-power consumption and high-speed assembly line ADC, adopting a dynamic comparator and overcoming the defect that the kickback noise of the comparator in the prior art is larger. In the invention, the pre-amplification stage and the capacitor storage and latch output structure are adopted, so that the connection between the output node of the rail-to-rail voltage change and the input can be isolated, and the kickback noise of the signal coupled to the input end through the input parasitic capacitor due to the rail-to-rail change of the output rail is reduced to a great extent; in the invention, the introduction of a prevention large-scale circuit and a capacitance storage technology does not increase the power consumption of the original comparator, but can greatly control the influence of kickback noise.
In order to solve the technical problem, the comparator applied to the high-speed pipeline ADC provided by the invention comprises a switched capacitor sampling front-end circuit, a pre-amplification stage circuit and a capacitor storage latch output stage circuit. The switched capacitor sampling front-end circuit comprises 4 sampling front-end switches and 2 capacitors, wherein the sampling front-end switches and the 2 capacitors are controlled by a time sequence S1, the 4 sampling front-end switches are respectively recorded as a switch S11, a switch S12, a switch S13 and a switch S14, the 2 capacitors are respectively recorded as a capacitor C1 and a capacitor C2, the switch S11 and the switch S12 respectively sample an input differential signal VIP and a differential reference level VRP to a capacitor C1, and the switch S13 and the switch S14 respectively sample an input differential signal VIN and a differential reference level VRN to the capacitor C2. The pre-amplification stage circuit comprises 3 PMOS tubes, 4 NMOS tubes and 2 switches which are controlled by a time sequence S2A, wherein 3 PMOS tubes are respectively recorded as a PMOS tube MP1, a PMOS tube MP2 and a PMOS tube MP3, 4 NMOS tubes are respectively recorded as an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN9 and an NMOS tube MN10, and 2 switches are respectively recorded as a switch S2A1 and a switch S2A 2. The capacitor storage latch output stage circuit comprises 2 PMOS tubes, 8 NMOS tubes, a capacitor C3 and 1 switch S15 controlled by S1, wherein the 2 PMOS tubes are respectively recorded as a PMOS tube MP4 and a PMOS tube MP5, and the 8 NMOS tubes are respectively recorded as an NMOS tube MN3, an NMOS tube MN4, an NMOS tube MN5, an NMOS tube MN6, an NMOS tube MN7, an NMOS tube MN8, an NMOS tube MN11 and an NMOS tube MN 12;
the connection relationship of all the devices is as follows:
one end of the capacitor C1 is connected with a switch S1 connected with the sampling input differential signal VIP and a switch S2 connected with the differential reference level VRP, and the other end of the capacitor C1 is connected with the gate end of an NMOS transistor MN 1; one end of the capacitor C2 is connected with the switch S3 connected with the sampling input differential signal VIN and the switch S4 connected with the differential reference level VRN, and the other end of the capacitor C2 is connected with the gate end of the NMOS transistor MN 2. The source end of the NMOS tube MN1 is grounded, and the gate end and the drain end are respectively connected to the two ends of the switch S2A 1; the source end of the NMOS tube MN2 is grounded, and the gate end and the drain end are respectively connected to the two ends of the switch S2A 2; the source-drain end of the NMOS tube MN9 is connected to the drain end of the NMOS tube MN1, and the gate end of the NMOS tube MN2 is connected to the gate end of the NMOS tube MN; the source-drain end of the NMOS tube MN10 is connected to the drain end of the NMOS tube MN2, and the gate end of the NMOS tube MN1 is connected to the gate end of the NMOS tube MN; the source ends of the PMOS tube MP1 and the PMOS tube MP2 are both connected to the drain end of the PMOS tube MP 3; the gate end and the drain end of the PMOS tube MP1 are both connected to the drain end of the NMOS tube MN 1; the gate end and the drain end of the PMOS tube MP2 are both connected to the drain end of the NMOS tube MN 2; the source terminal of the PMOS tube MP3 is connected with the power voltage, and the gate terminal is connected with the bias voltage VBias. The source ends of the NMOS transistor MN3 and the NMOS transistor MN4 are both connected to the ground; the gate end of the NMOS transistor MN3 is connected with the drain end of the PMOS transistor MP 1; the gate end of the NMOS transistor MN4 is connected with the drain end of the PMOS transistor MP 2; the source ends of the NMOS transistor MN7 and the NMOS transistor MN8 are both connected to the ground, and the gate ends of the NMOS transistor MN7 and the NMOS transistor MN8 are both connected to a bias voltage S2A; the gate end of the NMOS transistor MN5 and the gate end of the NMOS transistor MN6 are both connected to a bias voltage S1; the source end of the NMOS tube MN5 is connected with the drain end of the NMOS tube MN3, and the drain end of the NMOS tube MN7 is connected with the drain end of the NMOS tube MN; the source end of the NMOS tube MN6 is connected with the drain end of the NMOS tube MN4, and the drain end of the NMOS tube MN8 is connected with the drain end of the NMOS tube MN; the gate ends of the PMOS transistor MP4 and the NMOS transistor MN11 are connected, and the drain ends of the PMOS transistor MP5 and the NMOS transistor MN12 are connected; the drain ends of the PMOS transistor MP4 and the NMOS transistor MN11 are connected, and the gate ends of the PMOS transistor MP5 and the NMOS transistor MN12 are connected; two ends of the switch 15 are connected with the gate ends of the NMOS transistor MN11 and the NMOS transistor MN 12; the source ends of the PMOS tube MP4 and the PMOS tube MP5 are both connected to a power supply voltage; two ends of the capacitor C3 are respectively connected with the source ends of the NMOS transistor MN11 and the NMOS transistor MN 12.
Compared with the prior art, the invention has the beneficial effects that:
in the invention, a switch capacitor sampling front end samples and inputs an input signal and a reference voltage; the pre-amplification stage circuit performs large prevention on the input signal obtained by sampling, meanwhile, the large prevention circuit is not directly connected with the output of rail-to-rail voltage change, kickback noise can be reduced to a certain extent, and the influence of the kickback noise can also be reduced by a cross coupling structure adopted in the pre-amplification stage; the capacitor storage latch output stage circuit utilizes two phase inverters connected end to form a positive feedback loop, a tiny comparison result stored on a capacitor is amplified and latched for output, and two NMOS tubes MN3 and MN4 in the stage are turned off when rail-to-rail voltage changes are generated in the regeneration stage of a comparator, so that the input end is isolated from the rail-to-rail output changes, and the influence of kickback noise is greatly eliminated.
Drawings
FIG. 1 is a schematic diagram of a circuit structure of a comparator applied to a high-speed pipeline ADC according to the present invention;
fig. 2 is a control diagram of the timing of the switches in the present invention.
Detailed Description
The technical solutions of the present invention are further described in detail with reference to the accompanying drawings and specific embodiments, which are only illustrative of the present invention and are not intended to limit the present invention.
The circuit structure of the comparator applied to the high-speed pipeline ADC is shown in FIG. 1, and the comparator comprises a switched capacitor sampling front-end circuit, a pre-amplification stage circuit and a capacitor storage latch output stage circuit.
As shown in fig. 2, in the present invention, the timings S1 and S2 are two non-overlapping clock signals output by the two-phase non-overlapping clock generating circuit, and the timings S1A and S2A are clock signals output by the two-phase non-overlapping clock generating circuit whose high level duration is slightly shorter than the timings S1 and S2.
The switched capacitor sampling front-end circuit comprises 4 sampling front-end switches and 2 capacitors, wherein the sampling front-end switches and the 2 capacitors are controlled by a time sequence S1, the 4 sampling front-end switches are respectively recorded as a switch S11, a switch S12, a switch S13 and a switch S14, the 2 capacitors are respectively recorded as a capacitor C1 and a capacitor C2, the switch S11 and the switch S12 respectively sample an input differential signal VIP and a differential reference level VRP to a capacitor C1, and the switch S13 and the switch S14 respectively sample an input differential signal VIN and a differential reference level VRN to the capacitor C2.
The pre-amplification stage circuit comprises 3 PMOS tubes, 4 NMOS tubes and 2 switches which are controlled by a time sequence S2A, wherein 3 PMOS tubes are respectively recorded as a PMOS tube MP1, a PMOS tube MP2 and a PMOS tube MP3, 4 NMOS tubes are respectively recorded as an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN9 and an NMOS tube MN10, and 2 switches are respectively recorded as a switch S2A1 and a switch S2A 2.
The capacitor storage latch output stage circuit comprises 2 PMOS tubes, 8 NMOS tubes, a capacitor C3 and 1 switch S15 controlled by S1, wherein the 2 PMOS tubes are respectively recorded as a PMOS tube MP4 and a PMOS tube MP5, and the 8 NMOS tubes are respectively recorded as an NMOS tube MN3, an NMOS tube MN4, an NMOS tube MN5, an NMOS tube MN6, an NMOS tube MN7, an NMOS tube MN8, an NMOS tube MN11 and an NMOS tube MN 12.
The connection relationship of all the devices is as follows:
one end of the capacitor C1 is connected with a switch S1 connected with the sampling input differential signal VIP and a switch S2 connected with the differential reference level VRP, and the other end of the capacitor C1 is connected with the gate end of an NMOS transistor MN 1; one end of the capacitor C2 is connected with the switch S3 connected with the sampling input differential signal VIN and the switch S4 connected with the differential reference level VRN, and the other end of the capacitor C2 is connected with the gate end of the NMOS transistor MN 2. In the invention, the switched capacitor sampling front-end circuit samples and inputs an input signal and a reference voltage.
The source end of the NMOS tube MN1 is grounded, and the gate end and the drain end are respectively connected to the two ends of the switch S2A 1; the source end of the NMOS tube MN2 is grounded, and the gate end and the drain end are respectively connected to the two ends of the switch S2A 2; the source-drain end of the NMOS tube MN9 is connected to the drain end of the NMOS tube MN1, and the gate end of the NMOS tube MN2 is connected to the gate end of the NMOS tube MN; the source-drain end of the NMOS tube MN10 is connected to the drain end of the NMOS tube MN2, and the gate end of the NMOS tube MN1 is connected to the gate end of the NMOS tube MN; the source ends of the PMOS tube MP1 and the PMOS tube MP2 are both connected to the drain end of the PMOS tube MP 3; the gate end and the drain end of the PMOS tube MP1 are both connected to the drain end of the NMOS tube MN 1; the gate end and the drain end of the PMOS tube MP2 are both connected to the drain end of the NMOS tube MN 2; the source terminal of the PMOS tube MP3 is connected with the power voltage, and the gate terminal is connected with the bias voltage VBias. In the invention, the pre-amplification stage circuit adopts a cross-coupling structure to reduce the influence of kickback noise, and simultaneously, the pre-amplification stage circuit cuts off the connection between rail-to-rail output and input.
The source ends of the NMOS transistor MN3 and the NMOS transistor MN4 are both connected to the ground; the gate end of the NMOS transistor MN3 is connected with the drain end of the PMOS transistor MP 1; the gate end of the NMOS transistor MN4 is connected with the drain end of the PMOS transistor MP 2; the source ends of the NMOS transistor MN7 and the NMOS transistor MN8 are both connected to the ground, and the gate ends of the NMOS transistor MN7 and the NMOS transistor MN8 are both connected to a bias voltage S2A; the gate end of the NMOS transistor MN5 and the gate end of the NMOS transistor MN6 are both connected to a bias voltage S1; the source end of the NMOS tube MN5 is connected with the drain end of the NMOS tube MN3, and the drain end of the NMOS tube MN7 is connected with the drain end of the NMOS tube MN; the source end of the NMOS tube MN6 is connected with the drain end of the NMOS tube MN4, and the drain end of the NMOS tube MN8 is connected with the drain end of the NMOS tube MN; the gate ends of the PMOS transistor MP4 and the NMOS transistor MN11 are connected, and the drain ends of the PMOS transistor MP5 and the NMOS transistor MN12 are connected; the drain ends of the PMOS transistor MP4 and the NMOS transistor MN11 are connected, and the gate ends of the PMOS transistor MP5 and the NMOS transistor MN12 are connected; two ends of the switch 15 are connected with the gate ends of the NMOS transistor MN11 and the NMOS transistor MN 12; the source ends of the PMOS tube MP4 and the PMOS tube MP5 are both connected to a power supply voltage; two ends of the capacitor C3 are respectively connected with the source ends of the NMOS transistor MN11 and the NMOS transistor MN 12. In the invention, the capacitor storage latch output stage circuit amplifies and outputs the comparison result stored on the capacitor by using the positive feedback loop, and the connection between the rail-to-rail output and the input is cut off again by using the turn-off of MN3 and MN4 during amplification, thereby greatly reducing the influence of kickback noise.
The working principle of the comparator of the invention is as follows:
when the time sequence S1 is high, the sampling front end samples the input differential signals VIP and VIN and the differential reference levels VPN and VRP, the signals are slightly amplified by the pre-amplification stage and then transmitted to the capacitor storage latch output stage, at this time, since the switch S15 controlled by the time sequence S1 is turned on, the positive feedback loop composed of two inverters MP4, MN11, MP5 and MN12 connected end to end does not work, so a certain pre-amplified voltage difference signal is stored in the capacitor C3.
When the time sequence S1 is low level, the comparison regeneration stage is entered, the switch S15 controlled by the time sequence S1 is disconnected, the positive feedback loop enters the normal working stage, the voltage difference signal stored on the capacitor C1 is amplified, and the regeneration process at the moment is a strong positive feedback effect, so the voltage difference can be amplified to the rail-to-rail voltage in a short time and output. At this time, since the S1 is at a low level, the NMOS transistors MN5 and MN6 are turned off, and the connection between the NMOS transistors MN3 and MN4 and the pre-amplification stage is cut off, so that the input end is isolated from the rail-to-rail output change, thereby greatly eliminating the influence of kickback noise, which can reduce the influence of the kickback noise on the operational amplifier setup time, and thus improve the performance of the high-speed pipeline ADC.
While the present invention has been described with reference to the accompanying drawings, the present invention is not limited to the above-described embodiments, which are illustrative only and not restrictive, and various modifications which do not depart from the spirit of the present invention and which are intended to be covered by the claims of the present invention may be made by those skilled in the art.
Claims (1)
1. A comparator applied to a high-speed assembly line ADC comprises a switched capacitor sampling front-end circuit, a pre-amplification stage circuit and a capacitor storage latch output stage circuit; the method is characterized in that:
the switched capacitor sampling front-end circuit comprises 4 sampling front-end switches and 2 capacitors, wherein the sampling front-end switches and the 2 capacitors are controlled by a time sequence S1, the 4 sampling front-end switches are respectively recorded as a switch S11, a switch S12, a switch S13 and a switch S14, the 2 capacitors are respectively recorded as a capacitor C1 and a capacitor C2, the switch S11 is connected with a differential reference level VRP, the switch S12 is connected with a sampling input differential signal VIP, the switch S13 is connected with an input differential signal VIN, the switch S14 is connected with a differential reference level VRN, one end of the capacitor C1 is simultaneously connected with the switches S11 and S12, and the other end of the capacitor C1 is connected with the gate end of an NMOS tube MN; one end of the capacitor C2 is simultaneously connected with the switches S13 and S14, and the other end of the capacitor C2 is connected with the gate end of the NMOS transistor MN 2;
the pre-amplification stage circuit comprises 3 PMOS tubes, 4 NMOS tubes and 2 switches which are controlled by a time sequence S2A, wherein 3 PMOS tubes are respectively recorded as a PMOS tube MP1, a PMOS tube MP2 and a PMOS tube MP3, 4 NMOS tubes are respectively recorded as an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN9 and an NMOS tube MN10, and 2 switches are respectively recorded as a switch S2A1 and a switch S2A 2;
the capacitor storage latch output stage circuit comprises 2 PMOS tubes, 8 NMOS tubes, a capacitor C3 and 1 switch S15 controlled by S1, wherein the 2 PMOS tubes are respectively recorded as a PMOS tube MP4 and a PMOS tube MP5, and the 8 NMOS tubes are respectively recorded as an NMOS tube MN3, an NMOS tube MN4, an NMOS tube MN5, an NMOS tube MN6, an NMOS tube MN7, an NMOS tube MN8, an NMOS tube MN11 and an NMOS tube MN 12;
the connection relationship of all the devices is as follows:
one end of the capacitor C1 is connected with a switch S1 connected with the sampling input differential signal VIP and a switch S2 connected with the differential reference level VRP, and the other end of the capacitor C1 is connected with the gate end of an NMOS transistor MN 1; one end of a capacitor C2 is connected with a switch S3 connected with a sampling input differential signal VIN and a switch S4 connected with a differential reference level VRN, and the other end of the capacitor C2 is connected with the gate end of an NMOS (N-channel metal oxide semiconductor) transistor MN 2;
the source end of the NMOS tube MN1 is grounded, and the gate end and the drain end are respectively connected to the two ends of the switch S2A 1; the source end of the NMOS tube MN2 is grounded, and the gate end and the drain end are respectively connected to the two ends of the switch S2A 2; the source-drain end of the NMOS tube MN9 is connected to the drain end of the NMOS tube MN1, and the gate end of the NMOS tube MN2 is connected to the gate end of the NMOS tube MN; the source-drain end of the NMOS tube MN10 is connected to the drain end of the NMOS tube MN2, and the gate end of the NMOS tube MN1 is connected to the gate end of the NMOS tube MN; the source ends of the PMOS tube MP1 and the PMOS tube MP2 are both connected to the drain end of the PMOS tube MP 3; the gate end and the drain end of the PMOS tube MP1 are both connected to the drain end of the NMOS tube MN 1; the gate end and the drain end of the PMOS tube MP2 are both connected to the drain end of the NMOS tube MN 2; the source end of the PMOS tube MP3 is connected with the power voltage, and the gate end is connected with the bias voltage VBias;
the source ends of the NMOS transistor MN3 and the NMOS transistor MN4 are both connected to the ground; the gate end of the NMOS transistor MN3 is connected with the drain end of the PMOS transistor MP 1; the gate end of the NMOS transistor MN4 is connected with the drain end of the PMOS transistor MP 2; the source ends of the NMOS transistor MN7 and the NMOS transistor MN8 are both connected to the ground, and the gate ends of the NMOS transistor MN7 and the NMOS transistor MN8 are both connected to a bias voltage S2A; the gate end of the NMOS transistor MN5 and the gate end of the NMOS transistor MN6 are both connected to a bias voltage S1; the source end of the NMOS tube MN5 is connected with the drain end of the NMOS tube MN3, and the drain end of the NMOS tube MN7 is connected with the drain end of the NMOS tube MN; the source end of the NMOS tube MN6 is connected with the drain end of the NMOS tube MN4, and the drain end of the NMOS tube MN8 is connected with the drain end of the NMOS tube MN; the gate ends of the PMOS transistor MP4 and the NMOS transistor MN11 are connected, and the drain ends of the PMOS transistor MP5 and the NMOS transistor MN12 are connected; the drain ends of the PMOS transistor MP4 and the NMOS transistor MN11 are connected, and the gate ends of the PMOS transistor MP5 and the NMOS transistor MN12 are connected; two ends of the switch 15 are connected with the gate ends of the NMOS transistor MN11 and the NMOS transistor MN 12; the source ends of the PMOS tube MP4 and the PMOS tube MP5 are both connected to a power supply voltage; two ends of the capacitor C3 are respectively connected with the source ends of the NMOS transistor MN11 and the NMOS transistor MN 12.
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| CN112929019B (en) * | 2021-01-25 | 2022-02-08 | 无锡英迪芯微电子科技股份有限公司 | Novel multichannel high pressure sampling circuit |
| US11646727B2 (en) | 2021-09-03 | 2023-05-09 | Changxin Memory Technologies, Inc. | Comparator and decision feedback equalization circuit |
| CN115765691A (en) * | 2021-09-03 | 2023-03-07 | 长鑫存储技术有限公司 | Comparator and decision feedback equalization circuit |
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| CN106208984A (en) * | 2016-07-12 | 2016-12-07 | 天津大学 | High linearity trsanscondutance amplifier for the broad tuning scope of multimode Gm C wave filter |
| CN106603048A (en) * | 2016-11-22 | 2017-04-26 | 上海华力微电子有限公司 | Cascade comparator circuit |
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| US8198920B2 (en) * | 2009-03-23 | 2012-06-12 | Atmel Corporation | Low current comparator with programmable hysteresis |
| US10044362B2 (en) * | 2014-06-19 | 2018-08-07 | Texas Instruments Incorporated | Complementary current reusing preamp for operational amplifier |
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|---|---|---|---|---|
| CN106208984A (en) * | 2016-07-12 | 2016-12-07 | 天津大学 | High linearity trsanscondutance amplifier for the broad tuning scope of multimode Gm C wave filter |
| CN106603048A (en) * | 2016-11-22 | 2017-04-26 | 上海华力微电子有限公司 | Cascade comparator circuit |
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| A preamplifier-latch comparator for high accuracy high speed switched-capacitors pipelined ADC;Hao Zheng, Xiangning Fan;《2014 9th International Symposium on Communication Systems, Networks & Digital Sign》;20141016;全文 * |
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