CN107565966A - A kind of comparator applied to high-speed flow line ADC - Google Patents
A kind of comparator applied to high-speed flow line ADC Download PDFInfo
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- CN107565966A CN107565966A CN201710638094.9A CN201710638094A CN107565966A CN 107565966 A CN107565966 A CN 107565966A CN 201710638094 A CN201710638094 A CN 201710638094A CN 107565966 A CN107565966 A CN 107565966A
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- nmos tube
- pmos
- drain terminal
- switch
- electric capacity
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Abstract
The invention discloses a kind of comparator applied to high-speed flow line ADC, including switching capacity sampling front-end circuit, pre-amplification stage circuit and electric capacity storage to latch output-stage circuit；Input signal and reference voltage are carried out sampling input by switching capacity sampling front-end；Pre-amplification stage circuit carries out the input signal that sampling obtains prevent greatly, prevent big level circuit because the output not with rail-to-rail voltage change is joined directly together simultaneously, it can reduce to a certain extent and recalcitrate noise, and the cross coupling structure used in pre-amplification stage can also reduce the influence for recalcitrating noise；The electric capacity storage latches output-stage circuit using two end to end phase inverter composition regenerative feedback loops, comparative result small on electric capacity will be stored in and be amplified and latch output, two NMOS tube MN3 and MN4 in this grade are in comparator regeneration stage, turned off when producing rail-to-rail voltage change, input is set to isolate with rail-to-rail exporting change, so as to substantially eliminating the influence for recalcitrating noise.
Description
Technical field
The present invention relates to CMOS IC design fields, and in particular to comparator design.
Background technology
With the extensive use of IC chip, digital communication also receives more and more attention, analog-digital converter
(ADC) also continue to optimize and innovate as more and more designers as the key modules for converting analog signals into data signal
Field.In different types of ADC, pipeline ADC is with its high-speed, high precision, and the characteristics of low-power consumption can be realized, gradually from
Show one's talent in numerous species.Comparator carries out high performance set as the performance module for realizing high-speed flow line ADC to it
It is essential to count.
Comparator mainly has A-B classes latched comparator and dynamic comparer.A-B class latched comparator precision is higher, recalcitrates
Noise is smaller, but its speed is relatively slow and has quiescent dissipation；Dynamic comparer speed, power consumption are relatively low, but its recalcitrate noise compared with
Greatly；Offset voltage be present in two kinds of comparators.The offset voltage of comparator can be by the figure adjustment that is used in pipeline ADC
Technology greatly reduces, and the settling time of operational amplifier can then be had a strong impact on by recalcitrating noise, so as to limit pipeline ADC
Speed is lifted.
The content of the invention
The present invention is for low-power consumption and high-speed flow line ADC design requirement, using dynamic comparer, and to prior art
Middle comparator, which exists to recalcitrate the shortcomings that noise is larger and provide, a kind of can greatly control recalcitrate influence of noise to be applied to high velocity stream
Waterline ADC comparator.In the present invention, stored using pre-amplification stage and electric capacity and latch the structure of output, rail can be separated and arrived
The output node of rail voltage change is connected with input, largely reduces and passes through input due to exporting rail-to-rail change
Parasitic capacitance recalcitrates noise coupled to input end signal；In the present invention, prevent the introducing of big level circuit and electric capacity memory technology
Do not increase the power consumption of original comparator, but can greatly control the influence for recalcitrating noise.
In order to solve the above-mentioned technical problem, a kind of comparator applied to high-speed flow line ADC proposed by the present invention, including
Output-stage circuit is latched in switching capacity sampling front-end circuit, pre-amplification stage circuit and electric capacity storage.Before the switching capacity sampling
Terminal circuit includes 4 and is denoted as out respectively by the sampling front-end switch of sequential S1 controls and 2 electric capacity, 4 sampling front-end switches
S11, switch S12, switch S13 and switch S14 are closed, 2 electric capacity are denoted as electric capacity C1 and electric capacity C2, switch S11 and switch S12 respectively
Input differential signal VIP and differential reference level VRP to electric capacity C1, switch S13 and switch S14 are sampled respectively samples input respectively
Differential signal VIN and differential reference level VRN to electric capacity C2.The pre-amplification stage circuit includes 3 PMOSs, 4 NMOS tubes
Switched with 2 by sequential S2A controls, 3 PMOSs therein are denoted as PMOS MP1, PMOS MP2 and PMOS respectively
MP3,4 NMOS tubes are denoted as NMOS tube MN1, NMOS tube MN2, NMOS tube MN9 and NMOS tube MN10,2 switches and remembered respectively respectively
Make switch S2A1 and switch S2A2.Output-stage circuit is latched in the electric capacity storage includes 2 PMOSs, 8 NMOS tubes, electric capacity C3
With 1 switch S15 controlled by S1,2 PMOSs therein are denoted as PMOS MP4 and PMOS MP5,8 NMOS tubes respectively
NMOS tube MN3, NMOS tube MN4, NMOS tube MN5, NMOS tube MN6, NMOS tube MN7, NMOS tube MN8, NMOS tube are denoted as respectively
MN11 and NMOS tube MN12；
The annexation of above-mentioned all devices is as follows：
Electric capacity C1 one end simultaneously with the sampling input differential signal VIP switch S1 being connected and with differential reference level VRP
Connected switch S2 is connected, electric capacity C1 other end connection NMOS tube MN1 grid end；Electric capacity C2 one end inputs with sampling simultaneously
The switch S3 and be connected with the differential reference level VRN S4 being connected that differential signal VIN is connected, electric capacity C2 other end connection NMOS
Pipe MN2 grid end.NMOS tube MN1 source ground connection, grid end and drain terminal are coupled with switch S2A1 both ends；NMOS tube MN2's
Source is grounded, and grid end and drain terminal are coupled with the both ends for switching S2A2；NMOS tube MN9 source and drain end is connected to NMOS tube MN1
Drain terminal, grid end is connected to NMOS tube MN2 grid end；NMOS tube MN10 source and drain end is connected to NMOS tube MN2 drain terminal, grid end
It is connected to NMOS tube MN1 grid end；PMOS MP1 and PMOS MP2 source are all connected to PMOS MP3 drain terminal；PMOS
MP1 grid end and drain terminal are all connected to NMOS tube MN1 drain terminal；PMOS MP2 grid end and drain terminal is all connected to NMOS tube MN2
Drain terminal；PMOS MP3 source connects supply voltage, and grid end meets bias voltage VBias.NMOS tube MN3 and NMOS tube MN4 source
End is all connected to ground；NMOS tube MN3 grid end connects PMOS MP1 drain terminal；NMOS tube MN4 grid end connects PMOS MP2 leakage
End；With being all connected to, NMOS tube MN7 and NMOS tube MN8 grid end are all connected to partially NMOS tube MN7 and NMOS tube MN8 source
Put voltage S2A；NMOS tube MN5 grid end is all connected to bias voltage S1 with NMOS tube MN6 grid end；NMOS tube MN5 source
NMOS tube MN3 drain terminal is connect, drain terminal is connected with NMOS tube MN7 drain terminal；NMOS tube MN6 source connects NMOS tube MN4 drain terminal,
Drain terminal is connected with NMOS tube MN8 drain terminal；PMOS MP4 and NMOS tube MN11 grid end be connected and with PMOS MP5 and NMOS
Pipe MN12 drain terminal is connected；PMOS MP4 and NMOS tube MN11 drain terminal be connected and with PMOS MP5 and NMOS tube MN12
Grid end be connected；The both ends of switch 15 are connected with NMOS tube MN11 and NMOS tube MN12 grid end；PMOS MP4 and PMOS
Pipe MP5 source is all connected to supply voltage；The electric capacity C3 both ends source phase with NMOS tube MN11 and NMOS tube MN12 respectively
Connection.
Compared with prior art, the beneficial effects of the invention are as follows：
In the present invention, input signal and reference voltage are carried out sampling input by switching capacity sampling front-end；Pre-amplification stage electricity
The input signal that sampling obtains prevent greatly by road, while prevents big level circuit due to the not output with rail-to-rail voltage change
It is joined directly together, can reduces recalcitrate noise to a certain extent, and the cross coupling structure used in pre-amplification stage can also reduce back
Kick the influence of noise；The electric capacity storage latches output-stage circuit using two end to end phase inverter composition positive feedback loops
Road, comparative result small on electric capacity will be stored in and be amplified and latch output, two NMOS tubes MN3 and MN4 in this grade
In comparator regeneration stage, turned off when producing rail-to-rail voltage change, input is isolated with rail-to-rail exporting change, so as to
It substantially eliminating the influence for recalcitrating noise.
Brief description of the drawings
Fig. 1 is electrical block diagram of the present invention applied to high-speed flow line ADC comparator；
Fig. 2 is the control figure of each switching sequence in the present invention.
Embodiment
Technical solution of the present invention is described in further detail with specific embodiment below in conjunction with the accompanying drawings, described is specific
Only the present invention is explained for embodiment, is not intended to limit the invention.
A kind of comparator applied to high-speed flow line ADC provided by the invention, its circuit structure is as shown in figure 1, the ratio
Output-stage circuit is latched compared with device, including switching capacity sampling front-end circuit, pre-amplification stage circuit and electric capacity storage.
As shown in Fig. 2 in the present invention, sequential S1 and S2 are not handed over by two of two-phase not overlapping clock-generating circuit output
Folded clock signal, sequential S1A and S2A are compared with sequential S1 by the two-phase high level lasting time that overlapping clock-generating circuit does not export
The slightly shorter clock signal with S2.
The switching capacity sampling front-end circuit is switched including 4 sampling front-ends controlled by sequential S1 and 2 electric capacity,
4 sampling front-end switches are denoted as switching S11, switch S12, switch S13 respectively and switch S14, and 2 electric capacity are denoted as electric capacity C1 respectively
With electric capacity C2, switch S11 and switch S12 sample input differential signal VIP and differential reference level VRP to electric capacity C1 respectively, open
Close S13 and switch S14 samples input differential signal VIN and differential reference level VRN to electric capacity C2 respectively.
The pre-amplification stage circuit is switched including 3 PMOSs, 4 NMOS tubes and 2 by sequential S2A controls, its
In 3 PMOSs be denoted as PMOS MP1, PMOS MP2 and PMOS MP3 respectively, 4 NMOS tubes are denoted as NMOS tube respectively
MN10,2 MN1, NMOS tube MN2, NMOS tube MN9 and NMOS tube switch are denoted as switching S2A1 respectively and switch S2A2.
The electric capacity storage is latched output-stage circuit and controlled including 2 PMOSs, 8 NMOS tubes, electric capacity C3 and 1 by S1
Switch S15,2 PMOSs therein are denoted as PMOS MP4 and PMOS MP5 respectively, and 8 NMOS tubes are denoted as NMOS tube respectively
MN3, NMOS tube MN4, NMOS tube MN5, NMOS tube MN6, NMOS tube MN7, NMOS tube MN8, NMOS tube MN11 and NMOS tube MN12.
The annexation of above-mentioned all devices is as follows：
Electric capacity C1 one end simultaneously with the sampling input differential signal VIP switch S1 being connected and with differential reference level VRP
Connected switch S2 is connected, electric capacity C1 other end connection NMOS tube MN1 grid end；Electric capacity C2 one end inputs with sampling simultaneously
The switch S3 and be connected with the differential reference level VRN S4 being connected that differential signal VIN is connected, electric capacity C2 other end connection NMOS
Pipe MN2 grid end.In the present invention, input signal and reference voltage are carried out sampling input by switching capacity sampling front-end circuit.
NMOS tube MN1 source ground connection, grid end and drain terminal are coupled with switch S2A1 both ends；NMOS tube MN2 source
Ground connection, grid end and drain terminal are coupled with switch S2A2 both ends；NMOS tube MN9 source and drain end is connected to NMOS tube MN1 leakage
End, grid end are connected to NMOS tube MN2 grid end；NMOS tube MN10 source and drain end is connected to NMOS tube MN2 drain terminal, and grid end is connected to
NMOS tube MN1 grid end；PMOS MP1 and PMOS MP2 source are all connected to PMOS MP3 drain terminal；PMOS MP1's
Grid end and drain terminal are all connected to NMOS tube MN1 drain terminal；PMOS MP2 grid end and drain terminal are all connected to NMOS tube MN2 leakage
End；PMOS MP3 source connects supply voltage, and grid end meets bias voltage VBias.In the present invention, pre-amplification stage circuit is using friendship
Fork coupled structure reduces the influence for recalcitrating noise, while pre-amplification stage circuit has separated the company of rail-to-rail output and input in itself
Connect.
NMOS tube MN3 and NMOS tube MN4 source are all connected to ground；NMOS tube MN3 grid end connects PMOS MP1 leakage
End；NMOS tube MN4 grid end connects PMOS MP2 drain terminal；NMOS tube MN7 and NMOS tube MN8 source are all connected to ground, NMOS
Pipe MN7 and NMOS tube MN8 grid end are all connected to bias voltage S2A；NMOS tube MN5 grid end and NMOS tube MN6 grid end are equal
It is connected to bias voltage S1；NMOS tube MN5 source connects NMOS tube MN3 drain terminal, and drain terminal is connected with NMOS tube MN7 drain terminal；
NMOS tube MN6 source connects NMOS tube MN4 drain terminal, and drain terminal is connected with NMOS tube MN8 drain terminal；PMOS MP4 and NMOS tube
MN11 grid end is connected and is connected with PMOS MP5 and NMOS tube MN12 drain terminal；PMOS MP4's and NMOS tube MN11
Drain terminal is connected and is connected with PMOS MP5 and NMOS tube MN12 grid end；The both ends of switch 15 and NMOS tube MN11 and NMOS
Pipe MN12 grid end is connected；PMOS MP4 and PMOS MP5 source are all connected to supply voltage；Electric capacity C3 both ends point
Source not with NMOS tube MN11 and NMOS tube MN12 is connected.In the present invention, electric capacity storage latches output-stage circuit using just
Feedback control loop, which amplifies the comparative result being stored on electric capacity, to be exported, and separates rail again using MN3 and MN4 shut-off during amplification
To-rail output and the connection of input, significantly reduce the influence for recalcitrating noise.
The operation principle of comparator of the present invention：
When sequential S1 is high level, sampling front-end sampling input differential signal VIP, VIN and differential reference level VPN,
VRP, after pre-amplification stage somewhat amplifies signal, it is passed to electric capacity storage and latches output stage, now due to being controlled by sequential S1
Switch S15 conducting, do not worked by two end to end phase inverter MP4, MN11 and MP5, the MN12 regenerative feedback loop formed,
Therefore the certain voltage difference signal after pre-amplification is stored on electric capacity C3.
When sequential S1 is low level, into regeneration stage is compared, the switch S15 by S1 SECO disconnects, positive feedback
Loop enters normal work stage, the voltage differential signal being stored on electric capacity C1 is amplified, because regenerative process now is one
Individual strong positive feedback effect, therefore this voltage difference can be amplified to rail-to-rail voltage and output within a very short time.Now due to S1
For low level, NMOS tube MN5 and MN6 shut-off, the connection of NMOS tube MN3, MN4 and pre-amplification stage is separated, therefore make input
Isolate with rail-to-rail exporting change, so as to substantially eliminating the influence for recalcitrating noise, this, which can reduce, recalcitrates noise to fortune
The influence of settling time is put, so as to lift high-speed flow line ADC performance.
Although above in conjunction with accompanying drawing, invention has been described, and the invention is not limited in above-mentioned specific implementation
Mode, above-mentioned embodiment is only schematical, rather than restricted, and one of ordinary skill in the art is at this
Under the enlightenment of invention, without deviating from the spirit of the invention, many variations can also be made, these belong to the present invention's
Within protection.
Claims (1)
1. a kind of comparator applied to high-speed flow line ADC, including switching capacity sampling front-end circuit, pre-amplification stage circuit and
Output-stage circuit is latched in electric capacity storage；It is characterized in that：
The switching capacity sampling front-end circuit is switched including 4 sampling front-ends controlled by sequential S1 and 2 electric capacity, 4
Sampling front-end switch is denoted as respectively switch S11, switch S12, switch S13 and switch S14,2 electric capacity be denoted as respectively electric capacity C1 and
Electric capacity C2, switch S11 and switch S12 sample input differential signal VIP and differential reference level VRP to electric capacity C1, switch respectively
S13 and switch S14 sample input differential signal VIN and differential reference level VRN to electric capacity C2 respectively；
The pre-amplification stage circuit is switched including 3 PMOSs, 4 NMOS tubes and 2 by sequential S2A controls, and therein 3
Individual PMOS is denoted as PMOS MP1, PMOS MP2 and PMOS MP3 respectively, 4 NMOS tubes be denoted as respectively NMOS tube MN1,
NMOS tube MN2, NMOS tube MN9 and MN10,2 switch of NMOS tube are denoted as switching S2A1 respectively and switch S2A2；
The electric capacity storage is latched output-stage circuit and opened including 2 PMOSs, 8 NMOS tubes, electric capacity C3 and 1 by S1 controls
Close S15,2 PMOSs therein are denoted as PMOS MP4 and PMOS MP5 respectively, 8 NMOS tubes be denoted as respectively NMOS tube MN3,
NMOS tube MN4, NMOS tube MN5, NMOS tube MN6, NMOS tube MN7, NMOS tube MN8, NMOS tube MN11 and NMOS tube MN12；
The annexation of above-mentioned all devices is as follows：
Electric capacity C1 one end is connected with the sampling input differential signal VIP switch S1 being connected and with differential reference level VRP simultaneously
Switch S2 be connected, electric capacity C1 other end connection NMOS tube MN1 grid end；Electric capacity C2 one end is simultaneously with sampling input difference
The switch S3 and be connected with the differential reference level VRN S4 being connected that signal VIN is connected, electric capacity C2 other end connection NMOS tube
MN2 grid end；
NMOS tube MN1 source ground connection, grid end and drain terminal are coupled with switch S2A1 both ends；NMOS tube MN2 source ground connection,
Grid end and drain terminal are coupled with switch S2A2 both ends；NMOS tube MN9 source and drain end is connected to NMOS tube MN1 drain terminal, grid
Terminate to NMOS tube MN2 grid end；NMOS tube MN10 source and drain end is connected to NMOS tube MN2 drain terminal, and grid end is connected to NMOS
Pipe MN1 grid end；PMOS MP1 and PMOS MP2 source are all connected to PMOS MP3 drain terminal；PMOS MP1 grid end
NMOS tube MN1 drain terminal is all connected to drain terminal；PMOS MP2 grid end and drain terminal are all connected to NMOS tube MN2 drain terminal；
PMOS MP3 source connects supply voltage, and grid end meets bias voltage VBias；
NMOS tube MN3 and NMOS tube MN4 source are all connected to ground；NMOS tube MN3 grid end connects PMOS MP1 drain terminal；
NMOS tube MN4 grid end connects PMOS MP2 drain terminal；NMOS tube MN7 and NMOS tube MN8 source are all connected to ground, NMOS tube
MN7 and NMOS tube MN8 grid end are all connected to bias voltage S2A；NMOS tube MN5 grid end and NMOS tube MN6 grid end connect
It is connected to bias voltage S1；NMOS tube MN5 source connects NMOS tube MN3 drain terminal, and drain terminal is connected with NMOS tube MN7 drain terminal；
NMOS tube MN6 source connects NMOS tube MN4 drain terminal, and drain terminal is connected with NMOS tube MN8 drain terminal；PMOS MP4 and NMOS tube
MN11 grid end is connected and is connected with PMOS MP5 and NMOS tube MN12 drain terminal；PMOS MP4's and NMOS tube MN11
Drain terminal is connected and is connected with PMOS MP5 and NMOS tube MN12 grid end；The both ends of switch 15 and NMOS tube MN11 and NMOS
Pipe MN12 grid end is connected；PMOS MP4 and PMOS MP5 source are all connected to supply voltage；Electric capacity C3 both ends point
Source not with NMOS tube MN11 and NMOS tube MN12 is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710638094.9A CN107565966B (en) | 2017-07-31 | 2017-07-31 | Comparator applied to high-speed assembly line ADC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710638094.9A CN107565966B (en) | 2017-07-31 | 2017-07-31 | Comparator applied to high-speed assembly line ADC |
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| Publication Number | Publication Date |
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| CN107565966A true CN107565966A (en) | 2018-01-09 |
| CN107565966B CN107565966B (en) | 2020-04-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201710638094.9A Active CN107565966B (en) | 2017-07-31 | 2017-07-31 | Comparator applied to high-speed assembly line ADC |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112929019A (en) * | 2021-01-25 | 2021-06-08 | 无锡英迪芯微电子科技股份有限公司 | Novel multichannel high pressure sampling circuit |
| WO2023029346A1 (en) * | 2021-09-03 | 2023-03-09 | 长鑫存储技术有限公司 | Comparator and decision feedback equalization circuit |
| US11646727B2 (en) | 2021-09-03 | 2023-05-09 | Changxin Memory Technologies, Inc. | Comparator and decision feedback equalization circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100237908A1 (en) * | 2009-03-23 | 2010-09-23 | Atmel Corporation | Low current comparator with programmable hysteresis |
| US20150372651A1 (en) * | 2014-06-19 | 2015-12-24 | Texas Instruments Incorporated | Complementary current reusing preamp for operational amplifier |
| CN106208984A (en) * | 2016-07-12 | 2016-12-07 | 天津大学 | High linearity trsanscondutance amplifier for the broad tuning scope of multimode Gm C wave filter |
| CN106603048A (en) * | 2016-11-22 | 2017-04-26 | 上海华力微电子有限公司 | Cascade comparator circuit |
-
2017
- 2017-07-31 CN CN201710638094.9A patent/CN107565966B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100237908A1 (en) * | 2009-03-23 | 2010-09-23 | Atmel Corporation | Low current comparator with programmable hysteresis |
| US20150372651A1 (en) * | 2014-06-19 | 2015-12-24 | Texas Instruments Incorporated | Complementary current reusing preamp for operational amplifier |
| CN106208984A (en) * | 2016-07-12 | 2016-12-07 | 天津大学 | High linearity trsanscondutance amplifier for the broad tuning scope of multimode Gm C wave filter |
| CN106603048A (en) * | 2016-11-22 | 2017-04-26 | 上海华力微电子有限公司 | Cascade comparator circuit |
Non-Patent Citations (2)
| Title |
|---|
| HAO ZHENG, XIANGNING FAN: "A preamplifier-latch comparator for high accuracy high speed switched-capacitors pipelined ADC", 《2014 9TH INTERNATIONAL SYMPOSIUM ON COMMUNICATION SYSTEMS, NETWORKS & DIGITAL SIGN》 * |
| WENRONG YANG, JIADONG WANG: "Design and Analysis of a High-speed Comparator in a Pipelined ADC", 《 2007 INTERNATIONAL SYMPOSIUM ON HIGH DENSITY PACKAGING AND MICROSYSTEM INTEGRATION》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112929019A (en) * | 2021-01-25 | 2021-06-08 | 无锡英迪芯微电子科技股份有限公司 | Novel multichannel high pressure sampling circuit |
| CN112929019B (en) * | 2021-01-25 | 2022-02-08 | 无锡英迪芯微电子科技股份有限公司 | Novel multichannel high pressure sampling circuit |
| WO2023029346A1 (en) * | 2021-09-03 | 2023-03-09 | 长鑫存储技术有限公司 | Comparator and decision feedback equalization circuit |
| US11646727B2 (en) | 2021-09-03 | 2023-05-09 | Changxin Memory Technologies, Inc. | Comparator and decision feedback equalization circuit |
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|---|---|
| CN107565966B (en) | 2020-04-14 |
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