CN104702268B - The circuit that voltage buffer circuit and driving load with it switch with sequential - Google Patents
The circuit that voltage buffer circuit and driving load with it switch with sequential Download PDFInfo
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- CN104702268B CN104702268B CN201510059257.9A CN201510059257A CN104702268B CN 104702268 B CN104702268 B CN 104702268B CN 201510059257 A CN201510059257 A CN 201510059257A CN 104702268 B CN104702268 B CN 104702268B
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Abstract
The present invention provides the circuit that a kind of voltage buffer circuit and the driving load with it switch with sequential, wherein, the voltage buffer circuit is used for driving load, and it at least includes：Differential input stage, output stage and biasing module；The voltage buffer circuit of the present invention, can be switched fast the driving force for being supplied to load, power consumption is relatively low, and operating rate is fast；Large-drive-current can be provided when needing driving heavy load, provide small driving current when heavy load need not be driven, now the high current branch road in output stage is maintained at the critical point of shut-off by biasing module, greatly reduces the quiescent current of output stage.Simultaneously as the high current branch road in output stage is not complete switched off, it when needing large-drive-current, can quickly open, improve the switch speed of circuit and the stability of reference voltage.
Description
Technical field
The present invention relates to buffer circuit technical field, more particularly to a kind of voltage buffer circuit and the driving with it is negative
Carry the circuit switched with sequential.
Background technology
In Analogous Integrated Electronic Circuits, the situation that the load of reference voltage driving can switch with sequential, example can be often run into
Such as SAR ADC (Successive Approximation Register Analog-to-Digital Converter, by
It is secondary to approach register type analog-digital converter) in, the common mode reference voltage of comparator input terminal needs to drive under the cooperation of sequential
Big sampling capacitance (is loaded), therefore provides the circuit of common mode reference voltage the performance of whole circuit is played a key effect.
In the sample phase of SAR adc circuits, the common mode reference voltage produced by reference input voltage is required to setting
Fast driving bulky capacitor array reaches stabilization in fixed timing requirements, therefore the circuit of offer common mode reference voltage is needed with good
Good stability and larger driving force.In data processing stage, common mode reference voltage need not drive bulky capacitor array, because
This will also take into account power problemses caused by big driving force in circuit design.Fig. 1 is that simplest common mode reference voltage is produced
Circuit, common-mode reference electricity is produced by reference input voltage VREF by the first divider resistance Rd1 and the second divider resistance Rd2 partial pressures
VCM is pressed, common mode reference voltage VCM is directly by electric resistance partial pressure structure, i.e. the first load switch KC1 and the second load switch KC2,
To control the first sampling capacitance CS1 and the second sampling capacitance CS2 that driving is big.The circuit structure is simple, but in order to improve circuit
The big driving force of velocity interpolation, the first divider resistance Rd1 and the second divider resistance Rd2 value can not be too big.But such one
Come, the milliampere level quiescent current of the circuit will waste substantial amounts of power consumption, and electric resistance partial pressure structure is limited to a certain extent
The speed of the circuit and the stability of common mode reference voltage.
Fig. 2 is the load that an operational amplifier BUFFER is connected to common mode reference voltage and driving as buffer
Between.The circuit can the big driving force of simple realization, simultaneous buffering device output end load with input common mode reference voltage every
From, it is ensured that the stability of reference voltage.But in order to realize big driving force, the static state of common operational amplifier output stage
Electric current is also larger, need not be driven in circuit the time of heavy load, and big quiescent current can waste power consumption.
Accordingly, it is now desired to which a kind of voltage buffer circuit, can realize and big driving force is provided under heavy load, small negative
Lower reduction quiescent dissipation is carried, and the speed of circuit and the stability of reference voltage can be improved on this basis.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of voltage buffer circuit and has
The circuit that its driving load switches with sequential, for solving during generating circuit from reference voltage driving heavy load in the prior art,
The problem of quiescent current power wastage being caused in order to obtain big driving force.
In order to achieve the above objects and other related objects, the present invention provides a kind of voltage buffer circuit, for driving load,
Wherein, the voltage buffer circuit at least includes：Differential input stage, output stage and biasing module；
The positive input of the differential input stage connects a reference voltage, and the negative input of the differential input stage connects
The output end of the output stage is connect, is compared for the output voltage to the reference voltage and the output stage；
The output stage includes at least two-way low current branch road that is connected in parallel and at least high current branch road all the way, for
The relatively rear output driving current of the reference voltage and the output voltage of the output stage, and in voltage buffer circuit driving
Load need switching when there is provided the driving force being adapted；Wherein, it is switched to driving greatly in the voltage buffer circuit
During load, the output stage exports large-drive-current；When the voltage buffer circuit is switched to the small load of driving, the output
High current branch road in level is disconnected, and the output stage exports small driving current；
The biasing module connects the output stage, when being disconnected for the high current branch road in the output stage,
The high current branch road is biased to the critical point of shut-off, to reduce the quiescent current of the voltage buffer circuit.
Preferably, the differential input stage at least includes：First NMOS tube, the second NMOS tube, the first PMOS, second
PMOS and the 5th NMOS tube；
Wherein, the source ground of the 5th NMOS tube, grid one differential input stage of access of the 5th NMOS tube is inclined
Voltage is put, the drain electrode of the 5th NMOS tube is connected with the source electrode of first NMOS tube and the source electrode of second NMOS tube；
The drain electrode of first NMOS tube is connected with the grid of first PMOS and drain electrode；The drain electrode of second NMOS tube and the
The grid of two PMOSs is connected with drain electrode；The source electrode of first PMOS and the source electrode of the second PMOS are connected with power supply；Institute
The grid for stating the first NMOS tube is the negative input of the differential input stage, and the grid of second NMOS tube is the difference
The positive input of input stage.
Preferably, in the output stage, first via low current branch road at least includes：3rd PMOS and the 3rd NMOS
Pipe；Second road low current branch road at least includes：4th PMOS and the 4th NMOS tube；High current branch road at least includes：5th
PMOS, the 6th NMOS tube, first switch, second switch, third switch and the 4th switch；
Wherein, the source electrode of the 3rd PMOS is connected with power supply, the grid and described first of the 3rd PMOS
The grid of PMOS is connected, and the drain electrode of the 3rd PMOS is connected with the drain and gate of the 3rd NMOS tube, and described the
The source ground of three NMOS tubes；The source electrode of 4th PMOS is connected with power supply, the grid of the 4th PMOS with it is described
The grid of second PMOS is connected, and the drain electrode of the 4th PMOS is connected with the drain electrode of the 4th NMOS tube；Described 4th
The grid of NMOS tube is connected with the grid of the 3rd NMOS tube, the source ground of the 4th NMOS tube；The first switch
Anode be connected with the grid of the 4th PMOS, the grid of the negative terminal of the first switch and the 5th PMOS and institute
The anode for stating the 3rd switch is connected；The anode of the second switch is connected with the grid of the 4th NMOS tube, and described second opens
The negative terminal of pass is connected with the grid of the 6th NMOS tube and the anode of the 4th switch；The source electrode of 5th PMOS with
Power supply is connected, the drain electrode of the 5th PMOS and the drain electrode of the 4th PMOS and the drain electrode phase of the 6th NMOS tube
Even, the source ground of the 6th NMOS tube.
Preferably, the biasing module at least includes：The first biasing circuit for producing the first bias voltage；Described
One biasing circuit at least includes：6th PMOS, the 7th PMOS, first resistor and the 7th NMOS tube, wherein, described first is inclined
Put difference of the voltage less than or equal to supply voltage and the threshold voltage of the 6th PMOS；
Wherein, the source electrode of the 6th PMOS is connected with power supply, the grid and the described 7th of the 6th PMOS
The drain electrode of PMOS is connected with the positive pole of the first resistor, the drain electrode of the 6th PMOS and the source of the 7th PMOS
Pole is connected with the negative terminal of the 3rd switch；The grid of 7th PMOS and the negative pole of the first resistor and the 7th NMOS
The drain electrode of pipe is connected；The grid of 7th NMOS tube accesses one first bias circuit Bias voltage, the 7th NMOS tube
Source ground；First bias voltage is the voltage at the drain electrode of the 6th PMOS.
Preferably, the biasing module also includes：The second biasing circuit for producing the second bias voltage；Described second
Biasing circuit at least includes：8th PMOS, the 9th PMOS, second resistance, the 8th NMOS tube and the 9th NMOS tube, wherein,
Second bias voltage is more than or equal to the threshold voltage sum of earth terminal and the 9th NMOS tube；
Wherein, the source electrode of the 8th PMOS is connected with power supply, the grid and the described 6th of the 8th PMOS
The grid of PMOS is connected, and the drain electrode of the 8th PMOS is connected with the source electrode of the 9th PMOS；9th PMOS
The grid of pipe is connected with the grid of the 7th PMOS, the drain electrode of the 9th PMOS and the positive pole of the second resistance and
The grid of 8th NMOS tube is connected；The drain electrode of 8th NMOS tube and the negative terminal and the described 9th of the second resistance
The grid of NMOS tube is connected, the source electrode of the 8th NMOS tube and the negative terminal of the described 4th switch and the leakage of the 9th NMOS tube
Extremely it is connected, the source ground of the 9th NMOS tube；Second bias voltage is the electricity at the drain electrode of the 9th NMOS tube
Pressure.
The present invention also provides the circuit that a kind of driving load switches with sequential, wherein, the driving load switches with sequential
Circuit at least include：Voltage buffer circuit as described above.
Preferably, the circuit that the driving load switches with sequential is common mode reference voltage generation circuit, and it also includes：With
In the voltage structure for producing common mode reference voltage；Wherein, the common mode reference voltage that the voltage structure is produced with it
It is used as the reference voltage for being connected to the voltage buffer circuit.
Preferably, the voltage structure at least includes：First divider resistance and the second divider resistance；Wherein, it is described
The positive pole of first divider resistance accesses a reference input voltage, the negative pole of first divider resistance and second divider resistance
Positive pole be connected, the negative pole of second divider resistance ground connection；The common mode reference voltage is the negative of first divider resistance
Voltage at pole.
As described above, the circuit that the voltage buffer circuit of the present invention and the driving load with it switch with sequential, has
Following beneficial effect：
The voltage buffer circuit of the present invention, can be switched fast the driving force for being supplied to load, power consumption is relatively low, work speed
Degree is fast；Large-drive-current can be provided when needing driving heavy load, small driving current is provided when heavy load need not be driven,
Now the high current branch road in output stage is maintained at the critical point of shut-off by biasing module, greatly reduces the Static Electro of output stage
Stream.Simultaneously as the high current branch road in output stage is not complete switched off, when needing large-drive-current, can quickly it open
Open, improve the switch speed of circuit and the stability of reference voltage.
The circuit that the driving load of the present invention switches with sequential, especially SAR ADC common mode reference voltage generation circuit,
It can also be the circuit that the load of other drivings switches with sequential, include the above-mentioned voltage buffer circuit of the present invention, Neng Goushi
Big driving force is provided under present heavy load, reduces quiescent dissipation under small load, and circuit can be improved on this basis
The stability of speed and reference voltage.
Brief description of the drawings
Fig. 1 is shown as the schematic diagram of common mode reference voltage generation circuit of the prior art of the invention.
Fig. 2 is shown as the signal of the present invention common mode reference voltage generation circuit of the prior art with operational amplifier
Figure.
Fig. 3 is shown as the structural schematic block diagram of the voltage buffer circuit of first embodiment of the invention.
Fig. 4 is shown as the exemplary circuit diagram of the voltage buffer circuit of first embodiment of the invention.
Fig. 5 is shown as the schematic diagram for the circuit that the of the invention second driving load failed in love switches with sequential.
Component label instructions
VREF reference input voltages
VCM common mode reference voltages
The divider resistances of Rd1 first
The divider resistances of Rd2 second
The load switches of KC1 first
The load switches of KC2 second
The sampling capacitances of CS1 first
The sampling capacitances of CS2 second
BUFFER operational amplifiers
10 differential input stages
20 output stages
21 first via low current branch roads
22 second road low current branch roads
30 biasing modules
31 first biasing circuits
32 second biasing circuits
The negative input of VIN differential input stages
The positive input of VIP differential input stages
The output end (output voltage) of Vout output stages
GND earth terminals
The NMOS tube of NMOS tubes of MN1~MN9 first~the 9th
The PMOS of PMOSs of MP1~MP9 first~the 9th
K1~K4 first switches~4th switchs
VB1 differential input stage offset voltages
VB2 the first bias circuit Bias voltages
The bias voltages of Vbias1 first
The bias voltages of Vbias2 second
R1 first resistors
R2 second resistances
The current sources of I1 first
The current sources of I2 second
Mc mos capacitances
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Fig. 3 and Fig. 4 are referred to, first embodiment of the invention is related to a kind of voltage buffer circuit, for driving load.Need
Illustrate, the diagram provided in the present embodiment only illustrates the basic conception of the present invention in a schematic way, only show in schema then
Show with relevant component in the present invention rather than drawn according to component count, shape and the size during actual implement, its actual implementation
When each component kenel, quantity and ratio can be a kind of random change, and its assembly layout kenel may also be increasingly complex.
As shown in figure 3, the voltage buffer circuit of the present embodiment at least includes：Differential input stage 10, output stage 20 and biasing
Module 30.
For differential input stage 10, it has positive input and negative input.The positive input of differential input stage 10
One reference voltage of end connection, the negative input of differential input stage 10 connects the output end of output stage 20.Differential input stage 10 is used
It is compared in the output voltage to reference voltage and output stage 20.
For output stage 20, it includes at least two-way low current branch road being connected in parallel and at least high current branch road all the way.
Shown output stage 20 is used in reference voltage and the relatively rear output driving current of the output voltage of output stage 20, and in voltage buffer
There is provided the driving force being adapted when the load of circuit drives needs to switch.Wherein, it is switched to drive in voltage buffer circuit
During dynamic heavy load, the output of output stage 20 large-drive-current, i.e. output stage 20 provide big driving force for heavy load；It is slow in voltage
When rushing circuit and being switched to the small load of driving, the high current branch road in output stage 20 is disconnected, and output stage 20 exports small driving electricity
Stream, i.e. output stage 20 provide small driving force for small load.
For biasing module 30, it connects output stage 20, when being disconnected for the high current branch road in output stage 20,
High current branch road is biased to the critical point of shut-off, to reduce the quiescent current of voltage buffer circuit.
It should be noted that the power end in differential input stage 10, output stage 20 and biasing module 30 access it is same
Supply voltage.
It is illustrated in figure 4 in the exemplary circuit diagram of the present embodiment, differential input stage 10, output stage 20 and biasing module 30
Included specific component is as follows.It is pointed out that Fig. 4 is a kind of exemplary circuit in practical application, other institutes
Above-mentioned differential input stage 10 can be realized by having, the circuit of the effect of output stage 20 and biasing module 30 and its first device included
Part, within protection scope of the present invention.
Referring to Fig. 4, differential input stage 10 at least includes：First NMOS tube MN1, the second NMOS tube MN2, the first PMOS
MP1, the second PMOS MP2 and the 5th NMOS tube MN5.Wherein, the 5th NMOS tube MN5 source ground, the 5th NMOS tube MN5
Grid access one differential input stage 10 bias voltage VB1, the 5th NMOS tube MN5 drain electrode and the first NMOS tube MN1 source electrode
It is connected with the second NMOS tube MN2 source electrode；First NMOS tube MN1 drain electrode is connected with the first PMOS MP1 grid and drain electrode；
Second NMOS tube MN2 drain electrode is connected with the second PMOS MP2 grid and drain electrode；First PMOS MP1 source electrode and second
PMOS MP2 source electrode is connected with power supply；First NMOS tube MN1 grid is the negative input VIN of differential input stage 10, the
Two NMOS tube MN2 grid is the positive input VIP of differential input stage 10.
Please continue to refer to Fig. 4, in output stage 20, it is preferable that including the two-way low current branch road that is connected in parallel and all the way
High current branch road, two-way low current branch road is respectively first via low current branch road 21 and the second road low current branch road 22.
First via low current branch road 21 at least includes：3rd PMOS MP3 and the 3rd NMOS tube MN3.Second road low current
Branch road 22 at least includes：4th PMOS MP4 and the 4th NMOS tube MN4.High current branch road at least includes：5th PMOS MP5,
6th NMOS tube MN6, first switch K1, second switch K2, the 3rd switch K3 and the 4th switch K4.
Wherein, the 3rd PMOS MP3 source electrode is connected with power supply, the 3rd PMOS MP3 grid and the first PMOS MP1
Grid be connected, the 3rd PMOS MP3 drain electrode is connected with the 3rd NMOS tube MN3 drain and gate, the 3rd NMOS tube MN3's
Source ground；4th PMOS MP4 source electrode is connected with power supply, the 4th PMOS MP4 grid and the second PMOS MP2 grid
Extremely it is connected, the 4th PMOS MP4 drain electrode is connected with the 4th NMOS tube MN4 drain electrode；4th NMOS tube MN4 grid and the 3rd
NMOS tube MN3 grid is connected, the 4th NMOS tube MN4 source ground；First switch K1 anode and the 4th PMOS MP4's
Grid is connected, and first switch K1 negative terminal is connected with the anode of the 5th PMOS MP5 grid and the 3rd switch K3；Second switch
K2 anode is connected with the 4th NMOS tube MN4 grid, second switch K2 negative terminal and the 6th NMOS tube MN6 grid and the 4th
The anode for switching K4 is connected；5th PMOS MP5 source electrode is connected with power supply, the 5th PMOS MP5 drain electrode and the 4th PMOS
Pipe MP4 drain electrode is connected with the 6th NMOS tube MN6 drain electrode, the 6th NMOS tube MN6 source ground.
Please continue to refer to Fig. 4, biasing module 30 at least includes：The first biasing for producing the first bias voltage Vbias1
Circuit 31.First biasing circuit 31 at least includes：6th PMOS MP6, the 7th PMOS MP7, first resistor R1 and the 7th
NMOS tube MN7, wherein, the first bias voltage Vbias1 is less than or equal to supply voltage VDD and the 6th PMOS MP6 threshold voltage
Vthp difference, namely the first bias voltage Vbias1 the low Vthp of value of the value than supply voltage VDD.Wherein, the 6th PMOS MP6
Source electrode be connected with power supply, the 6th PMOS MP6 grid and the 7th PMOS MP7 drain electrode and first resistor R1 positive pole phase
Even, the 6th PMOS MP6 drain electrode is connected with the negative terminal of the 7th PMOS MP7 source electrode and the 3rd switch K3；7th PMOS
MP7 grid is connected with the drain electrode of first resistor R1 negative pole and the 7th NMOS tube MN7；7th NMOS tube MN7 grid access
The bias voltage VB2 of one first biasing circuit 31, the 7th NMOS tube MN7 source ground；First bias voltage Vbias1 is the 6th
Voltage at PMOS MP6 drain electrode.
Please continue to refer to Fig. 4, biasing module 30 also includes：The second biased electrical for producing the second bias voltage Vbias2
Road 32.Second biasing circuit 32 at least includes：8th PMOS MP8, the 9th PMOS MP9, second resistance R2, the 8th NMOS tube
MN8 and the 9th NMOS tube MN9, wherein, the second bias voltage Vbias2 is more than or equal to earth terminal GND's and the 9th NMOS tube MN9
Threshold voltage vt hn sums, namely the second bias voltage Vbias2 the high Vthn of magnitude of voltage of the value than earth terminal GND.Wherein,
Eight PMOS MP8 source electrode is connected with power supply, and the 8th PMOS MP8 grid is connected with the 6th PMOS MP6 grid, and the 8th
PMOS MP8 drain electrode is connected with the 9th PMOS MP9 source electrode；9th PMOS MP9 grid and the 7th PMOS MP7's
Grid is connected, and the 9th PMOS MP9 drain electrode is connected with the grid of second resistance R2 positive pole and the 8th NMOS tube MN8；8th
NMOS tube MN8 drain electrode is connected with second resistance R2 negative terminal and the 9th NMOS tube MN9 grid, the 8th NMOS tube MN8 source
Pole is connected with the drain electrode of the 4th switch K4 negative terminal and the 9th NMOS tube MN9, the 9th NMOS tube MN9 source ground；Second is inclined
Put the voltage at the drain electrode that voltage Vbias2 is the 9th NMOS tube MN9.
The voltage buffer circuit of the present embodiment can be applicable in SAR ADC common mode reference voltage generation circuit, can also
In the circuit switched applied to other driving loads with sequential.Needing the big load of driving, (load driven needs switching
For heavy load) when, all low current branch roads and high current branch road in output stage 20 are all connected in parallel and turned on, output stage 20
High current pattern is switched to, current branch increases, large-drive-current can be exported to heavy load, so as to provide big driving energy
Power.When big load (load driven needs to switch to small load) need not be driven, by the high current in output stage 20
Branch road and the second road low current branch road 22 are disconnected, and only have low current branch circuit parallel connection to connect and turn in output stage 20, are exported
Level 20 is switched to low current pattern, and current branch is reduced, and small driving current can be exported to small load, so as to provide small driving
Ability.When the high current branch road in output stage 20 and the second road low current branch road 22 are disconnected, by the high current branch road
Biasing module 30 is connected to, the biasing module 30 can provide independent bias to the high current branch road.This independent bias makes this
The gate-source voltage bias of the 6th NMOS tube MN6 in high current branch road is being slightly less than at the 6th NMOS tube MN6 threshold voltage, together
When make the gate-source voltage bias of the 5th PMOS MP5 in the high current branch road in slightly below the 5th PMOS MP5 threshold value electricity
At pressure.When not needing big driving current, biasing module 30 causes the high current branch road in output stage 20 to be biased in shut-off
Critical point, substantially reduces the quiescent current of output stage 20.Simultaneously as the high current branch road in output stage 20 does not have completely
Shut-off, when needing big driving current, can quickly open, circuit is substantially increased on the premise of quiescent dissipation is not increased
Switch speed, further increase the operating rate of circuit.
Second embodiment of the invention is related to the circuit that a kind of driving load switches with sequential, the driving load of the present embodiment with
The circuit of sequential switching refers to Fig. 5 using SAR ADC common mode reference voltage generation circuit as concrete application.
The circuit that the driving load of the present embodiment switches with sequential at least includes：Electricity involved by first embodiment of the invention
Press buffer circuit.
In addition, the circuit that driving load switches with sequential is common mode reference voltage generation circuit, it also includes：For producing
Common mode reference voltage VCM voltage structure；Wherein, voltage structure is used as connection using its common mode reference voltage produced
To the reference voltage of voltage buffer circuit.
Wherein, voltage structure at least includes：First divider resistance Rd1 and the second divider resistance Rd2；Wherein, first
Divider resistance Rd1 positive pole accesses the negative pole and the second divider resistance of reference input voltage a VREF, the first divider resistance Rd1
Rd2 positive pole is connected, the second divider resistance Rd2 negative pole ground connection；First divider resistance Rd1 and the second divider resistance Rd2 will join
Examine input voltage VREF partial pressures and produce common mode reference voltage VCM, common mode reference voltage VCM is the first divider resistance Rd1 negative pole
The voltage at place.
Please continue to refer to Fig. 5, voltage buffer circuit can be as an operational amplifier, and its output end is defeated for output stage 20
Go out to hold Vout, its positive input is the positive input VIP of differential input stage 10, its negative input is differential input stage 10
Negative input VIN.The output end of voltage buffer circuit is connected with its negative input, the negative-feedback knot of component unit gain
Structure, according to the gain of operational amplifier, the current potential for clamping down on its output end is equal with the reference voltage that its positive input is inputted, from
And realize the function of buffer circuit.Load is by mos capacitance Mc, the first load switch KC1, the second load switch KC2, the first sampling
Electric capacity CS1 and the second sampling capacitance CS2 is constituted.Output stage 20 is defeated wherein in mos capacitance Mc positive pole and voltage buffer circuit
Go out to hold Vout to be connected, mos capacitance Mc negative pole ground connection；The anode of first load switch KC1 anode and the second load switch KC2
It is connected with the output end vo ut of output stage in voltage buffer circuit 20, the first load switch KC1 negative terminal and the first sampling electricity
The positive pole for holding CS1 is connected；Second load switch KC2 negative terminal is connected with the second sampling capacitance CS2 positive pole；First sampling capacitance
CS1 negative pole is connected with the input VIN1 of follow-up adc circuit, and input voltage, the second sampling capacitance are provided for follow-up adc circuit
CS2 negative pole is connected with the reference voltage VREF1 of follow-up adc circuit, is used as the reference voltage input terminal of follow-up adc circuit.MOS
Electric capacity Mc is used for the frequency compensation of voltage buffer circuit.
The operation principle of the present embodiment common mode reference voltage generation circuit is：
When voltage buffer circuit needs to drive the heavy load being made up of the first sampling capacitance CS1 and the second sampling capacitance CS2
When, the first load switch KC1 and the second load switch KC2 are simultaneously turned on, the first sampling capacitance CS1 and the second sampling capacitance CS2
It is connected to the output end of voltage buffer circuit.First switch K1 and second switch K2 are also simultaneously turned on, the 3rd switch K3 and the 4th
Switch K4 ends simultaneously.Now high current branch road turns into the part in feedback loop, and locates in normal operation, tool
There is two-way low current branch road in big driving current, output stage 20 and high current branch road can be to the first sampling capacitance all the way
CS1 and the second rapid discharge and recharges of sampling capacitance CS2, make between the first sampling capacitance CS1 and the second sampling capacitance CS2 two-plates
Voltage is rapidly reached common mode reference voltage VCM, substantially increases the operating rate of circuit.
When buffer circuit need not drive the first sampling capacitance CS1 and the second sampling capacitance CS2, the first load switch
KC1 and the second load switch KC2 end simultaneously, and the first sampling capacitance CS1 and the second sampling capacitance CS2 are from voltage buffer circuit
Output end disconnects.Meanwhile, first switch K1 and second switch K2 end simultaneously, and the 3rd switch K3 and the 4th switch K4 are led simultaneously
Lead to, the first independent bias voltage Vbias1 and the second bias voltage Vbias2 of the high current branch route in output stage 20 carries out inclined
Put, the first current source I1 and the second current source I2 in as Fig. 5.First bias voltage Vbias1 and the second bias voltage
Vbias2 calculation formula is as follows：
Vbias1=VDD+VGSMP6-I·R1-VGSMP7；
Vbias2=VGSMN9+I·R2-VGSMN8。
Wherein, I is the quiescent current for flowing through two biasing circuits, VGSMP6For the 6th PMOS MP6 gate source voltage,
VGSMP7For the 7th PMOS MP7 gate source voltage, VGSMN8For the 8th NMOS tube MN8 gate source voltage, VGSMN9For the 9th NMOS tube
MN9 gate source voltage.
By setting rational metal-oxide-semiconductor breadth length ratio so that meeting lower relation of plane：
VDD+Vdsatp ＞ Vbias1 ≈ VDD+Vthp；Vdsatn ＜ Vbias2 ≈ Vthn；
IR1 ＜ Vthn；IR2 ＜ | Vthp |.
Wherein, Vdsatp is the 6th PMOS MP6 quiescent voltage, and Vdsatn is the 9th NMOS tube MN9 quiescent voltage,
Vdsatp=VGSMP6- Vthp, Vdsatn=VGSMN9-Vthn。
So that the 6th PMOS MP6, the 7th PMOS MP7, the 8th NMOS tube MN8 and the 9th NMOS tube MN9 work
In saturation region, while so that the 5th PMOS MP5 and the 6th NMOS tube MN6 are operated in sub-threshold region, substantially reducing static work
Make electric current, save power consumption；It can guarantee that the 5th PMOS MP5 and the 6th NMOS tube MN6 are not completely off simultaneously, can be quick
Open, further increase the operating rate of circuit, it is ensured that the stability of reference voltage.Further, since in output stage 20
5th PMOS MP5 of high current branch road and the 6th NMOS tube MN6 are operated in sub-threshold region, the quiescent current of the high current branch road
Very little, driving force is very weak, and output resistance is higher, has no effect on by the two-way low current in differential input stage 10 and output stage 20
The output for the current voltage buffer circuit that branch road is constituted.
It is pointed out that although the present embodiment is using SAR ADC common mode reference voltage generation circuit as concrete application,
But this is a kind of circuit of the voltage buffer circuit practical application involved by first embodiment of the invention, can not limit this hair
The other application of voltage buffer circuit involved by bright first embodiment, in other embodiments, other driving loads are with sequential
The circuit of switching can also be using the voltage buffer circuit involved by first embodiment of the invention.
In summary, the circuit that voltage buffer circuit of the invention and the driving load with it switch with sequential, has
Following beneficial effect：
The voltage buffer circuit of the present invention, can be switched fast the driving force for being supplied to load, power consumption is relatively low, work speed
Degree is fast；Large-drive-current can be provided when needing driving heavy load, small driving current is provided when heavy load need not be driven,
Now the high current branch road in output stage is maintained at the critical point of shut-off by biasing module, greatly reduces the Static Electro of output stage
Stream.Simultaneously as the high current branch road in output stage is not complete switched off, when needing large-drive-current, can quickly it open
Open, improve the switch speed of circuit and the stability of reference voltage.
The circuit that the driving load of the present invention switches with sequential, especially SAR ADC common mode reference voltage generation circuit,
It can also be the circuit that the load of other drivings switches with sequential, include the above-mentioned voltage buffer circuit of the present invention, Neng Goushi
Big driving force is provided under present heavy load, reduces quiescent dissipation under small load, and circuit can be improved on this basis
The stability of speed and reference voltage.
So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (8)
1. a kind of voltage buffer circuit, for driving load, it is characterised in that the voltage buffer circuit at least includes：Difference
Input stage, output stage and biasing module；
The positive input of the differential input stage connects a reference voltage, the negative input connection institute of the differential input stage
The output end of output stage is stated, is compared for the output voltage to the reference voltage and the output stage；
The output stage includes at least two-way low current branch road that is connected in parallel and at least high current branch road all the way, for described
The relatively rear output driving current of reference voltage and the output voltage of the output stage, and in bearing that the voltage buffer circuit drives
Carrying size, there is provided the driving force being adapted when needing to switch；Wherein, it is switched to driving heavy load in the voltage buffer circuit
When, the output stage exports large-drive-current；When the voltage buffer circuit is switched to the small load of driving, in the output stage
High current branch road disconnect, the output stage exports small driving current；
The biasing module connects the output stage, when being disconnected for the high current branch road in the output stage, by institute
The critical point that high current branch road is biased to shut-off is stated, to reduce the quiescent current of the voltage buffer circuit.
2. voltage buffer circuit according to claim 1, it is characterised in that the differential input stage at least includes：First
NMOS tube (MN1), the second NMOS tube (MN2), the first PMOS (MP1), the second PMOS (MP2) and the 5th NMOS tube
(MN5)；
Wherein, the source ground of the 5th NMOS tube (MN5), one difference of grid access of the 5th NMOS tube (MN5) is defeated
Enter a grade bias voltage (VB1), the source electrode of the drain electrode of the 5th NMOS tube (MN5) and first NMOS tube (MN1) and described
The source electrode of second NMOS tube (MN2) is connected；The drain electrode of first NMOS tube (MN1) and the grid of first PMOS (MP1)
Pole is connected with drain electrode；The drain electrode of second NMOS tube (MN2) is connected with the grid of the second PMOS (MP2) and drain electrode；It is described
The source electrode of first PMOS (MP1) and the source electrode of the second PMOS (MP2) are connected with power supply；First NMOS tube (MN1)
Grid is the negative input (VIN) of the differential input stage, and the grid of second NMOS tube (MN2) is the Differential Input
The positive input (VIP) of level.
3. voltage buffer circuit according to claim 2, it is characterised in that in the output stage, first via low current
Branch road at least includes：3rd PMOS (MP3) and the 3rd NMOS tube (MN3)；Second road low current branch road at least includes：4th
PMOS (MP4) and the 4th NMOS tube (MN4)；High current branch road at least includes：5th PMOS (MP5), the 6th NMOS tube
(MN6), first switch (K1), second switch (K2), the 3rd switch (K3) and the 4th switch (K4)；
Wherein, the source electrode of the 3rd PMOS (MP3) is connected with power supply, the grid of the 3rd PMOS (MP3) and described
The grid of first PMOS (MP1) is connected, the drain electrode of the 3rd PMOS (MP3) and the leakage of the 3rd NMOS tube (MN3)
Pole is connected with grid, the source ground of the 3rd NMOS tube (MN3)；The source electrode and power supply phase of 4th PMOS (MP4)
Even, the grid of the 4th PMOS (MP4) is connected with the grid of second PMOS (MP2), the 4th PMOS
(MP4) drain electrode is connected with the drain electrode of the 4th NMOS tube (MN4)；The grid of 4th NMOS tube (MN4) and described the
The grid of three NMOS tubes (MN3) is connected, the source ground of the 4th NMOS tube (MN4)；The anode of the first switch (K1)
It is connected with the grid of the 4th PMOS (MP4), negative terminal and the 5th PMOS (MP5) of the first switch (K1)
Grid is connected with the anode of the described 3rd switch (K3)；The anode of the second switch (K2) and the 4th NMOS tube (MN4)
Grid be connected, the negative terminal of the second switch (K2) and the grid of the 6th NMOS tube (MN6) and the 4th switch
(K4) anode is connected；The source electrode of 5th PMOS (MP5) is connected with power supply, the drain electrode of the 5th PMOS (MP5)
The drain electrode of drain electrode and the 6th NMOS tube (MN6) with the 4th PMOS (MP4) is connected, the 6th NMOS tube
(MN6) source ground.
4. voltage buffer circuit according to claim 3, it is characterised in that the biasing module at least includes：For producing
First biasing circuit of raw first bias voltage (Vbias1)；First biasing circuit at least includes：6th PMOS
(MP6), the 7th PMOS (MP7), first resistor (R1) and the 7th NMOS tube (MN7), wherein, first bias voltage
(Vbias1) it is less than or equal to the difference of supply voltage (VDD) and the threshold voltage of the 6th PMOS (MP6)；
Wherein, the source electrode of the 6th PMOS (MP6) is connected with power supply, the grid of the 6th PMOS (MP6) with it is described
The drain electrode of 7th PMOS (MP7) is connected with the positive pole of the first resistor (R1), the drain electrode of the 6th PMOS (MP6) with
The negative terminal of the source electrode of 7th PMOS (MP7) and the 3rd switch (K3) is connected；The grid of 7th PMOS (MP7) with
The drain electrode of the negative pole and the 7th NMOS tube (MN7) of the first resistor (R1) is connected；The grid of 7th NMOS tube (MN7)
One first bias circuit Bias voltage (VB2), the source ground of the 7th NMOS tube (MN7) are accessed in pole；First biasing
Voltage (Vbias1) is the voltage at the drain electrode of the 6th PMOS (MP6).
5. voltage buffer circuit according to claim 4, it is characterised in that the biasing module also includes：For producing
Second biasing circuit of the second bias voltage (Vbias2)；Second biasing circuit at least includes：8th PMOS (MP8),
9th PMOS (MP9), second resistance (R2), the 8th NMOS tube (MN8) and the 9th NMOS tube (MN9), wherein, described second is inclined
Voltage (Vbias2) is put more than or equal to earth terminal (GND) and the threshold voltage sum of the 9th NMOS tube (MN9)；
Wherein, the source electrode of the 8th PMOS (MP8) is connected with power supply, the grid of the 8th PMOS (MP8) with it is described
The grid of 6th PMOS (MP6) is connected, the drain electrode of the 8th PMOS (MP8) and the source of the 9th PMOS (MP9)
Extremely it is connected；The grid of 9th PMOS (MP9) is connected with the grid of the 7th PMOS (MP7), the 9th PMOS
The drain electrode of pipe (MP9) is connected with the positive pole of the second resistance (R2) and the grid of the 8th NMOS tube (MN8)；Described 8th
The drain electrode of NMOS tube (MN8) is connected with the negative terminal of the second resistance (R2) and the grid of the 9th NMOS tube (MN9), described
The source electrode of 8th NMOS tube (MN8) is connected with the drain electrode of the negative terminal and the 9th NMOS tube (MN9) of the described 4th switch (K4),
The source ground of 9th NMOS tube (MN9)；Second bias voltage (Vbias2) is the 9th NMOS tube (MN9)
Voltage at drain electrode.
6. the circuit that a kind of driving load switches with sequential, it is characterised in that the circuit that the driving load switches with sequential is extremely
Include less：Voltage buffer circuit as described in claim any one of 1-5.
7. the circuit that driving load according to claim 6 switches with sequential, it is characterised in that the driving load is at any time
The circuit of sequence switching is common mode reference voltage generation circuit, and it also includes：Voltage knot for producing common mode reference voltage
Structure；Wherein, the voltage structure is used as the ginseng for being connected to the voltage buffer circuit using its common mode reference voltage produced
Examine voltage.
8. the circuit that driving load according to claim 7 switches with sequential, it is characterised in that the voltage structure
At least include：First divider resistance (Rd1) and the second divider resistance (Rd2)；Wherein, first divider resistance (Rd1) is being just
A reference input voltage (VREF), the negative pole of first divider resistance (Rd1) and second divider resistance (Rd2) are accessed in pole
Positive pole be connected, the negative pole of second divider resistance (Rd2) ground connection；The common mode reference voltage is first divider resistance
(Rd1) the voltage at negative pole.
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| CN201510059257.9A CN104702268B (en) | 2015-02-04 | 2015-02-04 | The circuit that voltage buffer circuit and driving load with it switch with sequential |
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| CN201510059257.9A CN104702268B (en) | 2015-02-04 | 2015-02-04 | The circuit that voltage buffer circuit and driving load with it switch with sequential |
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| CN104702268B true CN104702268B (en) | 2017-08-08 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106325351A (en) * | 2016-10-14 | 2017-01-11 | 广州昌钰行信息科技有限公司 | Two-channel voltage buffer circuit |
| CN110763922B (en) * | 2019-11-01 | 2021-12-31 | 龙迅半导体（合肥）股份有限公司 | Differential reference voltage generation circuit, peak signal detection circuit, and electronic device |
| CN115167595B (en) * | 2022-07-12 | 2023-12-12 | 荣湃半导体（上海）有限公司 | Low-power consumption high-power supply ripple rejection ratio voltage buffer |
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Address after: Zhangjiang Building 20A, 289 Chunxiao Road, China (Shanghai) Free Trade Pilot Area, Pudong New Area, Shanghai Co-patentee after: VeriSilicon Microelectronics (Beijing) Co., Ltd. Patentee after: Xinyuan Microelectronics (Shanghai) Co., Ltd. Co-patentee after: VERISILICON MICROELECTRONICS (CHENGDU) CO., LTD. Co-patentee after: Core holdings limited company Address before: 201203 Zhangjiang Building 20A, 560 Songtao Road, Zhangjiang High-tech Park, Pudong New Area, Shanghai Co-patentee before: VeriSilicon Microelectronics (Beijing) Co., Ltd. Patentee before: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Co-patentee before: VERISILICON MICROELECTRONICS (CHENGDU) CO., LTD. Co-patentee before: VeriSilicon Holdings Co., Ltd. |
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