CN101159432A - CMOS type difference interface circuit - Google Patents

Abstract

A CMOS circuit with difference interface in which the difference input pole contains 4 PMOS transistors, namely M3, M4, M5 and M6; 5 NMOS transistors, namely M1, M2, M7, M8 and M9. These transistors jointly constitute NMOSFET input CMOS difference primary amplification circuit, wherein M1 and M2 are a pair of NMOS transistors, constituting geminate transistors; M3 and M5, M4 and M6, as well as M7 and M8 are double-scale mirror image current source as the load for M1 and M2; the M7 and M8 pair of current mirrors simultaneously converts double-end output into single-end output. M9 provides the direct current, i.e. tail current required by difference electric work; primary amplification circuit is linked with a secondary amplification circuit that is comprised of a PMOS transistor and a NMOS transistor Ma, wherein Ma is amplifier tube and Mb is the loading tube for Ma; the grid electrode level of the loading tube is connected with ground GND; the secondary amplification circuit is linked with the buffer output comprising two directors.

Description

CMOS type difference interface circuit

Technical field

The present invention relates to difference interface circuit, especially a kind of two-stage CMOS type difference interface circuit that contains special amplifying circuit.This circuit is applicable to LCD, PDP chip for driving, as their high speed data transmission interface, during work, higher small-signal differential mode gain is arranged, and simultaneously, according to different system power dissipation demands, cooperates the bias level of its work to have the scope of broad selective.

Background technology

Along with the development of flat panel displays such as PDP, LCD, their plate face size is increasing, and this just causes the transmission rate of the picture signal that drive circuit received of display floater more and more higher.If so the high-speed image signal adopts traditional Transistor-Transistor Logic level transmission, picture signal will be to the outside stronger electromagnetic interference of releasing through cable or the transmission of PCB cabling the time, and non-equilibrium transmission manner shows undesirable aspect the antinoise interference simultaneously.If the input data are because external disturbance makes a mistake, image shows just incorrect.In order to address these problems, National Semiconductor has proposed advanced LVDS and RSDS signal transmission standard, before these two standard mesh in extensive application and LCD and the PDP display interface circuit.LVDS and RSDS standard all comprise transmitter, interconnector and receiver three parts.The realization of receiver generally is made up of differential amplifier and biasing circuit, and wherein the more common structure of differential amplifier is the CMOS differential amplifier of PMOSFET input, as shown in Figure 6.The CMOS differential amplifier of PMOSFET input has following shortcoming: at first than higher, there is certain optimizing level value to the requirement of bias level in the CMOS differential amplifier of PMOSFET input; Secondly because the restriction of PMOS pipe self, for reaching certain difference mode gain, the CMOS differential amplifier of PMOSFET input requires differential pair tube that higher grid breadth length ratio is arranged, this can cause the increase of chip area, the requirement that this point and chip area are more and more littler is contrary, also is insoluble problem in the common structure of present CMOS difference interface circuit.

Summary of the invention

The invention provides a kind of CMOS type difference interface circuit, this circuit adopts two-stage CMOS differential amplifier, and bias level is not had specific (special) requirements, as long as satisfy the NMOS pipe energy unlatching work that tail current is provided; Simultaneously because the carrier mobility of NMOS pipe higher (comparing the PMOS pipe), it is lower to reach the required grid breadth length ratio of same difference mode gain, pass through the introducing of the secondary amplification circuit of special construction in addition, make the grid breadth length ratio of differential pair tube further reduce, finally allow differential pair tube shared area in the domain of whole difference interface circuit dwindle greatly.

Technical solution of the present invention is: a kind of CMOS type difference interface circuit, comprise the difference input to pipe, load pipe, tail current and buffering output, and it is characterized in that differential input stage even contains 4 PMOS pipes, be respectively M3, M4, M5 and M6; 5 NMOS pipes are respectively M1, M2, M7, M8 and M9; The common NMOSFET of formation imports the elementary amplifying circuit of CMOS difference, and wherein, M1 and M2 are a pair of NMOS pipes, constitute differential pair tube; M3 and M5, M4 and M6 and M7 and M8 are the loads that two scaled mirror current sources are M1 and M2; This transfers both-end output to single-ended output simultaneously to current mirror M7 and M8, and it is tail current that M9 provides the required direct current of difference channel work;

Cascade contains the secondary amplification circuit of 1 PMOS pipe Mb and 1 NMOS pipe Ma after the elementary amplifying circuit, and wherein, Ma is an amplifier tube, and Mb is the load pipe of Ma, and the grid level of this load pipe links to each other with ground GND;

Cascade contains the buffering output of two guiders after the secondary amplification circuit;

In the foregoing circuit, the substrate of all PMOS pipes meets high level VDD, and the substrate of all NMOS pipes meets low level GND.

Circuit connecting relation is as follows: input port InP and InN are connected the grid of M1 and M2 respectively, and the source electrode of M2, two metal-oxide-semiconductors of M1 and the drain electrode of metal-oxide-semiconductor M9 link together; Totally 4 nodes of the grid of the drain electrode of M1, two metal-oxide-semiconductors of M3 and M3, two metal-oxide-semiconductors of M5 interconnects; Totally 4 nodes of the grid of the drain electrode of M2, two metal-oxide-semiconductors of M4 and M4, two metal-oxide-semiconductors of M6 interconnects; Mb, M3, M4, M5 and the M6 source electrode of totally 5 metal-oxide-semiconductors receive on the power vd D; The drain electrode of M6, two metal-oxide-semiconductors of M8 and the grid of metal-oxide-semiconductor Ma interconnect; Totally 4 nodes of the grid of the drain electrode of M5, two metal-oxide-semiconductors of M7 and M7, two metal-oxide-semiconductors of M8 interconnects; M7, M8, M9, the Ma grid of the source electrode of totally 4 metal-oxide-semiconductors and metal-oxide-semiconductor Mb receive on the ground GND; The drain electrode of Ma, two metal-oxide-semiconductors of Mb and the input of guider INV1 interconnect; The grid of metal-oxide-semiconductor M9 links to each other with input port Vbias; The output of guider INV1 links to each other with the input of guider INV2; The output of guider INV2 links to each other with output port OUT.

Advantage of the present invention and beneficial effect:

CMOS type difference interface circuit of the present invention is better than difference interface circuit commonly used at present aspect a lot.

(1) all adopt the CMOS technology, CMOS itself has characteristics such as switching speed is fast, low in energy consumption, and preparation technology is simple.Under the 3.3V condition of power supply, circuit power consumption is only about 2.5mW.

(2) this interface circuit is very low to the requirement of bias voltage source, as long as satisfy the metal-oxide-semiconductor energy unlatching work that tail current work is provided; Needn't as the CMOS differential amplifier of PMOSFET input, be fixed on a just bias level.

(3) owing to introduced the secondary amplification circuit of special construction, make that its differential pair tube of interface circuit of the present invention has less grid width, is about 1/4th of present structure under the condition of equal difference mode gain, this can save chip area largely.

(4) secondary amplification circuit of Cai Yonging is simple in structure, does not need the bias voltage that provides extra, makes interface circuit of the present invention implement easily.

(5), make that the small-signal differential mode gain of interface circuit of the present invention is very high, thereby make that interface circuit of the present invention promptly can be used for can be used for the system of 5V again in the system of 3.3V owing to the introducing of special construction secondary amplification circuit.

Description of drawings

Fig. 1 is circuit theory diagrams of the present invention;

Fig. 2 is the magnitude of voltage at circuit of the present invention node N2 and N3 place when the ac small signal scanning analysis;

Fig. 3 is the Vdd current scanning curve of the different bias voltage correspondences of the present invention when working under 3.3V;

Fig. 4 is a functional simulation oscillogram of the present invention;

Fig. 5 is the scanning curve that bias levels different among the present invention influences output waveform;

Fig. 6 is the schematic diagram of the CMOS differential amplifier of the present PMOSFET input of using always.

Embodiment

As shown in Figure 1, interface circuit of the present invention has three parts to be formed, and is respectively frame of broken lines I1, I2 and the I3 among Fig. 1.I1 is the CMOS differential amplifier of NMOSFET input; Wherein InP and InN are respectively the normal phase input end and the inverting inputs of two-stage CMOS differential amplifier of the present invention; M1 and M2 are that a pair of NMOS pipe constitutes differential pair tube; M3 and M5, M4 and M6 and M7 and M8 are the loads that two scaled mirror current sources are M1 and M2; This plays a part M7 and M8 both-end output simultaneously to current mirror and transfers single-ended output to; M9 provides the required direct current of difference channel work (tail current), and the drain electrode of M9 is exactly node N1.

The CMOS differential amplifier of the PMOSFET of common structure input at present comprises differential pair tube, load pipe and tail current part equally, but because the carrier mobility of PMOS pipe is lower, reach certain difference mode gain, the grid breadth length ratio of its differential pair tube can be very high, this certainly will cause differential pair tube can occupy very big chip area, this is the defective of present common structure, also is insoluble problem.The interface circuit of introduction of the present invention wherein I1 part just can reduce the area of differential pair tube about half, because the carrier mobility of NMOS pipe is about the twice of PMOS pipe.I2 in the circuit of the present invention partly is a kind of amplifier of special construction, and Ma is an amplifier tube, and Mb is the load pipe of Ma, and the grid level of this load pipe does not need additionally to connect bias level, as long as link to each other with ground GND.Fig. 2 is the ac small signal scanning analysis waveform of interface circuit of the present invention, the spoke value of out2 (being the magnitude of voltage of N3 node among Fig. 1) is about 5 times of out1 (being the magnitude of voltage of N2 node among Fig. 1) as can be seen from Figure, this explanation is by the introducing of I2, improved the small-signal differential mode gain of interface circuit widely, thereby the chip area of differential pair tube can be reduced into originally below 1/4th fully, this has solved, and differential pair tube occupies the excessive problem of chip area in the present CMOS difference interface circuit.

Interface circuit of the present invention is mainly used its differential mode characteristic when practical application, its differential mode small signal gain A _V=A _VD* A _V2, A wherein _VDBe the small-signal differential mode gain of I1 part, A _V2Be the small signal gain of I2 part, the gain of I3 buffer stage puts aside; Below we with regard to Fig. 1 respectively to A _VDAnd A _V2Analyze:

The I1 part, the intuitive analysis of its primary differential signal module feature is as follows: suppose that all pipes all are operated in the saturation region, the differential mode level is-V between InP and the InN _Id, the mirror image proportionate relationship of M4 and M6 and M3 and M5 is 1:K, the channel transconductance of M1 or M2 is g _M1,2As Fig. 2, during differential mode work, the source electrode equivalence ground connection of M1 and M2; Flow through leakage current (direction is seen shown in Fig. 2 arrow, and the is together following) id2=0.5g of M2 and M4 _M1,2V _Id, flow through the leakage current id1=0.5g of M1 and M3 _M1,2V _IdThe passing ratio mirror, the leakage current that flows through M6 is K*id2, the leakage current that flows through M5 and M7 is K*id1; M7 and M8 are 1: 1 mirror current sources, and the leakage current among the M8 also is K*id1 so; KCL knows by Kirchhoff's current law (KCL), current i out=K* (the id1+id2)=K*g of output node (drain electrode of M6 and M8) _M1,2V _Id, the product of the small-signal output resistance rout of this electric current and output node is exactly a small-signal differential mode output voltage; This differential mode output level adds that the DC level of output node has just constituted final output transient level value.

I1 part small-signal differential mode gain quantitative analysis: by intuitive analysis above as can be known, the small-signal differential mode gain A VD approximate representation of this differential amplifier is as follows:

$A_{\mathrm{VD}}=\frac{V_{\mathrm{out}}}{V_{\mathrm{id}}}=K\·\frac{{-g}_{m\mathrm{1,2}}}{g_{\mathrm{ds}6}+g_{\mathrm{ds}8}}---\left(1\right)$

In the following formula $g_m$ ${\mathrm{1,2}}_{}=\sqrt{{2K}^{\&prime;}{(W/L)}_{\mathrm{1,2}}\left|{\mathrm{<figure-callout\; id="1"\; label="I\; D"\; filenames="S2007101355839E00011.png,S2007101355839E00021.png"\; state="\{\{state\}\}">I</figure-callout>}}_D\right|}---\left(2\right)$

I _D1，2＝ISS/2＝I _D5，6/K (3)

$I_{\mathrm{SS}}=\frac{K^{\&prime;}{W}_9}{{2L}_9}{(V_{\mathrm{GS}9}-V_T)}^2(1+{\mathrm{\&lambda;}}_9{V}_{\mathrm{DS}9})---\left(4\right)$

g _ds6≈Kλ ₆I _SS/2g _ds8≈Kλ ₈I _SS/2 (5)

To can get A in formula (2) (3) (5) the substitution formula (1) _VDApproximate expression be:

$A_{\mathrm{VD}}\&ap;\frac{-2}{{\mathrm{\&lambda;}}_6+{\mathrm{\&lambda;}}_8}\sqrt{K^{\&prime;}{(W/L)}_{\mathrm{1,2}}\&CenterDot;\frac{1}{I_{\mathrm{SS}}}}---\left(6\right)$

The quantitative analysis of I2 part small signal gain: this part-structure is simple, and the expression formula that is easy to just can to obtain its small signal gain is as follows:

$A_{V2}=\frac{V_{\mathrm{out}}}{V_{\mathrm{in}}}=\frac{-g_{\mathrm{ma}}}{g_{\mathrm{dsa}}+g_{\mathrm{dsb}}}=\frac{-1}{{\mathrm{\&lambda;}}_a+{\mathrm{\&lambda;}}_b}\sqrt{\frac{2K^{\&prime;}{W}_a}{I_{\mathrm{Da},b}{L}_a}}---\left(7\right)$

$I_{\mathrm{Da},b}=\frac{K^{\&prime;}{W}_b}{{2L}_b}{(-V_{\mathrm{DD}}-V_T)}^2(1+{\mathrm{\&lambda;}}_b{V}_{\mathrm{DSb}})---\left(8\right)$

More than K '=μ in eight formula _nC _OxWith λ be the technology decision of IC manufacturing works, know by formula (4), (6) and (7), as long as the suitable grid breadth length ratio of adjustment M1, M2, M9 and Ma just can obtain needed difference mode gain; Iss has directly determined the power consumption of circuit, as shown in Figure 3, at Vdd=3.3V, during the difference mode signal of the 200mV of input 200MHz, scans the pairing Vdd transient current of different Vbias, and average power consumption is between 0.6*3.3mW～0.9*3.3mW as can be seen.

CMOS type difference interface circuit of the present invention not only can be that the RSDS conversion of signals of 200mV is logic levels such as TTL, CMOS, LVCMOS with representative value, also can be that the LVDS conversion of signals of 350mV is logic levels such as TTL, CMOS, LVCMOS with representative value.Shown in Figure 4 is exactly the simulation waveform that the difference-mode input small-signal of 200mV is converted to the LVCMOS level of 3.3V.

Shown in Figure 5 is the output waveform of the different bias level Vbias correspondence of scanning.Simulated conditions is Vdd=5V among the figure, the difference mode signal of the 200mV of input 200MHz; Vbias needs only the threshold voltage greater than the NMOS pipe as can be seen, and interface circuit of the present invention all can operate as normal.

Claims (2)

1. a CMOS type difference interface circuit comprises the difference input to pipe, load pipe, tail current and buffering output, it is characterized in that differential input stage even contains 4 PMOS pipes, is respectively M3, M4, M5 and M6; 5 NMOS pipes are respectively M1, M2, M7, M8 and M9; The common NMOSFET of formation imports the elementary amplifying circuit of CMOS difference, and wherein, M1 and M2 are a pair of NMOS pipes, constitute differential pair tube; M3 and M5, M4 and M6 and M7 and M8 are the loads that two scaled mirror current sources are M1 and M2; This transfers both-end output to single-ended output simultaneously to current mirror M7 and M8, and it is tail current that M9 provides the required direct current of difference channel work;

Cascade contains the secondary amplification circuit of 1 PMOS pipe Mb and 1 NMOS pipe Ma after the elementary amplifying circuit, and wherein, Ma is an amplifier tube, and Mb is the load pipe of Ma, and the grid level of this load pipe links to each other with ground GND;

Cascade contains the buffering output of two guiders after the secondary amplification circuit;

In the foregoing circuit, the substrate of all PMOS pipes meets high level VDD, and the substrate of all NMOS pipes meets low level GND.

2. CMOS type difference interface circuit according to claim 1 is characterized in that circuit connecting relation is as follows:

Input port InP and InN are connected the grid of M1 and M2 respectively, and the source electrode of M2, two metal-oxide-semiconductors of M1 and the drain electrode of metal-oxide-semiconductor M9 link together; Totally 4 nodes of the grid of the drain electrode of M1, two metal-oxide-semiconductors of M3 and M3, two metal-oxide-semiconductors of M5 interconnects; Totally 4 nodes of the grid of the drain electrode of M2, two metal-oxide-semiconductors of M4 and M4, two metal-oxide-semiconductors of M6 interconnects; Mb, M3, M4, M5 and the M6 source electrode of totally 5 metal-oxide-semiconductors receive on the power vd D; The drain electrode of M6, two metal-oxide-semiconductors of M8 and the grid of metal-oxide-semiconductor Ma interconnect; Totally 4 nodes of the grid of the drain electrode of M5, two metal-oxide-semiconductors of M7 and M7, two metal-oxide-semiconductors of M8 interconnects; M7, M8, M9, the Ma grid of the source electrode of totally 4 metal-oxide-semiconductors and metal-oxide-semiconductor Mb receive on the ground GND; The drain electrode of Ma, two metal-oxide-semiconductors of Mb and the input of guider INV1 interconnect; The grid of metal-oxide-semiconductor M9 links to each other with input port Vbias; The output of guider INV1 links to each other with the input of guider INV2; The output of guider INV2 links to each other with output port OUT.

Images