CN102420602B - Power converter and differential circuit - Google Patents
Power converter and differential circuit Download PDFInfo
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- CN102420602B CN102420602B CN201110409205.1A CN201110409205A CN102420602B CN 102420602 B CN102420602 B CN 102420602B CN 201110409205 A CN201110409205 A CN 201110409205A CN 102420602 B CN102420602 B CN 102420602B
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Abstract
The invention provides a differential circuit, which comprises an input stage circuit containing a first differential transistor and a second differential transistor, wherein a gate of the first differential transistor serves as a first voltage input by the first input end, and a gate of the second differential transistor serves as a second voltage input by the second input end; an amplification output stage circuit connected with the input stage circuit and used for amplifying a difference between the first voltage and the second voltage and then outputting the amplified difference; and a comparison output stage circuit connected with the input stage circuit and used for comparing whether the difference between the first voltage and the second voltage is greater than a first preset value. Compared with prior art, the power converter and the differential circuit disclosed by the invention enable an error amplifier and an overvoltage comparer and/or an under-voltage comparer to multiplex the input stage circuit so as to avoid an additional relative deviation caused by the process when an independent input stage circuit is used and further enable the overvoltage comparer to work more steadily.
Description
[technical field]
The present invention relates to Power Management Design field, particularly relate to a kind of power supply changeover device and interior difference channel thereof.
[background technology]
In DC-DC power converter, generally comprise error amplifier, under-voltage comparator and overvoltage comparator.The function of error amplifier is detect output feedback voltage and reference voltage poor, works output voltage is adjusted to and meets the output feedback voltage state equal with reference voltage together with whole feedback loop.Whether under-voltage comparator detects output voltage in under-voltage condition, is generally set as 95% of target output voltage, and this value is under-voltage detection threshold.Whether overvoltage comparator detects output voltage in overvoltage condition, is generally set as 105% of target output voltage, and this value is overvoltage detection threshold.In prior art, for general completely independently three circuit that adopt of the error amplifier in power converter, under-voltage comparator and overvoltage comparator, be that each independent circuits adopts independently differential input stage, because each differential input stage in integrated circuit fabrication process exists random input deviation, for example, for error amplifier, there is certain deviation to the threshold voltage of pipe in two difference input, and this deviation is random between chip.Equally, also there is certain deviation to pipe in the difference input of under-voltage comparator and overvoltage comparator, and these deviations and error amplifier input deviation are inconsistent.Therefore, just caused existing because technique causes additional relative deviation between the output feedback voltage of error amplifier adjustment and the detection threshold of under-voltage and overvoltage comparator.Due to the existence of relative deviation, may cause described overvoltage comparator or under-voltage comparator to occur job insecurity phenomenon.Take overvoltage comparator as example, the existence of relative deviation may cause the overvoltage detection threshold of some chip less than normal, as become 101% from set 105%.And overvoltage comparator is when overvoltage condition detected, can reduces duty ratio by stopcock, thereby reduce output voltage to avoid output overvoltage.In the time that overvoltage detection threshold becomes too small; in addition due to factors such as some noises; even if just may cause in the time that error amplifier carries out normal loop adjustment; also there will be the situation of overvoltage comparator error detection to overvoltage condition; thereby the normal adjustment of the mushing error that leads to errors amplifier, and produce wild effect.
Therefore, be necessary to propose a kind of improved technical scheme and solve the problems referred to above.
[summary of the invention]
One of object of the present invention is to provide a kind of difference channel of power supply changeover device, and it can avoid error amplifier and overvoltage comparator because technique causes additional relative deviation, thereby makes overvoltage comparator work more stable.
Two of object of the present invention is to provide a kind of power supply changeover device that comprises difference channel, and described difference channel can avoid error amplifier and overvoltage comparator because technique causes additional relative deviation, thereby makes the work of overvoltage comparator more stable.
To achieve these goals, according to an aspect of the present invention, the present invention proposes a kind of difference channel, it comprises: the input stage circuit that comprises the first difference transistor and the second difference transistor, the grid of the first difference transistor is inputted the first voltage as first input end, and the grid of the second difference transistor is as the second input input second voltage; The amplification output-stage circuit being connected with described input stage circuit, for exporting after poor amplification of the first voltage and second voltage; The comparison output-stage circuit being connected with described input stage circuit, for comparing the first voltage and poor first predetermined value that whether is greater than of second voltage.
In a further embodiment, described input stage circuit also comprises the first current source, and one end of the first current source is connected with the source class of the second difference transistor with the source class of the first difference transistor.
In a further embodiment, described amplification output-stage circuit comprises the first transistor and the transistor seconds that are connected between VDD-to-VSS, node between the first transistor and transistor seconds is as the output of described amplification output-stage circuit, in the time that described the first voltage equals described second voltage, electric current on the first transistor is directly proportional to the electric current on the first difference transistor, and the electric current on transistor seconds is directly proportional to the electric current on the second difference transistor.
In a further embodiment, described relatively output-stage circuit comprises inverter and is connected on the 3rd transistor and the second current source between VDD-to-VSS, node between the second current source and the 3rd transistor connects the input of described inverter, the output of described inverter reflects whether the difference between the first voltage and second voltage is greater than the first predetermined value, in the time that described the first voltage equals described second voltage, the electric current on the 3rd transistor is directly proportional to the electric current on the first difference transistor.
In a further embodiment, described relatively output-stage circuit comprises the 4th transistor and the 5th transistor that are connected between VDD-to-VSS, to the second current source of the 4th transistor and the 5th transistorized intermediate node Injection Current, the inverter that its input is connected with the 5th transistorized intermediate node with the 4th transistor, whether the difference between output output reflection the first voltage and the second voltage of described inverter is greater than the first predetermined value, in the time that described the first voltage equals described second voltage, electric current on the 4th transistor is directly proportional to the electric current on the first difference transistor, electric current on the 5th transistor is directly proportional to the electric current on the second difference transistor.
According to a further aspect in the invention, the present invention proposes a kind of power supply changeover device, it comprises pulse width modulated comparator, logical circuit, output circuit, feedback circuit and difference channel, described difference channel comprises input stage circuit, the amplification output-stage circuit being connected with described input stage circuit and the comparison output-stage circuit being connected with described input stage circuit, described input stage circuit comprises the first difference transistor and the second difference transistor, the grid of the first difference transistor inputs as first input end the feedback voltage that described feedback circuit provides, the grid of the second difference transistor is as the second input input reference voltage, described amplification output-stage circuit will be exported to described pulse width modulated comparator after described feedback voltage and the poor amplification of described reference voltage, whether the difference of the described relatively more described feedback voltage of output-stage circuit and described reference voltage is greater than overvoltage threshold, and comparative result is exported to described logical circuit, described pulse width modulated comparator generates pulse-width signal according to the signal of described amplification output-stage circuit output, and exports to described logical circuit, described logical circuit is given described output circuit according to the comparison signal output control signal of described pulse-width signal and the output of described relatively output-stage circuit, described output circuit generates output voltage according to the control signal of described logical circuit, described feedback circuit produces described feedback voltage according to the output voltage of described output circuit.
Compared with prior art, in the present invention by making error amplifier and overvoltage comparator, thereby while avoiding using independent input level circuit because technique causes additional relative deviation, and then make overvoltage comparator work more stable.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.Wherein:
Fig. 1 is the circuit diagram in one embodiment of difference channel of error amplifier in the present invention and the multiplexing input stage circuit of overvoltage comparator;
Fig. 2 is the circuit diagram in another embodiment of difference channel of error amplifier in the present invention and the multiplexing input stage circuit of overvoltage comparator;
Fig. 3 is the circuit diagram in one embodiment of difference channel of error amplifier in the present invention and the multiplexing input stage circuit of under-voltage comparator;
Fig. 4 is the circuit diagram in another embodiment of difference channel of error amplifier in the present invention and the multiplexing input stage circuit of overvoltage comparator; With
Fig. 5 is the exemplary plot of the difference channel of error amplifier, overvoltage comparator and the multiplexing input stage circuit of under-voltage comparator in the present invention application in voltage descending DC-DC converter.
[embodiment]
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.The word that " connection ", " joining ", " being connected to " etc. herein relates to electric connection all can represent direct or indirect electric connection.
Alleged " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention herein.Different local in this manual " in one embodiment " that occur not all refer to same embodiment, neither be independent or the embodiment mutually exclusive with other embodiment optionally.
The invention provides a kind of difference channel, it forms after by error amplifier and overvoltage comparator and/or the multiplexing input stage circuit of under-voltage comparator.Described difference channel comprises input stage circuit, the amplification output-stage circuit being connected with described input stage circuit and the comparison output-stage circuit being connected with described input stage circuit.Described input stage circuit comprises the first difference transistor and the second difference transistor, and the grid of the first difference transistor is inputted the first voltage as first input end, and the grid of the second difference transistor is as the second input input second voltage.Described amplification output-stage circuit is for exporting after poor amplification of the first voltage and second voltage.Whether described relatively output-stage circuit is greater than the first predetermined value or no second predetermined value that is less than for the difference that compares the first voltage and second voltage.
Please refer to shown in Fig. 1 its difference channel for the error amplifier in the present invention and the multiplexing input stage circuit of overvoltage comparator circuit diagram in one embodiment.
In the present embodiment, the input stage circuit of described difference channel comprises the first current source I1, PMOS difference transistor MP1, MP2, nmos pass transistor MN1 and MN3.A termination power VIN of the first current source I1, the source electrode of another termination PMOS difference transistor MP1 and MP2, the drain electrode of PMOS difference transistor MP1 is connected with the drain electrode of nmos pass transistor MN1, and the drain electrode of PMOS difference transistor MP2 is connected with the drain electrode of nmos pass transistor MN3.The source ground of nmos pass transistor MN1 and MN3.The grid of PMOS difference transistor MP1 meets feedback voltage FB, and the grid of PMOS difference transistor MP2 meets reference voltage Ref.
The amplification output-stage circuit of described difference channel comprises the PMOS transistor MP3 and the nmos pass transistor MN2 that are connected between power supply VIN and ground, is connected in PMOS transistor MP4 and nmos pass transistor MN4 between power supply VIN and ground.The grid of nmos pass transistor MN2 is connected with the grid of nmos pass transistor MN1, and the grid of nmos pass transistor MN4 is connected with the grid of nmos pass transistor MN3, and the grid of PMOS transistor MP3 is connected with the grid of PMOS transistor MP4.Like this, nmos pass transistor MN4 and MN3 form current mirror, and nmos pass transistor MN2 and MN1 form current mirror, and PMOS transistor MP4 and MP3 form current mirror.The intermediate node of PMOS transistor MP4 and nmos pass transistor MN4 is the output of this amplification output-stage circuit, its output error amplifying signal EAO.
This amplification output-stage circuit forms error amplifier together with described input stage circuit, for amplifying the poor of feedback voltage FB and reference voltage Ref, this error amplifier can be operated in the feedback control loop in DC-to-DC converter, larger gain is provided, realizes loop feedback voltage FB is adjusted and equals reference voltage Ref.In the time that feedback voltage FB equals reference voltage Ref, the electric current of PMOS transistor MP4 is directly proportional to the electric current of PMOS difference transistor MP1, and the electric current of the electric current of nmos pass transistor MN4 and PMOS difference transistor MP2 is directly proportional.
The comparison output-stage circuit of described difference channel comprises the second current source I2 and the nmos pass transistor MN5 that are connected between power supply VIN and ground, and inverter INV1 and the INV2 of series connection, the wherein intermediate node of second source I2 and nmos pass transistor MN5 described in the input termination of INV1, the output of described inverter INV2 is the output of this comparison output-stage circuit, its output comparison signal OVP.The grid of described nmos pass transistor MN5 is connected with the grid of described nmos pass transistor MN1, and both form current mirror, and in the time that feedback voltage FB equals reference voltage Ref, the electric current of nmos pass transistor MN5 is directly proportional to the electric current of PMOS difference transistor MP1.In the time that the electric current of nmos pass transistor MN5 equals the electric current of described the second current source I2, described comparison signal OVP upset, now the difference between described feedback voltage FB and described reference voltage Ref equals predetermined excess pressure threshold value.
This comparison output-stage circuit forms overvoltage comparator together with described input stage circuit, when its difference at described feedback voltage FB and described reference voltage Ref is greater than predetermined excess pressure threshold value, and its upset output over-voltage protection signal (being useful signal).
In the present embodiment, the useful signal of comparison signal OVP is high level signal, and the condition that comparison signal OVP is turned to high level from low level is: the electric current of nmos pass transistor MN5 becomes the electric current of nmos pass transistor MN5 to be less than the situation of the electric current of the second current source I2 from being greater than the curent change of the second current source I2.Suppose that the width and the length that in design, meet nmos pass transistor MN5 and MN1 all equate, the electric current of the current replication nmos pass transistor MN1 of nmos pass transistor MN5, it copies ratio is 1: 1., in the time that the electric current of nmos pass transistor MN5 equals the electric current of the second current source I2, the electric current of nmos pass transistor MN1 also equals the electric current of the second current source I2.Because the electric current of nmos pass transistor MN1 equals the electric current of PMOS difference transistor MP1, so when the output signal OVP upset of described relatively output circuit, the electric current of PMOS difference transistor MP1 also equals the electric current of the second current source I2.For PMOS difference transistor MP1 and MP2, in the time that both electric currents equate, its gate source voltage is equal, and because the source electrode of PMOS difference transistor MP1 and MP2 links together, its source voltage equates, so feedback voltage FB equals reference voltage Ref.Equal again the electric current of the first current source I1 according to the electric current sum of the electric current of Kirchhoff's law PMOS difference transistor MP1 and PMOS difference transistor MP2, so meet the condition that feedback voltage FB equals reference voltage Ref be, the electric current of PMOS difference transistor MP1 should equal the electric current of PMOS difference transistor MP2, and equals I1/2.For being operated in the situation of small-signal, difference transistor is operated in saturation region, and its small signal electric current meets:
ΔI＝-|ΔVgs|.gm (1)
Wherein Δ I is curent change, and Δ Vgs is that gate source voltage changes, the mutual conductance that gm is difference transistor.
The state that the state that relatively electric current of PMOS difference transistor MP1 and MP2 is equal and the electric current of PMOS difference transistor MP1 equal the electric current of the second current source I2 can obtain the curent change Δ I=I2-I1/2 (2) of PMOS difference transistor MP1
Wherein I2 is the current value of the second current source I2, and I1 is the current value of the first current source II.
According to formula (1), (2) can obtain: | Δ Vgs|=-(I2-I1/2)/gm=(I1/2-I2)/gm (3)
So in the time that the difference of feedback voltage FB and reference voltage Ref equals (I1/2-I2)/gm (being predetermined excess pressure threshold value), the electric current of PMOS difference transistor MP1 equals the electric current of the second current source I2, causes the comparison signal OVP of described relatively output circuit output to be turned into high level from low level.I2 also can design with I1 proportional, and as I2=I1/4 (4), formula (3) is reduced to | Δ Vgs|=I1/ (4.gm) (5)
Further design PMOS difference transistor MP1 and MP2 are in the time of sub-threshold region, known according to subthreshold value MOS characteristic formula:
gm＝I
D/(ξ.VT) (6)
Wherein I
dfor metal-oxide-semiconductor drain current, VT is thermal voltage, and ξ is process constant.
Here for PMOS difference transistor MP1, in the time that the comparison signal OVP of described relatively output circuit output is turned into high level from low level, its I
d=I2
In the time of I2=I1/4, bring formula (5) into, (6) can obtain:
|ΔVgs|＝I1/(4.I2/(ξ.VT))＝ξ.VT
Designing different I2 and the ratio of I1, can obtain different | Δ Vgs|, obtains different predetermined excess pressure threshold values.
Therefore, the turn threshold of described overvoltage comparator is VFB=VRef+ ξ .VT, and when feedback voltage V FB is above than the high ξ .VT of reference voltage V Ref, comparison signal OVP exports high level, represents feedback overvoltage FB overvoltage, i.e. output voltage overvoltage.
Please refer to shown in Fig. 2 its difference channel for the error amplifier in the present invention and the multiplexing input stage circuit of overvoltage comparator circuit diagram in another embodiment.Identical with Fig. 1 of described input stage circuit in Fig. 2 and the circuit structure of described amplification output-stage circuit.Not identical with Fig. 1 of the circuit structure of the comparison output-stage circuit in Fig. 2, is introduced described relatively output-stage circuit below in detail.
In the present embodiment, the comparison output-stage circuit of described difference channel comprises the PMOS transistor MP5 and the nmos pass transistor MN5 that are connected between power supply VIN and ground, to the second current source I2 of the intermediate node Injection Current of PMOS transistor MP5 and nmos pass transistor MN5, and inverter INV1, the input termination PMOS transistor MP5 of wherein said inverter INV1 and the intermediate node of nmos pass transistor MN5, the output of described inverter INV1 is the output of this comparison output-stage circuit, its output comparison signal OVP.The grid of described PMOS transistor MP5 is connected with the grid of described PMOS transistor MP3, and the grid of described nmos pass transistor MN5 is connected with the grid of described nmos pass transistor MN3.Like this, PMOS transistor MP3 and MP5 form current mirror, and nmos pass transistor MN3 and MN5 form current mirror.In the time that described feedback voltage FB equals described reference voltage Ref, the electric current of PMOS transistor MP5 is directly proportional to the electric current of PMOS difference transistor MP1, and the electric current of nmos pass transistor MN5 is directly proportional to the electric current of PMOS difference transistor MP2.In the time that the electric current of nmos pass transistor MN5 equals the electric current of described PMOS transistor MP5 and the electric current sum of the second current source I2, described comparison signal OVP upset, now the difference between described feedback voltage FB and described reference voltage Ref equals predetermined excess pressure threshold value.
This comparison output-stage circuit forms overvoltage comparator together with described input stage circuit, when its difference at feedback voltage FB and described reference voltage Ref is greater than this predetermined excess pressure threshold value, and its upset output over-voltage protection signal.
According to Fig. 1 in the overvoltage comparator principle of similitude, when known comparison signal OVP upset, VFB-VRef=I2/gm, wherein VFB is the voltage of feedback voltage FB, VRef is the voltage of reference voltage Ref, and I2 is the electric current of the second current source I2, the mutual conductance that gm is difference transistor.Design different I2 values, can obtain different predetermined excess pressure threshold values.
Please refer to shown in Fig. 3 its difference channel for the error amplifier in the present invention and the multiplexing input stage circuit of under-voltage comparator circuit diagram in one embodiment.Identical with Fig. 2 of described input stage circuit in Fig. 3 and the circuit structure of described amplification output-stage circuit.Not identical with Fig. 2 of the circuit structure of the comparison output-stage circuit in Fig. 3, is introduced described relatively output-stage circuit below in detail.
In the present embodiment, described relatively output-stage circuit comprises the PMOS transistor MP5 and the nmos pass transistor MN5 that are connected between power supply VIN and ground, extract the second current source I2 of electric current from the intermediate node of PMOS transistor MP5 and nmos pass transistor MN5, and inverter INV1 and the INV2 of series winding, the wherein input termination PMOS transistor MP5 of INV1 and the intermediate node of nmos pass transistor MN5, the output of described inverter INV2 is the output of this comparison output-stage circuit, its output comparison signal UVP.The grid of described PMOS transistor MP5 is connected with the grid of described PMOS transistor MP3, the grid of described nmos pass transistor MN5 is connected with the grid of described nmos pass transistor MN3, like this, PMOS transistor MP3 and MP5 form current mirror, and nmos pass transistor MN3 and MN5 form current mirror.In the time that feedback voltage FB equals reference voltage Ref, the electric current of PMOS transistor MP5 is directly proportional to the electric current of PMOS difference transistor MP1, and the electric current of nmos pass transistor MN5 is directly proportional to the electric current of PMOS difference transistor MP2.In the time that the electric current of PMOS transistor MP5 equals the electric current of nmos pass transistor MN5 and the electric current sum of current source I2, described comparison signal UVP upset, now the difference between described feedback voltage FB and described reference voltage Ref equals predetermined under-voltage threshold value.
This comparison output-stage circuit forms under-voltage comparator together with described input stage circuit, when its difference at feedback voltage FB and described reference voltage Ref is less than predetermined under-voltage threshold value, and its upset output under-voltage protection signal.
According to Fig. 2 in the overvoltage comparator principle of similitude, when known comparison signal UVP upset, VBF-VRef=-I2/gm, wherein VFB is the magnitude of voltage of feedback voltage FB, VRef is the magnitude of voltage of reference voltage Ref, I2 is the electric current of the second current source I2.Design different I2 values, can obtain different under-voltage threshold values.
Please refer to shown in Fig. 4 its difference channel for the error amplifier in the present invention and the multiplexing input stage circuit of under-voltage comparator circuit diagram in another embodiment.
In the present embodiment, the input stage circuit of described difference channel comprises the first current source I1, PMOS difference transistor MP1 and MP2, resistance R 1 and R3, nmos pass transistor MNC1 and MNC3, nmos pass transistor MN1 and MN3.A termination power VIN of the first current source I1, the source electrode of another termination PMOS difference transistor MP1 and MP2, resistance R 1, nmos pass transistor MNC1 and MN1 are connected between the drain electrode and ground of PMOS difference transistor MP1 successively, the grid of nmos pass transistor MNC1 is connected with the drain electrode of PMOS difference transistor MP1, resistance R 3, nmos pass transistor MNC3 and MN3 are connected between the drain electrode and ground of PMOS difference transistor MP2 successively, and the grid of nmos pass transistor MNC3 is connected with the drain electrode of PMOS difference transistor MP2.The grid of PMOS difference transistor MP1 meets feedback voltage FB, and the grid of PMOS difference transistor MP2 meets reference voltage Ref.
The amplification output-stage circuit of described difference channel comprises the PMOS transistor MP3 and the MPC3 that are connected on successively between power supply VIN and ground, resistance R 2, nmos pass transistor MNC2 and MN2; Be connected on successively PMOS transistor MP4 and MPC4 between power supply VIN and ground, nmos pass transistor MNC4 and MN4.The grid of PMOS transistor MP3 and MP4 is connected with the drain electrode of PMOS transistor MPC3, the grid of PMOS transistor MPC3 and MPC4 is connected with the drain electrode of nmos pass transistor MNC2, and the grid of nmos pass transistor MNC2, MN2, MNC4 and MN4 is connected with the grid of nmos pass transistor MNC1, MN1, MNC3 and MN3 respectively.The intermediate node of PMOS transistor MPC4 and nmos pass transistor MNC4 is the output of this amplification output-stage circuit, its output error amplifying signal EAO.
This amplification output-stage circuit forms error amplifier together with described input stage circuit, this error amplifier is the error amplifier with directly link structure, this structure is very high by the low-frequency gain design of error amplifier, to obtain very high gain around feedback, very high gain around feedback can be realized higher output voltage precision.But, in the time of comparator and the multiplexing described input stage circuit of described error amplifier, can not adopt the connected mode of Fig. 1～3, otherwise the speed of comparator can be very slow, causes normally using.
In the present embodiment, described relatively output-stage circuit comprises the PMOS transistor MP5 and the nmos pass transistor MN5 that are connected between power supply VIN and ground, be connected in PMOS transistor MP7 and nmos pass transistor MN7 between power supply VIN and ground, extract the second current source I2 of electric current from the intermediate node of PMOS transistor MP5 and nmos pass transistor MN5, and inverter INV1 and the INV2 of series winding, the wherein input termination PMOS transistor MP5 of INV1 and the intermediate node of nmos pass transistor MN5, the output of described inverter INV2 is the output of this comparison output-stage circuit, its output comparison signal UVP.The grid of PMOS transistor MP5 is connected with the grid of PMOS transistor MP7, the grid of nmos pass transistor MN7 is connected with the drain electrode of nmos pass transistor MNC1, the grid of nmos pass transistor MN5 is connected with the drain electrode of nmos pass transistor MNC3, compared with comparison output-stage circuit in Fig. 3, the nmos pass transistor MN7 newly increasing and PMOS transistor MP7 are from lower end nmos pass transistor MN1 replica current, thus the delay of having avoided the cascade structure of error amplifier to cause.
For the purpose of simplifying the description, the present invention has only described PMOS as the execution mode of inputting pipe, to one skilled in the art, obviously also can adopt NMOS as the execution mode of inputting pipe.
According to description above, also can design the difference channel of error amplifier, overvoltage comparator and the multiplexing input stage circuit of under-voltage comparator.This difference channel comprises input stage circuit, under-voltage relatively output-stage circuit and relatively output-stage circuit of overvoltage, concrete structure such as can be in Fig. 1 increase again a comparison output-stage circuit as shown in Figure 3, the concrete those of ordinary skill connecting and illustrate in affiliated field can be learnt according to aforementioned description, repeats no more herein.
Please refer to shown in Fig. 5 the exemplary plot of the application of its difference channel for error amplifier, overvoltage comparator and the multiplexing input stage circuit of under-voltage comparator in the present invention in buck DC to dc power supply changeover device.
Described power supply changeover device comprises the difference channel EA_COMP that realizes error amplifier and overvoltage comparator, the multiplexing input stage circuit of under-voltage comparator, stabiloity compensation circuit (such as comprising R6 and C6), pwm comparator PWMC, logical circuit, output circuit is (such as comprising power switch MPX1 and MNX1, inductance L 1 and capacitor C 1), feedback circuit (such as comprising feedback resistance R1 and R2).Described difference channel EA_COMP is according to feedback voltage FB and reference voltage Ref output error amplifying signal EAO, overvoltage comparison signal OVP, under-voltage comparison signal UVP.Described pwm comparator PWMC, by error amplification signal EAO and sawtooth waveforms Vramp comparison, generates pulse-width signal PWMO, and exports to described logical circuit.Described logical circuit is given described output circuit according to overvoltage comparison signal OVP, under-voltage comparison signal UVP and output pulse width modulation signal PWMO output control signal.Described output circuit generates output voltage according to the control signal of described logical circuit.Described feedback circuit produces described feedback voltage FB according to the output voltage of described output circuit.In the present embodiment, described logical circuit produces power tube and drives signal PDRV and NDRV power ratio control switch MPX1 and MNX1.LX signal is output dc voltage VO after inductance L 1 and capacitor C 1 filtering.Voltage VO produces feedback voltage FB through feedback circuit.Form thus feedback circuit.
Here describe voltage-mode voltage descending DC-DC converter as an example of Fig. 5 example and adopted example of the present invention, but the present invention is obviously also suitable for various current-mode DC-to-DC converter, also be suitable for various booster type DC-to-DC converter, and other types DC-to-DC converter.
Principle of the present invention is by making the multiplexing input stage circuit of error amplifier and overvoltage comparator and/or under-voltage comparator, thereby avoids because technique causes additional relative deviation, so make overvoltage comparator and/or under-voltage comparator work more stable.
Above-mentioned explanation has fully disclosed the specific embodiment of the present invention.It is pointed out that and be familiar with the scope that any change that person skilled in art does the specific embodiment of the present invention does not all depart from claims of the present invention.Correspondingly, the scope of claim of the present invention is also not limited only to previous embodiment.
Claims (2)
1. a difference channel, is characterized in that, it comprises:
The input stage circuit that comprises the first difference transistor MP1 and the second difference transistor MP2, the grid of the first difference transistor is inputted the first voltage as first input end, and the grid of the second difference transistor is as the second input input second voltage;
The amplification output-stage circuit being connected with described input stage circuit, for exporting after poor amplification of the first voltage and second voltage;
The comparison output-stage circuit being connected with described input stage circuit, for comparing the first voltage and poor first predetermined value that whether is greater than of second voltage,
Described input stage circuit also comprises the first current source I1, resistance R 1 and R3, nmos pass transistor MNC1 and MNC3, nmos pass transistor MN1 and MN3, a wherein termination power VIN of the first current source I1, the source electrode of another termination difference transistor MP1 and MP2, resistance R 1, nmos pass transistor MNC1 and MN1 are connected between the drain electrode and ground of difference transistor MP1 successively, the grid of nmos pass transistor MNC1 is connected with the drain electrode of PMOS difference transistor MP1, resistance R 3, nmos pass transistor MNC3 and MN3 are connected between the drain electrode and ground of difference transistor MP2 successively, the grid of nmos pass transistor MNC3 is connected with the drain electrode of PMOS difference transistor MP2,
Described amplification output-stage circuit comprises the PMOS transistor MP3 and the MPC3 that are connected on successively between power supply VIN and ground, resistance R 2, nmos pass transistor MNC2 and MN2; Be connected on successively PMOS transistor MP4 and MPC4 between power supply VIN and ground, nmos pass transistor MNC4 and MN4, wherein the grid of PMOS transistor MP3 and MP4 is connected with the drain electrode of PMOS transistor MPC3, the grid of PMOS transistor MPC3 and MPC4 is connected with the drain electrode of nmos pass transistor MNC2, the grid of nmos pass transistor MNC2, MN2, MNC4 and MN4 is connected with the grid of nmos pass transistor MNC1, MN1, MNC3 and MN3 respectively, the intermediate node of PMOS transistor MPC4 and nmos pass transistor MNC4 is the output of this amplification output-stage circuit
Described relatively output-stage circuit comprises the PMOS transistor MP5 and the nmos pass transistor MN5 that are connected between power supply VIN and ground, be connected in PMOS transistor MP7 and nmos pass transistor MN7 between power supply VIN and ground, extract the second current source I2 of electric current from the intermediate node of PMOS transistor MP5 and nmos pass transistor MN5, and inverter INV1 and the INV2 of series winding, the wherein input termination PMOS transistor MP5 of INV1 and the intermediate node of nmos pass transistor MN5, the output of described inverter INV2 is the output of this comparison output-stage circuit, the grid of PMOS transistor MP5 is connected with the grid of PMOS transistor MP7, the grid of nmos pass transistor MN7 is connected with the drain electrode of nmos pass transistor MNC1, the grid of nmos pass transistor MN5 is connected with the drain electrode of nmos pass transistor MNC3, the grid of nmos pass transistor MN7 is connected with the grid of nmos pass transistor MN1, the grid of nmos pass transistor MN5 is connected with the grid of nmos pass transistor MN3.
2. a power supply changeover device, it comprises pulse width modulated comparator, logical circuit, output circuit and feedback circuit, it is characterized in that, it also comprises difference channel,
Described difference channel comprises input stage circuit, the amplification output-stage circuit being connected with described input stage circuit and the comparison output-stage circuit being connected with described input stage circuit, described input stage circuit comprises the first difference transistor MP1 and the second difference transistor MP2, the grid of the first difference transistor inputs as first input end the feedback voltage that described feedback circuit provides, the grid of the second difference transistor is as the second input input reference voltage, described amplification output-stage circuit will be exported to described pulse width modulated comparator after described feedback voltage and the poor amplification of described reference voltage, whether the difference of the described relatively more described feedback voltage of output-stage circuit and described reference voltage is greater than overvoltage threshold, and comparative result is exported to described logical circuit,
Described pulse width modulated comparator generates pulse-width signal according to the signal of described amplification output-stage circuit output, and exports to described logical circuit;
Described logical circuit is given described output circuit according to the comparison signal output control signal of described pulse-width signal and the output of described relatively output-stage circuit;
Described output circuit generates output voltage according to the control signal of described logical circuit;
Described feedback circuit produces described feedback voltage according to the output voltage of described output circuit,
Described input stage circuit also comprises the first current source I1, resistance R 1 and R3, nmos pass transistor MNC1 and MNC3, nmos pass transistor MN1 and MN3, a wherein termination power VIN of the first current source I1, the source electrode of another termination difference transistor MP1 and MP2, resistance R 1, nmos pass transistor MNC1 and MN1 are connected between the drain electrode and ground of difference transistor MP1 successively, the grid of nmos pass transistor MNC1 is connected with the drain electrode of PMOS difference transistor MP1, resistance R 3, nmos pass transistor MNC3 and MN3 are connected between the drain electrode and ground of difference transistor MP2 successively, the grid of nmos pass transistor MNC3 is connected with the drain electrode of difference transistor MP2, feedback voltage described in the grid of difference transistor MP1, reference voltage described in the grid of difference transistor MP2,
Described amplification output-stage circuit comprises the PMOS transistor MP3 and the MPC3 that are connected on successively between power supply VIN and ground, resistance R 2, nmos pass transistor MNC2 and MN2; Be connected on successively PMOS transistor MP4 and MPC4 between power supply VIN and ground, nmos pass transistor MNC4 and MN4, wherein the grid of PMOS transistor MP3 and MP4 is connected with the drain electrode of PMOS transistor MPC3, the grid of PMOS transistor MPC3 and MPC4 is connected with the drain electrode of nmos pass transistor MNC2, the grid of nmos pass transistor MNC2, MN2, MNC4 and MN4 is connected with the grid of nmos pass transistor MNC1, MN1, MNC3 and MN3 respectively, the intermediate node of PMOS transistor MPC4 and nmos pass transistor MNC4 is the output of this amplification output-stage circuit
Described relatively output-stage circuit comprises the PMOS transistor MP5 and the nmos pass transistor MN5 that are connected between power supply VIN and ground, be connected in PMOS transistor MP7 and nmos pass transistor MN7 between power supply VIN and ground, extract the second current source I2 of electric current from the intermediate node of PMOS transistor MP5 and nmos pass transistor MN5, and inverter INV1 and the INV2 of series winding, the wherein input termination PMOS transistor MP5 of INV1 and the intermediate node of nmos pass transistor MN5, the output of described inverter INV2 is the output of this comparison output-stage circuit, the grid of PMOS transistor MP5 is connected with the grid of PMOS transistor MP7, the grid of nmos pass transistor MN7 is connected with the drain electrode of nmos pass transistor MNC1, the grid of nmos pass transistor MN5 is connected with the drain electrode of nmos pass transistor MNC3, the grid of nmos pass transistor MN7 is connected with the grid of nmos pass transistor MN1, the grid of nmos pass transistor MN5 is connected with the grid of nmos pass transistor MN3.
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| CN201110409205.1A CN102420602B (en) | 2011-12-09 | 2011-12-09 | Power converter and differential circuit |
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| CN102420602B true CN102420602B (en) | 2014-05-28 |
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| CN104135149B (en) * | 2014-08-14 | 2016-09-21 | 西安电子科技大学 | A kind of selectable error amplifier and voltage comparator multiplex circuit |
| CN104333218A (en) * | 2014-11-05 | 2015-02-04 | 遵义师范学院 | Transconductance and output voltage comparison circuit for DC/DC (Direct Current/Direct Current) |
| CN108768352B (en) * | 2018-07-17 | 2023-11-03 | 上海艾为电子技术股份有限公司 | Comparator with a comparator circuit |
| CN112086945B (en) * | 2020-08-05 | 2022-04-01 | 广东美的白色家电技术创新中心有限公司 | Overvoltage protection circuit and electronic equipment |
| CN113849029B (en) * | 2021-09-26 | 2022-08-26 | 电子科技大学 | Under-voltage detection circuit of self-biased reference source |
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| CN101295927A (en) * | 2008-06-19 | 2008-10-29 | 北京中星微电子有限公司 | Modified oscillator and decompression power converter |
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