CN103956981B - A kind of operation amplifier circuit eliminating DC offset voltage - Google Patents
A kind of operation amplifier circuit eliminating DC offset voltage Download PDFInfo
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- CN103956981B CN103956981B CN201410137208.8A CN201410137208A CN103956981B CN 103956981 B CN103956981 B CN 103956981B CN 201410137208 A CN201410137208 A CN 201410137208A CN 103956981 B CN103956981 B CN 103956981B
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Abstract
The invention discloses a kind of operation amplifier circuit eliminating DC offset voltage, including two transadmittance gain unit, impedance unit, four switches, three electric capacity, wherein the first transadmittance gain unit includes 4 p-type metal-oxide-semiconductors, second transadmittance gain unit comprises 3 N-type metal-oxide-semiconductors, they use the differential pair input structure of tail current biasing, and Differential Input is converted into electric current；Impedance unit comprises 4 p-type metal-oxide-semiconductors and 4 N-type metal-oxide-semiconductors, uses the Telescopic cascode structure of Single-end output, converts the current into voltage and obtain enough gains；Electric capacity stores the misalignment signal caused because of factors such as process deviations, the negative feedback of DC maladjustment is realized under on-off control closed loop, the Differential Input Single-end output operational amplifier that the present invention proposes, sampled misalignment signal by electric capacity, can effectively solve the DC maladjustment problem that the factors such as process deviation cause, circuit structure is simple, can be compatible with standard CMOS process, it is easy to application.
Description
Technical field
The present invention relates to a kind of operation amplifier circuit, particularly relate to a kind of operation amplifier eliminating DC offset voltage
Device circuit.
Background technology
If amplifier input terminal voltage is 0V, then output end voltage also should be 0V, but it is true that input
End always has certain voltage for outfan during 0V, and this voltage is referred to as offset voltage.Consumer electronics market in recent years
Expanding, ic power field also develops rapidly, and requires more and more higher, to as electricity with properties of product
The reference voltage of source core requires increasingly harsher.The operational amplifier being applied in band-gap reference circuit, its
Offset voltage is often exaggerated and is embodied in benchmark output, the biggest on reference precision impact, it is therefore desirable to
Take measures to eliminate the DC maladjustment of amplifier.
Summary of the invention
Because the defect of prior art, the present invention provides a kind of operational amplifier electricity eliminating DC offset voltage
Road, including the first transadmittance gain unit, the second transadmittance gain unit, impedance unit, switch and electric capacity；
Described first transadmittance gain unit (1) includes 4 p-type metal-oxide-semiconductors, respectively p-type metal-oxide-semiconductor
(MP1), p-type metal-oxide-semiconductor (MP2), p-type metal-oxide-semiconductor (MP3) and p-type metal-oxide-semiconductor (MP4),
Described first transadmittance gain unit (1) is the differential input structure that cascade current source does tail current source formula,
Differential input voltage is converted into electric current, and the drain electrode of described p-type metal-oxide-semiconductor (MP1) connects described p-type MOS
The source electrode of pipe (MP2), the grid of described p-type metal-oxide-semiconductor (MP1) connects bias voltage (Vpb1),
The grid of described p-type metal-oxide-semiconductor (MP2) connects bias voltage (Vpb2), described p-type metal-oxide-semiconductor (MP3)
Source class, the source class of described p-type metal-oxide-semiconductor (MP4) and the drain of described p-type metal-oxide-semiconductor (MP2)
Being connected, the grid of described p-type metal-oxide-semiconductor (MP3) and the grid of described p-type metal-oxide-semiconductor (MP4) divide
Do not meet differential input end Vin and Vip of amplifier circuit；
Described second transadmittance gain unit (2) includes 3 N-type metal-oxide-semiconductors, respectively N-type metal-oxide-semiconductor
(MN1), N-type metal-oxide-semiconductor (MN2) and N-type metal-oxide-semiconductor (MN3), described second mutual conductance increasing
Benefit unit is the differential pair structure of tail current biasing, the source electrode of described N-type metal-oxide-semiconductor (MN1), described
The source electrode of N-type metal-oxide-semiconductor (MN2) and the drain of described N-type metal-oxide-semiconductor (MN3) are connected together,
The grid of described N-type metal-oxide-semiconductor (MN3) connects bias voltage (Vnb1)；
Described impedance unit comprises 4 p-type metal-oxide-semiconductors, respectively p-type metal-oxide-semiconductor (MP5), p-type
Metal-oxide-semiconductor (MP6), p-type metal-oxide-semiconductor (MP7) and p-type metal-oxide-semiconductor (MP8), and 4 N
Type metal-oxide-semiconductor, respectively N-type metal-oxide-semiconductor (MN4), N-type metal-oxide-semiconductor (MN5), N-type MOS
Pipe (MN6) and N-type metal-oxide-semiconductor (MN7), described impedance unit is the telescopic common source of Single-end output
Common gate structure, is converted into current signal voltage signal, and produces enough gains, described p-type MOS
The drain of pipe (MP5) connects the source electrode of described p-type metal-oxide-semiconductor (MP6), described p-type metal-oxide-semiconductor (MP7)
Drain connect the source electrode of described p-type metal-oxide-semiconductor (MP8), the grid of described p-type metal-oxide-semiconductor (MP5),
The grid of described p-type metal-oxide-semiconductor (MP7) is connected with described bias voltage (Vpb1), described p-type
The grid of metal-oxide-semiconductor (MP6), grid and the bias voltage (Vpb2) of described p-type metal-oxide-semiconductor (MP8)
Connect, the drain of described p-type metal-oxide-semiconductor (MP6), the grid of described N-type metal-oxide-semiconductor (MN4),
The drain of described N-type metal-oxide-semiconductor (MN4) and the grid of described N-type metal-oxide-semiconductor (MN5) are connected on
Together, the source electrode of described N-type metal-oxide-semiconductor (MN4), the grid of described N-type metal-oxide-semiconductor (MN6),
The drain of described N-type metal-oxide-semiconductor (MN6) and the grid of described N-type metal-oxide-semiconductor (MN7) are connected on
Together, the source electrode of described N-type metal-oxide-semiconductor (MN5) and the drain of described N-type metal-oxide-semiconductor (MN7)
It is connected together.
The mode of operation of described on-off control operation amplifier circuit, at sample phase, operation amplifier circuit
Misalignment signal is sampled and misalignment signal is stored on electric capacity, at imbalance elimination stage, operation amplifier
Device circuit formed DC maladjustment negative feedback, reduce operation amplifier signal imbalance.
Further, the drain electrode of p-type metal-oxide-semiconductor (MP3) described in described first transadmittance gain unit with
The source electrode of described N-type metal-oxide-semiconductor (MN4), the grid of N-type metal-oxide-semiconductor (MN6), N-type MOS
The drain of pipe (MN6) is connected, the drain electrode of p-type metal-oxide-semiconductor (MP4) and N-type metal-oxide-semiconductor (MN5)
Source electrode be connected with the drain of N-type metal-oxide-semiconductor (MN7).
Further, the drain electrode of N-type metal-oxide-semiconductor (MN1) described in described second transadmittance gain unit with
The drain electrode of p-type metal-oxide-semiconductor (MP5) described in described impedance unit and described p-type metal-oxide-semiconductor (MP6)
Source electrode be connected, the drain electrode of described N-type metal-oxide-semiconductor (MN2) and described p-type metal-oxide-semiconductor (MP7)
Drain electrode be connected with the source electrode of described p-type metal-oxide-semiconductor (MP8).
Further, described switch is clock switch, and quantity is 4, is respectively switch (S1), opens
Close (S2), switch (S3) and switch (S4), for coupling switch, described switch (S1), described in open
Closing (S3) and described switch (S4) is clock switch in the same direction, described switch (S2) be with S1,
The clock switch that S3, S4 reversely and not overlap.
Further, the quantity of described electric capacity is 3, respectively electric capacity (C1), electric capacity (C2) and electric capacity (C3),
For matching capacitance, the capacitance of electric capacity (C3) is more than described electric capacity (C1) and the electric capacity of described electric capacity (C2)
Amount, electric capacity (C3) is bulky capacitor.
Further, the two ends of described switch (S1) respectively with the described P in described first transadmittance gain unit
The grid of type metal-oxide-semiconductor (MP4) is connected with the grid of described p-type metal-oxide-semiconductor (MP3), described switch
(S2) two ends are connected with drain electrode and the outfan (Vout) of described p-type metal-oxide-semiconductor (MP8) respectively, institute
State the two ends of switch (S3) respectively with drain electrode and the described electric capacity (C1) of described p-type metal-oxide-semiconductor (MP8)
Positive pole be connected, described switch (S4) respectively with described outfan (Vout) and described electric capacity (C2)
Positive pole is connected, and the positive pole of described electric capacity (C3) is connected with described outfan (Vout), and ground (GND)
It is connected.
A kind of operation amplifier circuit eliminating DC offset voltage that the present invention provides, including two transadmittance gain
Unit, impedance unit, four switches, three electric capacity, wherein the first transadmittance gain unit includes 4
P-type metal-oxide-semiconductor, the second transadmittance gain unit comprises 3 N-type metal-oxide-semiconductors, and they use tail current inclined
The differential pair input structure put, is converted into electric current by Differential Input；Impedance unit comprises 4 p-types MOS
Pipe and 4 N-type metal-oxide-semiconductors, use the Telescopic cascode structure of Single-end output, convert the current into
Voltage also obtains enough gains；Electric capacity stores the misalignment signal caused because of factors such as process deviations, at switch
Control to realize under closed loop the negative feedback of DC maladjustment, thus realize the DC maladjustment that amplifier is low.The present invention is real
Show a kind of Differential Input Single-end output operational amplifier, sampled misalignment signal by electric capacity, it is possible to efficient solution
The DC maladjustment problem that the factors such as process deviation of determining cause, circuit structure is simple, energy and standard CMOS process
Compatible, it is easy to application.
Below with reference to accompanying drawing, the technique effect of design, concrete structure and the generation of the present invention is described further,
To be fully understood from the purpose of the present invention, feature and effect.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of a preferred embodiment of the present invention；
Fig. 2 is the state that the preferred embodiment of the present invention switchs in the course of the work.
Detailed description of the invention
Fig. 1 is the circuit diagram of a preferred embodiment of the present invention, a kind of fortune eliminating DC offset voltage
Calculate the circuit diagram of amplifier circuit, including first transadmittance gain unit the 1, second transadmittance gain unit 2, impedance list
Unit 3, switch and electric capacity；First transadmittance gain unit includes 4 p-type metal-oxide-semiconductors, respectively p-types MOS
Pipe MP1, p-type metal-oxide-semiconductor MP2, p-type metal-oxide-semiconductor MP3 and p-type metal-oxide-semiconductor MP4, first across
Leading gain unit is the differential input structure that cascade current source does tail current source formula, is turned by differential input voltage
Turning to electric current, the drain electrode of p-type metal-oxide-semiconductor MP1 connects the source electrode of p-type metal-oxide-semiconductor MP2, p-type MOS
The grid of pipe MP1 meets bias voltage Vpb1, and the grid of p-type metal-oxide-semiconductor MP2 meets bias voltage Vpb2,
The source class of p-type metal-oxide-semiconductor MP3, the source class of p-type metal-oxide-semiconductor MP4 and the leakage of p-type metal-oxide-semiconductor MP2
Level is connected, and the grid of p-type metal-oxide-semiconductor MP3 and the grid of p-type metal-oxide-semiconductor MP4 connect amplifier electricity respectively
Differential input end Vin and Vip on road；Second transadmittance gain unit includes 3 N-type metal-oxide-semiconductors, respectively
For N-type metal-oxide-semiconductor MN1, N-type metal-oxide-semiconductor MN2 and N-type metal-oxide-semiconductor MN3, the second mutual conductance increases
Benefit unit is the differential pair structure of tail current biasing, the source electrode of N-type metal-oxide-semiconductor MN1, N-type metal-oxide-semiconductor
The source electrode of MN2 and the drain of N-type metal-oxide-semiconductor MN3 are connected together, the grid of N-type metal-oxide-semiconductor MN3
Meet bias voltage Vnb1；Impedance unit comprises 4 p-type metal-oxide-semiconductors, respectively p-type metal-oxide-semiconductor MP5,
P-type metal-oxide-semiconductor MP6, p-type metal-oxide-semiconductor MP7 and p-type metal-oxide-semiconductor MP8, and 4 N-types MOS
Pipe, respectively N-type metal-oxide-semiconductor MN4, N-type metal-oxide-semiconductor MN5, N-type metal-oxide-semiconductor (MN6) and
N-type metal-oxide-semiconductor (MN7), impedance unit is the Telescopic cascode structure of Single-end output, by electric current
Signal is converted into voltage signal, and produces enough gains, and the drain of p-type metal-oxide-semiconductor MP5 connects p-type
The source electrode of metal-oxide-semiconductor MP6, the drain of p-type metal-oxide-semiconductor MP7 meets the source electrode of p-type metal-oxide-semiconductor MP8, P
The grid of type metal-oxide-semiconductor MP5, the grid of p-type metal-oxide-semiconductor MP7 are connected with bias voltage Vpb1, P
The grid of type metal-oxide-semiconductor MP6, the grid of p-type metal-oxide-semiconductor MP8 are connected with bias voltage Vpb2, P
The drain of type metal-oxide-semiconductor MP6, the grid of N-type metal-oxide-semiconductor MN4, the drain of N-type metal-oxide-semiconductor MN4
And the grid of N-type metal-oxide-semiconductor MN5 is connected together, the source electrode of N-type metal-oxide-semiconductor (MN4), N-type
The grid of metal-oxide-semiconductor MN6, the drain of N-type metal-oxide-semiconductor MN6 and the grid of N-type metal-oxide-semiconductor MN7
Pole is connected together, and the source electrode of N-type metal-oxide-semiconductor MN5 and the drain of N-type metal-oxide-semiconductor MN7 are connected together.
The mode of operation of on-off control operation amplifier circuit, in sample phase, operation amplifier circuit is to imbalance letter
Number carry out sampling and being stored on electric capacity by misalignment signal, in imbalance elimination stage, operation amplifier circuit shape
Become DC maladjustment negative feedback, reduce operation amplifier signal imbalance.P-type in first transadmittance gain unit
The drain electrode of metal-oxide-semiconductor MP3 is connected with MN4 source electrode, MN6 grid, MN6 drain, MP4 drain electrode with
MN5 source electrode, MN7 drain are connected；In second transadmittance gain unit the drain electrode of N-type metal-oxide-semiconductor MN1 with
In impedance unit, the drain electrode of p-type metal-oxide-semiconductor MP5 is connected with the source electrode of p-type metal-oxide-semiconductor MP6, N-type
The drain electrode of the drain electrode of metal-oxide-semiconductor MN2 and p-type metal-oxide-semiconductor (MP7) and p-type metal-oxide-semiconductor (MP8)
Source electrode is connected.Switch is clock switch, and quantity is 4, respectively switchs S1, switch S2, switch
S3 and switch S4, is clock switch in the same direction for coupling switch, switch S1, switch S3 and switch S4,
Switch S2 is the clock switch reversely and not overlapped with S1, S3, S4.The quantity of electric capacity is 3,
Being respectively electric capacity C1, electric capacity C2 and electric capacity C3, for matching capacitance, the capacitance of electric capacity C3 is more than electric capacity C1
With the capacitance of electric capacity C2, electric capacity C3 is bulky capacitor.Switch S1 two ends respectively with the first transadmittance gain list
The grid of the p-type metal-oxide-semiconductor MP4 in unit is connected with the grid of p-type metal-oxide-semiconductor MP3, switch S2's
Two ends are connected with drain electrode and the output end vo ut of p-type metal-oxide-semiconductor MP8 respectively, and the two ends of switch S3 are respectively
Drain electrode and the positive pole of electric capacity C1 with p-type metal-oxide-semiconductor MP8 are connected, switch S4 respectively with output end vo ut
Being connected with the positive pole of electric capacity C2, the positive pole of electric capacity C3 is connected with output end vo ut, is connected with ground GND.
It is illustrated in figure 2 the shape of the operation amplifier circuit work process breaker in middle eliminating DC offset voltage
State, when wherein switching off, level is high, and switch Guan Bi level is low.In the T1 time period, switch S1, switch
S3, switch S4 Guan Bi, switch S2 disconnects, and this stage is imbalance sample phase, operational amplifier defeated
Entering voltage is 0, it is believed that the offset voltage caused due to factors such as fabrication errors is the input of amplifier, electric capacity
C3 is bulky capacitor, thus the voltage on electric capacity C2 is also fixing, and the offset voltage of operational amplifier is electric
Hold C1 and electric capacity C2 sampling；In the T2 time period, switch S1, switch S3 and switch S4 disconnect, switch
S2 close, operational amplifier under normal amplification mode, p-type metal-oxide-semiconductor in the first transadmittance gain unit
The grid of MP3 and the grid of p-type metal-oxide-semiconductor MP4 connect respectively operational amplifier differential input end Vin and
Vip, the DC offset voltage being stored on electric capacity C1 and electric capacity C2 defines the negative feedback of DC maladjustment,
Thus reduce the DC maladjustment impact on operational amplifier.The work of T3 time period circuit is identical with the T1 time period,
The work of T4 time period circuit is identical with the T2 time period, and the iteration through multiple cycles can gradually eliminate computing and put
The DC maladjustment of big device.
The preferred embodiment of the present invention described in detail above, it is achieved that a kind of Differential Input Single-end output
Operational amplifier, is sampled misalignment signal by electric capacity, it is possible to effectively solve that the factors such as process deviation cause is straight
Stream imbalance, circuit structure is simple, can be compatible with standard CMOS process, it is easy to application.
Should be appreciated that the ordinary skill of this area just can be made all according to the design of the present invention without creative work
Many modifications and variations.Therefore, all technical staff in the art are under this invention's idea on the basis of prior art
On by the available technical scheme of logical analysis, reasoning, or a limited experiment, all should be by claims
Determined by protection domain.
Claims (6)
1. the operation amplifier circuit eliminating DC offset voltage, it is characterised in that: include the first transadmittance gain list
Unit (1), the second transadmittance gain unit (2), impedance unit (3), switch and electric capacity；Described first transadmittance gain
Unit (1) and described second transadmittance gain unit (2) electrically connect with described impedance unit (3) respectively；
Described first transadmittance gain unit (1) includes 4 p-type metal-oxide-semiconductors, respectively p-type metal-oxide-semiconductor
(MP1), p-type metal-oxide-semiconductor (MP2), p-type metal-oxide-semiconductor (MP3) and p-type metal-oxide-semiconductor (MP4),
Described first transadmittance gain unit (1) is the differential input structure that cascade current source does tail current source formula,
Differential input voltage is converted into electric current, and the drain electrode of described p-type metal-oxide-semiconductor (MP1) connects described p-type MOS
The source electrode of pipe (MP2), the grid of described p-type metal-oxide-semiconductor (MP1) connects bias voltage (Vpb1),
The grid of described p-type metal-oxide-semiconductor (MP2) connects bias voltage (Vpb2), described p-type metal-oxide-semiconductor (MP3)
Source class, the source class of described p-type metal-oxide-semiconductor (MP4) and the drain of described p-type metal-oxide-semiconductor (MP2)
Being connected, the grid of described p-type metal-oxide-semiconductor (MP3) and the grid of described p-type metal-oxide-semiconductor (MP4) divide
Do not meet differential input end (Vin) and (Vip) of amplifier circuit；
Described second transadmittance gain unit (2) includes 3 N-type metal-oxide-semiconductors, respectively N-type metal-oxide-semiconductor
(MN1), N-type metal-oxide-semiconductor (MN2) and N-type metal-oxide-semiconductor (MN3), described second mutual conductance increasing
Benefit unit (2) is the differential pair structure of tail current biasing, the source electrode of described N-type metal-oxide-semiconductor (MN1),
The source electrode of described N-type metal-oxide-semiconductor (MN2) and the drain of described N-type metal-oxide-semiconductor (MN3) are connected on one
Rising, the grid of described N-type metal-oxide-semiconductor (MN3) connects bias voltage (Vnb1)；
Described impedance unit (3) comprises 4 p-type metal-oxide-semiconductors, respectively p-type metal-oxide-semiconductor (MP5),
P-type metal-oxide-semiconductor (MP6), p-type metal-oxide-semiconductor (MP7) and p-type metal-oxide-semiconductor (MP8), and 4
N-type metal-oxide-semiconductor, respectively N-type metal-oxide-semiconductor (MN4), N-type metal-oxide-semiconductor (MN5), N-type
Metal-oxide-semiconductor (MN6) and N-type metal-oxide-semiconductor (MN7), described impedance unit (3) is Single-end output
Telescopic cascode structure, is converted into current signal voltage signal, and produces enough gains, described
The drain of p-type metal-oxide-semiconductor (MP5) connects the source electrode of described p-type metal-oxide-semiconductor (MP6), described p-type
The drain of metal-oxide-semiconductor (MP7) connects the source electrode of described p-type metal-oxide-semiconductor (MP8), described p-type MOS
The pipe grid of (MP5), grid and the described bias voltage (Vpb1) of described p-type metal-oxide-semiconductor (MP7)
Connect, the grid of described p-type metal-oxide-semiconductor (MP6), described p-type metal-oxide-semiconductor (MP8) grid with
Bias voltage (Vpb2) connects, the drain of described p-type metal-oxide-semiconductor (MP6), described N-type MOS
The pipe grid of (MN4), the drain of described N-type metal-oxide-semiconductor (MN4) and described N-type metal-oxide-semiconductor
(MN5) grid is connected together, the source electrode of described N-type metal-oxide-semiconductor (MN4), described N-type MOS
The pipe grid of (MN6), the drain of described N-type metal-oxide-semiconductor (MN6) and described N-type metal-oxide-semiconductor
(MN7) grid is connected together, the source electrode of described N-type metal-oxide-semiconductor (MN5) and described N-type MOS
The drain of pipe (MN7) is connected together.
A kind of operation amplifier circuit eliminating DC offset voltage the most as claimed in claim 1, it is characterised in that
The drain electrode of p-type metal-oxide-semiconductor (MP3) described in described first transadmittance gain unit (1) and described N-type
The source electrode of metal-oxide-semiconductor (MN4), the grid of N-type metal-oxide-semiconductor (MN6), N-type metal-oxide-semiconductor (MN6)
Drain be connected, the source electrode of the drain electrode of p-type metal-oxide-semiconductor (MP4) and N-type metal-oxide-semiconductor (MN5) and N
The drain of type metal-oxide-semiconductor (MN7) is connected.
A kind of operation amplifier circuit eliminating DC offset voltage the most as claimed in claim 1, it is characterised in that
The drain electrode of N-type metal-oxide-semiconductor (MN1) described in described second transadmittance gain unit (2) and described impedance list
The drain electrode of p-type metal-oxide-semiconductor (MP5) described in unit (3) and the source of described p-type metal-oxide-semiconductor (MP6)
The most connected, the drain electrode of described N-type metal-oxide-semiconductor (MN2) and the leakage of described p-type metal-oxide-semiconductor (MP7)
Pole is connected with the source electrode of described p-type metal-oxide-semiconductor (MP8).
A kind of operation amplifier circuit eliminating DC offset voltage the most as claimed in claim 1, it is characterised in that
Described switch is clock switch, and quantity is 4, is respectively switch (S1), switch (S2), switch
(S3) and switch (S4), for coupling switch, described switch (S1), described switch (S3) and described
Switch (S4) is clock switch in the same direction, described switch (S2) be with switch (S1), switch (S3),
The clock switch that switch (S4) reversely and not overlaps.
A kind of operation amplifier circuit eliminating DC offset voltage the most as claimed in claim 4, it is characterised in that
The quantity of described electric capacity is 3, respectively electric capacity (C1), electric capacity (C2) and electric capacity (C3), for coupling electricity
Holding, the capacitance of electric capacity (C3) is more than described electric capacity (C1) and the capacitance of described electric capacity (C2).
A kind of operation amplifier circuit eliminating DC offset voltage the most as claimed in claim 5, it is characterised in that
The two ends of described switch (S1) respectively with described p-type MOS in described first transadmittance gain unit (1)
The grid of pipe (MP4) is connected with the grid of described p-type metal-oxide-semiconductor (MP3), described switch (S2)
Two ends be connected with drain electrode and the outfan (Vout) of described p-type metal-oxide-semiconductor (MP8) respectively, described switch
(S3) two ends are respectively with the drain electrode of described p-type metal-oxide-semiconductor (MP8) and described electric capacity (C1) just
The most connected, described switch (S4) respectively with described outfan (Vout) and the positive pole of described electric capacity (C2)
Being connected, the positive pole of described electric capacity (C3) is connected with described outfan (Vout), is connected with ground (GND).
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| CN101217263A (en) * | 2008-01-17 | 2008-07-09 | 埃派克森微电子有限公司 | A compensatory method and device for DC offset voltage of amplifier |
| CN101976095A (en) * | 2010-11-19 | 2011-02-16 | 长沙景嘉微电子有限公司 | High-precision band-gap reference source circuit based on emitter current compensation |
| CN103066934A (en) * | 2012-12-20 | 2013-04-24 | 西安电子科技大学 | Variable-gain operational amplifier for infrared receiver |
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| CN101217263A (en) * | 2008-01-17 | 2008-07-09 | 埃派克森微电子有限公司 | A compensatory method and device for DC offset voltage of amplifier |
| CN101976095A (en) * | 2010-11-19 | 2011-02-16 | 长沙景嘉微电子有限公司 | High-precision band-gap reference source circuit based on emitter current compensation |
| CN103066934A (en) * | 2012-12-20 | 2013-04-24 | 西安电子科技大学 | Variable-gain operational amplifier for infrared receiver |
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| CN103956981A (en) | 2014-07-30 |
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