CN103956981A - Operational amplifier circuit capable of eliminating direct current offset voltage - Google Patents
Operational amplifier circuit capable of eliminating direct current offset voltage Download PDFInfo
- Publication number
- CN103956981A CN103956981A CN201410137208.8A CN201410137208A CN103956981A CN 103956981 A CN103956981 A CN 103956981A CN 201410137208 A CN201410137208 A CN 201410137208A CN 103956981 A CN103956981 A CN 103956981A
- Authority
- CN
- China
- Prior art keywords
- oxide
- semiconductor
- type metal
- switch
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Amplifiers (AREA)
Abstract
The invention discloses an operational amplifier circuit capable of eliminating a direct current offset voltage. The operational amplifier circuit comprises two transconductance gain units, an impedance unit, four switches and three capacitors, wherein the first transconductance gain unit comprises four P-type MOS (Metal Oxide Semiconductor) tubes; the second transconductance gain unit comprises three N-type MOS tubes; the transconductance gain units adopt differential pair input structures with bias tail current, and the differential input is converted into current; the impedance unit comprises four P-type MOS tubes and four N-type MOS tubes and adopt a single-ended output sleeve type cascode structure, the current is converted into voltage and enough gain is obtained; the capacitors store detuning signals which are caused by factors such as craft deviation, and negative feedback of direct current detuning is realized under an on-off control closed loop. According to a differential input and single-ended output operational amplifier, the direct current detuning problem caused by factors such as the craft deviation is effectively solved by a way that the capacitors sample the detuning signals, the circuit is simple in structure and compatible with a standard CMOS (Complementary Metal-Oxide-Semiconductor Transistor) technology, and the application is easy.
Description
Technical field
The present invention relates to a kind of operation amplifier circuit, relate in particular to a kind of operation amplifier circuit of eliminating DC offset voltage.
Background technology
If amplifier input terminal voltage is 0V, output end voltage should be also 0V, but in fact, when input is 0V, output always has certain voltage, and this voltage is called offset voltage.Consumer electronics market expands in recent years, and the also develop rapidly of ic power field follows properties of product to require more and more higher, the reference voltage as power supply core is required more and more harsher.Be applied to the operational amplifier in band-gap reference circuit, it is upper that its offset voltage is often exaggerated and is embodied in benchmark output, very large on reference precision impact, therefore needs to take measures to eliminate the DC maladjustment of amplifier.
Summary of the invention
Because the defect of prior art the invention provides a kind of operation amplifier circuit of eliminating DC offset voltage, comprise the first transadmittance gain unit, the second transadmittance gain unit, impedance unit, switch and electric capacity;
Described the first transadmittance gain unit (1) comprises 4 P type metal-oxide-semiconductors, be respectively P type metal-oxide-semiconductor (MP1), P type metal-oxide-semiconductor (MP2), P type metal-oxide-semiconductor (MP3) and P type metal-oxide-semiconductor (MP4), described the first transadmittance gain unit (1) is the difference input structure that cascade current source does tail current source formula, difference input voltage is converted into electric current, the drain electrode of described P type metal-oxide-semiconductor (MP1) connects the source electrode of described P type metal-oxide-semiconductor (MP2), the grid of described P type metal-oxide-semiconductor (MP1) connects bias voltage (Vpb1), the grid of described P type metal-oxide-semiconductor (MP2) connects bias voltage (Vpb2), the source class of described P type metal-oxide-semiconductor (MP3), the source class of described P type metal-oxide-semiconductor (MP4) is connected with the leakage level of described P type metal-oxide-semiconductor (MP2), the grid of the grid of described P type metal-oxide-semiconductor (MP3) and described P type metal-oxide-semiconductor (MP4) meets respectively differential input end Vin and the Vip of amplifier circuit,
Described the second transadmittance gain unit (2) comprises 3 N-type metal-oxide-semiconductors, be respectively N-type metal-oxide-semiconductor (MN1), N-type metal-oxide-semiconductor (MN2) and N-type metal-oxide-semiconductor (MN3), described the second transadmittance gain unit is the differential pair structure of tail current biasing, the leakage level of the source electrode of described N-type metal-oxide-semiconductor (MN1), the source electrode of described N-type metal-oxide-semiconductor (MN2) and described N-type metal-oxide-semiconductor (MN3) is connected together, and the grid of described N-type metal-oxide-semiconductor (MN3) connects bias voltage (Vnb1);
Described impedance unit comprises 4 P type metal-oxide-semiconductors, be respectively P type metal-oxide-semiconductor (MP5), P type metal-oxide-semiconductor (MP6), P type metal-oxide-semiconductor (MP7) and P type metal-oxide-semiconductor (MP8), with 4 N-type metal-oxide-semiconductors, be respectively N-type metal-oxide-semiconductor (MN4), N-type metal-oxide-semiconductor (MN5), N-type metal-oxide-semiconductor (MN6) and N-type metal-oxide-semiconductor (MN7), described impedance unit is the Telescopic cascode structure of Single-end output, current signal is converted into voltage signal, and produce enough gains, the leakage level of described P type metal-oxide-semiconductor (MP5) connects the source electrode of described P type metal-oxide-semiconductor (MP6), the leakage level of described P type metal-oxide-semiconductor (MP7) connects the source electrode of described P type metal-oxide-semiconductor (MP7), the grid of described P type metal-oxide-semiconductor (MP5), the grid of described P type metal-oxide-semiconductor (MP7) is connected with described bias voltage (Vpb1), the grid of described P type metal-oxide-semiconductor (MP6), the grid of described P type metal-oxide-semiconductor (MP8) is connected with bias voltage (Vpb2), the leakage level of described P type metal-oxide-semiconductor (MP6), the grid of described N-type metal-oxide-semiconductor (MN4), the grid of the leakage level of described N-type metal-oxide-semiconductor (MN4) and described N-type metal-oxide-semiconductor (MN5) is connected together, the source electrode of described N-type metal-oxide-semiconductor (MN4), the grid of described N-type metal-oxide-semiconductor (MN6), the grid of the leakage level of described N-type metal-oxide-semiconductor (MN6) and described N-type metal-oxide-semiconductor (MN7) is connected together, the leakage level of the source electrode of described N-type metal-oxide-semiconductor (MN5) and described N-type metal-oxide-semiconductor (MN7) is connected together.
The mode of operation of described switch control algorithm amplifier circuit, in sample phase, operation amplifier circuit is sampled to misalignment signal and misalignment signal is stored on electric capacity, in the imbalance elimination stage, operation amplifier circuit forms the negative feedback of DC maladjustment, reduce operation amplifier signal imbalance.
Further, the grid of the drain electrode of P type metal-oxide-semiconductor (MP3) described in described the first transadmittance gain unit and the source electrode of described N-type metal-oxide-semiconductor (MN4), N-type metal-oxide-semiconductor (MN6), the leakage level of N-type metal-oxide-semiconductor (MN6) are connected, and the drain electrode of P type metal-oxide-semiconductor (MP4) is connected with the leakage level of N-type metal-oxide-semiconductor (MN7) with the source electrode of N-type metal-oxide-semiconductor (MN5).
Further, the drain electrode of N-type metal-oxide-semiconductor (MN1) described in described the second transimpedance gain unit and the drain electrode of the metal-oxide-semiconductor of P type described in described impedance unit (MP5) are connected with the source electrode of described P type metal-oxide-semiconductor (MP6), and the drain electrode of described N-type metal-oxide-semiconductor (MN2) is connected with the source electrode of described P type metal-oxide-semiconductor (MP8) with the drain electrode of described P type metal-oxide-semiconductor (MP7).
Further, described switch is clock switch, quantity is 4, be respectively switch (S1), switch (S2), switch (S3) and switch (S4), for coupling switch, described switch (S1), described switch (S3) and described switch (S4) are clock switches in the same way, and described switch (S2) is the clock switch reverse and not overlapping with S1, S3, S4.
Further, the quantity of described electric capacity is 3, is respectively electric capacity (C1), electric capacity (C2) and electric capacity (C3), is matching capacitance, the capacitance of electric capacity (C3) is greater than the capacitance of described electric capacity (C1) and described electric capacity (C2), and electric capacity (C3) is large electric capacity.
Further, the two ends of described switch (S1) are connected with the grid of described P type metal-oxide-semiconductor (MP3) with the grid of the described P type metal-oxide-semiconductor (MP4) in described the first transimpedance gain unit respectively, the two ends of described switch (S2) are connected with output (Vout) with the drain electrode of described P type metal-oxide-semiconductor (MP8) respectively, the two ends of described switch (S3) are connected with the positive pole of described electric capacity (C1) with the drain electrode of described P type metal-oxide-semiconductor (MP8) respectively, described switch (S4) is connected with the positive pole of described electric capacity (C2) with described output (Vout) respectively, the positive pole of described electric capacity (C3) is connected with described output (Vout), be connected with ground (GND).
A kind of operation amplifier circuit of eliminating DC offset voltage provided by the invention, comprise two transadmittance gain unit, an impedance unit, four switches, three electric capacity, wherein the first transadmittance gain unit comprises 4 P type metal-oxide-semiconductors, the second transadmittance gain unit comprises 3 N-type metal-oxide-semiconductors, the differential pair input structure that they adopt tail current to setover, is converted into electric current by difference input; Impedance unit comprises 4 P type metal-oxide-semiconductors and 4 N-type metal-oxide-semiconductors, adopts the Telescopic cascode structure of Single-end output, and electric current is converted into voltage and obtains enough gains; The misalignment signal that capacitance stores causes because of factors such as process deviations is realized the negative feedback of DC maladjustment under switch Control loop, thereby realizes the DC maladjustment that amplifier is low.The present invention has realized a kind of difference input Single-end output operational amplifier, by the electric capacity misalignment signal of sample, can effective solution process deviation etc. the DC maladjustment problem that causes of factor, circuit structure is simple, can and standard CMOS process compatibility, be easy to apply.
Below with reference to accompanying drawing, the technique effect of design of the present invention, concrete structure and generation is described further, to understand fully object of the present invention, feature and effect.
Brief description of the drawings
Fig. 1 is the circuit diagram of a preferred embodiment of the present invention;
Fig. 2 is a preferred embodiment of the present invention state of switch in the course of the work.
Embodiment
Fig. 1 is the circuit diagram of a preferred embodiment of the present invention, i.e. a kind of circuit diagram of the operation amplifier circuit of eliminating DC offset voltage comprises the first transadmittance gain unit 1, the second transadmittance gain unit 2, impedance unit 3, switch and electric capacity, the first transadmittance gain unit comprises 4 P type metal-oxide-semiconductors, be respectively P type metal-oxide-semiconductor MP1, P type metal-oxide-semiconductor MP2, P type metal-oxide-semiconductor MP3 and P type metal-oxide-semiconductor MP4, the first transadmittance gain unit is the difference input structure that cascade current source does tail current source formula, difference input voltage is converted into electric current, the drain electrode of P type metal-oxide-semiconductor MP1 connects the source electrode of P type metal-oxide-semiconductor MP2, the grid of P type metal-oxide-semiconductor MP1 meets bias voltage Vpb1, the grid of P type metal-oxide-semiconductor MP2 meets bias voltage Vpb2, the source class of P type metal-oxide-semiconductor MP3, the source class of P type metal-oxide-semiconductor MP4 is connected with the leakage level of P type metal-oxide-semiconductor MP2, the grid of the grid of P type metal-oxide-semiconductor MP3 and P type metal-oxide-semiconductor MP4 meets respectively differential input end Vin and the Vip of amplifier circuit, the second transadmittance gain unit comprises 3 N-type metal-oxide-semiconductors, be respectively N-type metal-oxide-semiconductor MN1, N-type metal-oxide-semiconductor MN2 and N-type metal-oxide-semiconductor MN3, the second transadmittance gain unit is the differential pair structure of tail current biasing, the leakage level of the source electrode of N-type metal-oxide-semiconductor MN1, the source electrode of N-type metal-oxide-semiconductor MN2 and N-type metal-oxide-semiconductor MN3 is connected together, and the grid of N-type metal-oxide-semiconductor MN3 meets bias voltage Vnb1, impedance unit comprises 4 P type metal-oxide-semiconductors, be respectively P type metal-oxide-semiconductor MP5, P type metal-oxide-semiconductor MP6, P type metal-oxide-semiconductor MP7 and P type metal-oxide-semiconductor MP8, with 4 N-type metal-oxide-semiconductors, be respectively N-type metal-oxide-semiconductor MN4, N-type metal-oxide-semiconductor MN5, N-type metal-oxide-semiconductor (MN6) and N-type metal-oxide-semiconductor (MN7), impedance unit is the Telescopic cascode structure of Single-end output, current signal is converted into voltage signal, and produce enough gains, the leakage level of P type metal-oxide-semiconductor MP5 connects the source electrode of P type metal-oxide-semiconductor MP6, the leakage level of P type metal-oxide-semiconductor MP7 connects the source electrode of P type metal-oxide-semiconductor MP7, the grid of P type metal-oxide-semiconductor MP5, the grid of P type metal-oxide-semiconductor MP7 is connected with bias voltage Vpb1, the grid of P type metal-oxide-semiconductor MP6, the grid of P type metal-oxide-semiconductor MP8 is connected with bias voltage Vpb2, the leakage level of P type metal-oxide-semiconductor MP6, the grid of N-type metal-oxide-semiconductor MN4, the grid of the leakage level of N-type metal-oxide-semiconductor MN4 and N-type metal-oxide-semiconductor MN5 is connected together, the source electrode of N-type metal-oxide-semiconductor (MN4), the grid of N-type metal-oxide-semiconductor MN6, the grid of the leakage level of N-type metal-oxide-semiconductor MN6 and N-type metal-oxide-semiconductor MN7 is connected together, the leakage level of the source electrode of N-type metal-oxide-semiconductor MN5 and N-type metal-oxide-semiconductor MN7 is connected together.The mode of operation of switch control algorithm amplifier circuit, in sample phase, operation amplifier circuit is sampled to misalignment signal and misalignment signal is stored on electric capacity, in the imbalance elimination stage, operation amplifier circuit forms the negative feedback of DC maladjustment, reduce operation amplifier signal imbalance.In the first transadmittance gain unit, the drain electrode of P type metal-oxide-semiconductor MP3 is connected with MN4 source electrode, MN6 grid, MN6 leakage level, and MP4 drain electrode is leaked level with MN5 source electrode, MN7 and is connected; In the second transimpedance gain unit, the drain electrode of N-type metal-oxide-semiconductor MN1 is connected with the source electrode of P type metal-oxide-semiconductor MP6 with the drain electrode of P type metal-oxide-semiconductor MP5 in impedance unit, and the drain electrode of N-type metal-oxide-semiconductor MN2 is connected with the source electrode of P type metal-oxide-semiconductor (MP8) with the drain electrode of P type metal-oxide-semiconductor (MP7).Switch is clock switch, quantity is 4, is respectively switch S 1, switch S 2, switch S 3 and switch S 4, is coupling switch, switch S 1, switch S 3 and switch S 4 are clock switches in the same way, and switch S 2 is clock switches reverse and not overlapping with S1, S3, S4.The quantity of electric capacity is 3, is respectively capacitor C 1, capacitor C 2 and capacitor C 3, is matching capacitance, and the capacitance of capacitor C 3 is greater than the capacitance of capacitor C 1 and capacitor C 2, and capacitor C 3 is large electric capacity.The two ends of switch S 1 are connected with the grid of P type metal-oxide-semiconductor MP3 with the grid of the P type metal-oxide-semiconductor MP4 in the first transimpedance gain unit respectively, the two ends of switch S 2 are connected with output end vo ut with the drain electrode of P type metal-oxide-semiconductor MP8 respectively, the two ends of switch S 3 are connected with the positive pole of capacitor C 1 with the drain electrode of P type metal-oxide-semiconductor MP8 respectively, switch S 4 is connected with the positive pole of capacitor C 2 with output end vo ut respectively, the positive pole of capacitor C 3 is connected with output end vo ut, and GND is connected with ground.
Be illustrated in figure 2 the state of switch in the operation amplifier circuit course of work of eliminating DC offset voltage, when wherein switch disconnects, level is high, and the closed level of switch is low.In the T1 time period, switch S 1, switch S 3, switch S 4 closures, switch S 2 disconnects, this one-phase is imbalance sample phase, the input voltage of operational amplifier is 0, can think that the offset voltage causing due to factors such as fabrication errors is the input of amplifier, and capacitor C 3 is large electric capacity, thereby the voltage in capacitor C 2 is also fixed, the offset voltage of operational amplifier is sampled by capacitor C 1 and capacitor C 2; In the T2 time period, switch S 1, switch S 3 very switch S 4 disconnect, switch S 2 closures, operational amplifier is under normal amplification mode, in the first transadmittance gain unit, the grid of the grid of P type metal-oxide-semiconductor MP3 and P type metal-oxide-semiconductor MP4 meets respectively differential input end Vin and the Vip of operational amplifier, the DC offset voltage being stored in capacitor C 1 and capacitor C 2 has formed the negative feedback of DC maladjustment, thereby reduces the impact of DC maladjustment on operational amplifier.T3 time period circuit working is identical with the T1 time period, and T4 time period circuit working is identical with the T2 time period, can eliminate gradually the DC maladjustment of operational amplifier through the iteration in multiple cycles.
More than describe preferred embodiment of the present invention in detail, realize a kind of operational amplifier of difference input Single-end output, by the electric capacity misalignment signal of sampling, can effective solution process deviation etc. the DC maladjustment problem that causes of factor, circuit structure is simple, energy and standard CMOS process compatibility, be easy to application.
The ordinary skill that should be appreciated that this area just can design according to the present invention be made many modifications and variations without creative work.Therefore, all technical staff in the art, all should be in by the determined protection range of claims under this invention's idea on the basis of existing technology by the available technical scheme of logical analysis, reasoning, or a limited experiment.
Claims (6)
1. an operation amplifier circuit of eliminating DC offset voltage, is characterized in that: comprise the first transadmittance gain unit (1), the second transadmittance gain unit (2), impedance unit (3), switch and electric capacity; Described the first transadmittance gain unit (1) and described the second transadmittance gain unit (2) are electrically connected with described impedance unit (3) respectively;
Described the first transadmittance gain unit (1) comprises 4 P type metal-oxide-semiconductors, be respectively P type metal-oxide-semiconductor (MP1), P type metal-oxide-semiconductor (MP2), P type metal-oxide-semiconductor (MP3) and P type metal-oxide-semiconductor (MP4), described the first transadmittance gain unit (1) is the difference input structure that cascade current source does tail current source formula, difference input voltage is converted into electric current, the drain electrode of described P type metal-oxide-semiconductor (MP1) connects the source electrode of described P type metal-oxide-semiconductor (MP2), the grid of described P type metal-oxide-semiconductor (MP1) connects bias voltage (Vpb1), the grid of described P type metal-oxide-semiconductor (MP2) connects bias voltage (Vpb2), the source class of described P type metal-oxide-semiconductor (MP3), the source class of described P type metal-oxide-semiconductor (MP4) is connected with the leakage level of described P type metal-oxide-semiconductor (MP2), the grid of the grid of described P type metal-oxide-semiconductor (MP3) and described P type metal-oxide-semiconductor (MP4) connects respectively the differential input end (Vin) of amplifier circuit and (Vip),
Described the second transadmittance gain unit (2) comprises 3 N-type metal-oxide-semiconductors, be respectively N-type metal-oxide-semiconductor (MN1), N-type metal-oxide-semiconductor (MN2) and N-type metal-oxide-semiconductor (MN3), described the second transadmittance gain unit (2) is the differential pair structure of tail current biasing, the leakage level of the source electrode of described N-type metal-oxide-semiconductor (MN1), the source electrode of described N-type metal-oxide-semiconductor (MN2) and described N-type metal-oxide-semiconductor (MN3) is connected together, and the grid of described N-type metal-oxide-semiconductor (MN3) connects bias voltage (Vnb1);
Described impedance unit (3) comprises 4 P type metal-oxide-semiconductors, be respectively P type metal-oxide-semiconductor (MP5), P type metal-oxide-semiconductor (MP6), P type metal-oxide-semiconductor (MP7) and P type metal-oxide-semiconductor (MP8), with 4 N-type metal-oxide-semiconductors, be respectively N-type metal-oxide-semiconductor (MN4), N-type metal-oxide-semiconductor (MN5), N-type metal-oxide-semiconductor (MN6) and N-type metal-oxide-semiconductor (MN7), described impedance unit (3) is the Telescopic cascode structure of Single-end output, current signal is converted into voltage signal, and produce enough gains, the leakage level of described P type metal-oxide-semiconductor (MP5) connects the source electrode of described P type metal-oxide-semiconductor (MP6), the leakage level of described P type metal-oxide-semiconductor (MP7) connects the source electrode of described P type metal-oxide-semiconductor (MP7), the grid of described P type metal-oxide-semiconductor (MP5), the grid of described P type metal-oxide-semiconductor (MP7) is connected with described bias voltage (Vpb1), the grid of described P type metal-oxide-semiconductor (MP6), the grid of described P type metal-oxide-semiconductor (MP8) is connected with bias voltage (Vpb2), the leakage level of described P type metal-oxide-semiconductor (MP6), the grid of described N-type metal-oxide-semiconductor (MN4), the grid of the leakage level of described N-type metal-oxide-semiconductor (MN4) and described N-type metal-oxide-semiconductor (MN5) is connected together, the source electrode of described N-type metal-oxide-semiconductor (MN4), the grid of described N-type metal-oxide-semiconductor (MN6), the grid of the leakage level of described N-type metal-oxide-semiconductor (MN6) and described N-type metal-oxide-semiconductor (MN7) is connected together, the leakage level of the source electrode of described N-type metal-oxide-semiconductor (MN5) and described N-type metal-oxide-semiconductor (MN7) is connected together.
2. a kind of operation amplifier circuit of eliminating DC offset voltage as claimed in claim 1, it is characterized in that, described in described the first transadmittance gain unit (1), the grid of the drain electrode of P type metal-oxide-semiconductor (MP3) and the source electrode of described N-type metal-oxide-semiconductor (MN4), N-type metal-oxide-semiconductor (MN6), the leakage level of N-type metal-oxide-semiconductor (MN6) are connected, and the drain electrode of P type metal-oxide-semiconductor (MP4) is connected with the leakage level of N-type metal-oxide-semiconductor (MN7) with the source electrode of N-type metal-oxide-semiconductor (MN5).
3. a kind of operation amplifier circuit of eliminating DC offset voltage as claimed in claim 1, it is characterized in that, the drain electrode of N-type metal-oxide-semiconductor (MN1) described in described the second transimpedance gain unit (2) and the drain electrode of P type metal-oxide-semiconductor (MP5) described in described impedance unit (3) are connected with the source electrode of described P type metal-oxide-semiconductor (MP6), and the drain electrode of described N-type metal-oxide-semiconductor (MN2) is connected with the source electrode of described P type metal-oxide-semiconductor (MP8) with the drain electrode of described P type metal-oxide-semiconductor (MP7).
4. a kind of operation amplifier circuit of eliminating DC offset voltage as claimed in claim 1, it is characterized in that, described switch is clock switch, quantity is 4, be respectively switch (S1), switch (S2), switch (S3) and switch (S4), for coupling switch, described switch (S1), described switch (S3) and described switch (S4) are clock switches in the same way, and described switch (S2) is the clock switch reverse and not overlapping with S1, S3, S4.
5. a kind of operation amplifier circuit of eliminating DC offset voltage as claimed in claim 4, it is characterized in that, the quantity of described electric capacity is 3, be respectively electric capacity (C1), electric capacity (C2) and electric capacity (C3), for matching capacitance, the capacitance of electric capacity (C3) is greater than the capacitance of described electric capacity (C1) and described electric capacity (C2).
6. a kind of operation amplifier circuit of eliminating DC offset voltage as claimed in claim 5, it is characterized in that, the two ends of described switch (S1) are connected with the grid of described P type metal-oxide-semiconductor (MP3) with the grid of the described P type metal-oxide-semiconductor (MP4) in described the first transimpedance gain unit (1) respectively, the two ends of described switch (S2) are connected with output (Vout) with the drain electrode of described P type metal-oxide-semiconductor (MP8) respectively, the two ends of described switch (S3) are connected with the positive pole of described electric capacity (C1) with the drain electrode of described P type metal-oxide-semiconductor (MP8) respectively, described switch (S4) is connected with the positive pole of described electric capacity (C2) with described output (Vout) respectively, the positive pole of described electric capacity (C3) is connected with described output (Vout), be connected with ground (GND).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410137208.8A CN103956981B (en) | 2014-04-04 | 2014-04-04 | A kind of operation amplifier circuit eliminating DC offset voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410137208.8A CN103956981B (en) | 2014-04-04 | 2014-04-04 | A kind of operation amplifier circuit eliminating DC offset voltage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103956981A true CN103956981A (en) | 2014-07-30 |
| CN103956981B CN103956981B (en) | 2016-09-14 |
Family
ID=51334223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410137208.8A Active CN103956981B (en) | 2014-04-04 | 2014-04-04 | A kind of operation amplifier circuit eliminating DC offset voltage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103956981B (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104200221A (en) * | 2014-08-26 | 2014-12-10 | 上海思立微电子科技有限公司 | Fingerprint identification sensor |
| CN105429603A (en) * | 2014-09-12 | 2016-03-23 | Ess技术有限公司 | Two differential amplifier configuration |
| CN105680810A (en) * | 2015-12-31 | 2016-06-15 | 杭州士兰微电子股份有限公司 | Amplification circuit, signal amplification method and sensing signal processing device |
| CN105897185A (en) * | 2016-04-28 | 2016-08-24 | 西安航天民芯科技有限公司 | Circuit for low-offset operational amplifier |
| CN106483366A (en) * | 2015-12-31 | 2017-03-08 | 无锡华润矽科微电子有限公司 | A kind of current detection circuit eliminating offset voltage |
| CN107623498A (en) * | 2017-10-18 | 2018-01-23 | 上海芯北电子科技有限公司 | A kind of operational amplifier calibration method and circuit |
| CN110492852A (en) * | 2019-09-17 | 2019-11-22 | 江苏润石科技有限公司 | The differential input structure of operational amplifier performance can be improved |
| CN111610424A (en) * | 2019-02-26 | 2020-09-01 | 圣邦微电子（北京）股份有限公司 | Test circuit, test method and test device for operational amplifier |
| CN112583359A (en) * | 2020-12-16 | 2021-03-30 | 无锡市晶源微电子有限公司 | Self-adaptive compensation device for transconductance amplifier offset and transconductance amplifier |
| CN112731997A (en) * | 2020-12-05 | 2021-04-30 | 西安翔腾微电子科技有限公司 | High-precision automatic zero-setting belt reference circuit and method |
| CN113341212A (en) * | 2021-06-05 | 2021-09-03 | 晶通微电子(南京)有限公司 | Differential voltage detection circuit with wide voltage input range |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101217263B (en) * | 2008-01-17 | 2010-12-15 | 埃派克森微电子有限公司 | A compensatory method and device for DC offset voltage of amplifier |
| CN101976095B (en) * | 2010-11-19 | 2012-06-06 | 长沙景嘉微电子有限公司 | High-precision band-gap reference source circuit based on emitter current compensation |
| CN103066934B (en) * | 2012-12-20 | 2016-02-10 | 西安电子科技大学 | For the variable gain operational amplifier in infrared remote receiver |
-
2014
- 2014-04-04 CN CN201410137208.8A patent/CN103956981B/en active Active
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104200221B (en) * | 2014-08-26 | 2017-11-24 | 上海思立微电子科技有限公司 | A kind of fingerprint Identification sensor |
| CN104200221A (en) * | 2014-08-26 | 2014-12-10 | 上海思立微电子科技有限公司 | Fingerprint identification sensor |
| CN105429603A (en) * | 2014-09-12 | 2016-03-23 | Ess技术有限公司 | Two differential amplifier configuration |
| CN105680810B (en) * | 2015-12-31 | 2018-09-04 | 杭州士兰微电子股份有限公司 | Amplifying circuit, method for amplifying signal and transducing signal processing unit |
| CN106483366B (en) * | 2015-12-31 | 2018-06-29 | 无锡华润矽科微电子有限公司 | A kind of current detection circuit for eliminating offset voltage |
| CN105680810A (en) * | 2015-12-31 | 2016-06-15 | 杭州士兰微电子股份有限公司 | Amplification circuit, signal amplification method and sensing signal processing device |
| CN106483366A (en) * | 2015-12-31 | 2017-03-08 | 无锡华润矽科微电子有限公司 | A kind of current detection circuit eliminating offset voltage |
| CN105897185A (en) * | 2016-04-28 | 2016-08-24 | 西安航天民芯科技有限公司 | Circuit for low-offset operational amplifier |
| CN105897185B (en) * | 2016-04-28 | 2019-02-12 | 西安航天民芯科技有限公司 | A kind of circuit applied to low imbalance operational amplifier |
| CN107623498A (en) * | 2017-10-18 | 2018-01-23 | 上海芯北电子科技有限公司 | A kind of operational amplifier calibration method and circuit |
| CN107623498B (en) * | 2017-10-18 | 2020-10-09 | 上海芯北电子科技有限公司 | Operational amplifier calibration method and circuit |
| CN111610424B (en) * | 2019-02-26 | 2022-08-16 | 圣邦微电子（北京）股份有限公司 | Test circuit, test method and test device for operational amplifier |
| CN111610424A (en) * | 2019-02-26 | 2020-09-01 | 圣邦微电子（北京）股份有限公司 | Test circuit, test method and test device for operational amplifier |
| CN110492852A (en) * | 2019-09-17 | 2019-11-22 | 江苏润石科技有限公司 | The differential input structure of operational amplifier performance can be improved |
| CN110492852B (en) * | 2019-09-17 | 2024-05-17 | 江苏润石科技有限公司 | Differential input structure capable of improving operational amplifier performance |
| CN112731997A (en) * | 2020-12-05 | 2021-04-30 | 西安翔腾微电子科技有限公司 | High-precision automatic zero-setting belt reference circuit and method |
| CN112583359A (en) * | 2020-12-16 | 2021-03-30 | 无锡市晶源微电子有限公司 | Self-adaptive compensation device for transconductance amplifier offset and transconductance amplifier |
| CN113341212A (en) * | 2021-06-05 | 2021-09-03 | 晶通微电子(南京)有限公司 | Differential voltage detection circuit with wide voltage input range |
| CN113341212B (en) * | 2021-06-05 | 2022-08-02 | 晶通微电子(南京)有限公司 | Differential voltage detection circuit with wide voltage input range |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103956981B (en) | 2016-09-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103956981A (en) | Operational amplifier circuit capable of eliminating direct current offset voltage | |
| CN103219961B (en) | Bandwidth-adjustable operational amplifier circuit | |
| CN104407662B (en) | A kind of underloading transient state strengthens the low pressure difference linear voltage regulator of circuit and this circuit integrated | |
| CN101951236B (en) | Digital variable gain amplifier | |
| CN104656733B (en) | Self-adaptation exports the low pressure difference linear voltage regulator of ultra low quiescent current | |
| CN103838290B (en) | Ldo circuit | |
| CN105242734A (en) | High-power LDO circuit without externally setting capacitor | |
| CN103346765A (en) | Gate-source following sampling switch | |
| CN103760943B (en) | A kind of slew rate enhancing circuit being applied to LDO | |
| CN104143929A (en) | Ultra-low voltage self-powered rectifier circuit used for obtaining RF energy | |
| CN105958948A (en) | Low-power-consumption wide-range operational transconductance amplifier | |
| CN201846315U (en) | Digital variable gain amplifier | |
| CN105529994B (en) | Trans-impedance amplifier with gain bootstrap function | |
| CN203775151U (en) | Operational amplifier circuit for eliminating direct-current offset voltages | |
| CN104253590A (en) | Fully differential operational amplifier module circuit, analog-to-digital converter and readout circuit | |
| CN104702268B (en) | The circuit that voltage buffer circuit and driving load with it switch with sequential | |
| CN102545805B (en) | Two-stage operational amplifier | |
| CN104579260A (en) | Hysteresis comparator for radio frequency identification | |
| CN105680833A (en) | Constant transconductance rail-to-rail voltage comparator | |
| CN106026928A (en) | Low-voltage single-balancing current multiplexing passive mixer | |
| CN103051289B (en) | Preliminary amplifier with low clock crosstalk, dynamic comparator and circuit | |
| CN105932971A (en) | Three-level operation amplifier driving wide-range capacitive loads | |
| CN106059516B (en) | Track to track operational amplification circuit and ADC converter, dcdc converter and power amplifier | |
| CN105162468B (en) | A kind of high speed benchmark buffer circuit with voltage bootstrapping | |
| CN104300949A (en) | Low-voltage resetting circuit for radio frequency chip of internet of things |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |