CN105680833A - Constant transconductance rail-to-rail voltage comparator - Google Patents

Abstract

The invention discloses a constant transconductance rail-to-rail voltage comparator, comprising a biasing circuit, a dual differential input circuit, an active load and an output buffer circuit which are electrically connected in sequence, wherein the biasing circuit is used for providing biasing current; the dual differential input circuit is connected with the active load, and used for achieving rail-to-rail in the range of an input common-mode voltage and constant transconductance in the whole common-mode input range; the output buffer circuit outputs a comparison signal via using two stages of inverter circuits; and the dual differential input circuit comprises NMOS differential input pairs, PMOS differential input pairs, a current source corresponding to the NMOS differential input pairs, and a current source corresponding to the PMOS differential input pairs, wherein the NMOS differential input pairs are connected with the PMOS differential input pairs in parallel.

Description

A kind of constant transconductance track to track voltage comparator

Technical field

The present invention relates to electronic technology field, in particular to a kind of constant transconductance track to track voltage comparator.

Background technology

It is the one in unicircuit that comparer (also can be called voltage comparator). Voltage comparator compares the size of two input voltages, and judges wherein which voltage height. Level according to output voltage is big to judge which input voltage.

But, with general comparer at present, when relatively difference input voltage, can the scope of common mode input (inputcommonmodevoltage) of identification not track to track (rail-to-rail), that is, its can the scope of common mode input of identification cannot from ground terminal GND to operating voltage VDD. As common mode input is partial to ground terminal GND, will with the comparer with PMOS Differential Input pair; On the contrary, as common mode input is partial to operating voltage VDD, will with have nmos differential input to comparer. And general track to track voltage comparator does not have constant transconductance characteristic, wireless charging control chip cannot be met to the particular requirement of common-mode input range and mutual conductance.

Summary of the invention

Therefore, for above-mentioned problem, the present invention proposes a kind of constant transconductance track to track voltage comparator, this voltage comparator input stage adopt nmos differential input to PMOS Differential Input to parallel-connection structure, can compare to voltage of supply VDD full voltage range at GND, achieve maximumization of common mode input voltage scope, reach track to track. And the present invention is by appropriate design transistor (NMOS and PMOS) size, the mutual conductance in realizing circuit common-mode input range three regions (only nmos differential input to conducting, only PMOS Differential Input to conducting and NMOS with PMOS Differential Input to pipe conducting simultaneously) is the same big, namely maintains mutual conductance in whole common-mode input range constant.

In order to solve the problems of the technologies described above, the technical solution adopted in the present invention is as follows:

A kind of constant transconductance track to track voltage comparator, comprises biasing circuit, double input circuit, active load and output buffer; Described biasing circuit, double input circuit, active load and output buffer are electrically connected in turn;Described biasing circuit is for providing bias current; Described double input circuit is connected with active load, for realize within the scope of common mode input, reaching track to track and in whole common-mode input range mutual conductance constant; Described output buffer exports by adopting two-stage phase inverter circuit realiration to compare signal; Wherein, described double input circuit comprise nmos differential input to, PMOS Differential Input to, nmos differential input to the current source of correspondence and PMOS Differential Input to the current source of correspondence, nmos differential input to PMOS Differential Input to being connected in parallel. In foregoing description, Differential Input is as signal using the difference of two input terminuss, this transistor corresponding to two input terminuss is exactly difference pair, Differential Input adopts one to the same transistor of parameter characteristic as input terminus to general, thus have nmos differential (input) to or PMOS difference (input).

Described biasing circuit comprises bias current sources Ibs, NMOS tube MN1, NMOS tube MN2 and PMOS MP1; The drain electrode of described NMOS tube MN1 meets bias current sources Ibs; The drain electrode of described NMOS tube MN1 and grid are even; The source level ground connection of described NMOS tube MN1; The grid of described NMOS tube MN1 is connected with the grid of NMOS tube MN2; The grid of described NMOS tube MN2 is connected with double input circuit; The source level ground connection of described NMOS tube MN2; The drain electrode of described NMOS tube MN2 is connected with the drain electrode of described PMOS MP1; The source electrode of described PMOS MP1 meets voltage of supply VDD; The drain and gate of described PMOS MP1 is connected;

Described double input circuit comprises voltage signal electrode input end Vinp, voltage signal negative input Vinn, PMOS MP2, PMOS MP6, PMOS MP7, PMOS MP12, NMOS tube MN6, NMOS tube MN7, NMOS tube MN12, NMOS tube MN3, the source level of described PMOS MP2 meets voltage of supply VDD, and the leakage level of described PMOS MP2 is connected with the source level of the source level of described PMOS MP7, described PMOS MP12 and the source level of described NMOS tube MN6, the grid of described PMOS MP2 is connected with grid and the described active load of described PMOS MP1, the grid of described PMOS MP6 is connected with grid and the described voltage signal negative input Vinn of described NMOS tube MN6, the drain electrode of described PMOS MP6 is connected with described active load, the source level of described PMOS MP6 is connected with the source level of described PMOS MP12, the described grid of MOS pipe MP7 is connected with the grid of described NMOS tube MN7 and described voltage signal electrode input end Vinp, the drain electrode of described PMOS MP7 is connected with described active load, the source level of described PMOS MP7 is connected with the source level of described PMOS MP12, the grid level of described PMOS MP12 is connected with drain electrode, the grid level of described PMOS MP12 is connected with the grid level of described NMOS tube MN12, the leakage level of described PMOS MP12 is connected with the leakage level of described NMOS tube MN12, the grid level of described NMOS tube MN12 is connected with drain electrode, the source level of described NMOS tube MN12 and the source level of described NMOS tube MN6, the source level of described NMOS tube MN7 and the leakage level of described NMOS tube MN3 connect, the grid level of described NMOS tube MN6 meets described voltage signal negative input Vinn, the leakage level of described NMOS tube MN6 is connected with active load, the grid level of described NMOS tube MN7 meets described voltage signal electrode input end Vinp, the leakage level of described NMOS tube MN7 is connected with active load, the grid of described NMOS tube MN3 is connected with the grid of described NMOS tube MN2, the source level ground connection of described NMOS tube MN3.

Described active load comprises PMOS MP3, PMOS MP4, PMOS MP8, PMOS MP9, NMOS tube MN4, NMOS tube MN5, NMOS tube MN8, NMOS tube MN9, biased voltage Vbs1 and biased voltage Vbs2, the source electrode of described PMOS MP3 meets voltage of supply VDD, the grid of described PMOS MP3 and the grid of PMOS MP2, the grid of PMOS MP4 and output buffer connect, the drain electrode of described PMOS MP3 is connected with the leakage level of described NMOS tube MN6 and the source electrode of described PMOS MP8, the grid of described PMOS MP8 connects one end of described biased voltage Vbs1, the other end ground connection of described biased voltage Vbs1, the leakage level of described PMOS MP8 is connected with the leakage level of NMOS tube MN8 and output buffer, the grid of described NMOS tube MN8 connects one end of described biased voltage Vbs2, the other end ground connection of described biased voltage Vbs2, the source electrode of described NMOS tube MN8 is connected with the leakage level of described PMOS MP6 and the leakage level of described NMOS tube MN4, the source ground of described NMOS tube MN4, the grid of described NMOS tube MN4 is connected with the grid of described NMOS tube MN5 and the leakage level of described NMOS tube MN9, the source ground of described NMOS tube MN5, the leakage level of described NMOS tube MN5 is connected with the source electrode of the leakage level of described PMOS MP7 and described NMOS tube MN9, the grid of described NMOS tube MN9 is connected with the grid level of described NMOS tube MN8 and one end of described biased voltage Vbs2, the described leakage level of NMOS tube MN9 of stating is connected with the leakage level of the grid of described NMOS tube MN5 and described PMOS MP9, the grid of described PMOS MP9 is connected with the grid of described PMOS MP8 and one end of described biased voltage Vbs1, the source electrode of described PMOS MP9 is connected with the leakage level of described NMOS tube MN7 and the leakage level of PMOS MP4, the grid of described PMOS MP4 and the grid of described NMOS tube MN3, the grid of described PMOS MP2 and described output buffer connect, the source electrode of described PMOS MP4 meets voltage of supply VDD.

Described output buffer comprises PMOS MP5, PMOS MP10, PMOS MP11, NMOS tube MN10 and NMOS tube MN11, the source electrode of described PMOS MP5 meets voltage of supply VDD, the grid of described PMOS MP5 is connected with the grid of described PMOS MP2, the leakage level of described PMOS MP5 is connected with the source electrode of described PMOS MP10, the grid of described PMOS MP10 and the leakage level of described PMOS MP8, the leakage level of described NMOS tube MN8 and the grid of described NMOS tube MN10 connect, the source ground of described NMOS tube MN10, the leakage level of described NMOS tube MN10 and the leakage level of described PMOS MP10, the grid of described PMOS MP1 and the grid of described NMOS tube MN11 connect, the source electrode of described PMOS MP11 meets voltage of supply VDD, the leakage level of described PMOS MP11 is connected with the leakage level of described NMOS tube MN11 and output end vo ut, the source ground of described NMOS tube MN11.

The size of described NMOS tube MN3 is N (N=4～10) times of described NMOS tube MN1 size, the size of described NMOS tube MN1 is equal with the size of described NMOS tube MN2, the size of described PMOS MP2 is N (N=4～10) times of described PMOS MP1 size, the size of described PMOS MP6 is equal with the size of described PMOS MP7, and the size of described NMOS tube MN6 is equal with the size of described NMOS tube MN7.

The present invention adopts such scheme, compared with prior art, has following useful effect:

1, the present invention input stage adopt nmos differential to PMOS differential pair parallel-connection structure, it is possible to compare to voltage of supply VDD full voltage range at GND, it is achieved that maximumization of common mode input voltage scope, reaches track to track;

2, the present invention is by appropriate design transistor (NMOS and PMOS) size, the mutual conductance in realizing circuit common-mode input range three regions (only nmos differential input to conducting, only PMOS Differential Input to conducting and NMOS with PMOS Differential Input to pipe conducting simultaneously) is the same big, namely maintains mutual conductance in whole common-mode input range constant;

3, the technical solution adopted in the present invention is simple, with low cost, is easy to large-scale application, has good practicality.

Accompanying drawing explanation

Fig. 1 is a kind of constant transconductance track to track voltage comparator theory structure schematic diagram of the present invention.

Embodiment

Now the present invention is further described with embodiment by reference to the accompanying drawings.

See Fig. 1, a kind of constant transconductance track to track voltage comparator of the present invention, comprises biasing circuit 100, double input circuit 200, active load 300 and output buffer 400; Described biasing circuit 100 is electrically connected successively with double input circuit 200, active load 300 and output buffer 400. Wherein, biasing circuit is for providing bias current; Double input circuit is connected with active load, for realize within the scope of common mode input, reaching track to track and in whole common-mode input range mutual conductance constant; Output buffer, compares signal by adopting two-stage phase inverter circuit realiration and exports.

As a specific embodiment, see Fig. 1, biasing circuit comprises bias current sources Ibs, NMOS tube MN1, NMOS tube MN2 and PMOS MP1; The drain electrode of NMOS tube MN1 meets bias current sources Ibs; The drain and gate of NMOS tube MN1 is connected; The source level ground connection of NMOS tube MN1; The grid of NMOS tube MN1 is connected with the grid of NMOS tube MN2; The grid of NMOS tube MN2 is connected with double input circuit; The source level ground connection of NMOS tube MN2; The drain electrode of NMOS tube MN2 is connected with the drain electrode of PMOS MP1; The source electrode of PMOS MP1 meets voltage of supply VDD; The drain and gate of PMOS MP1 is connected.

Double input circuit comprises voltage signal electrode input end Vinp, voltage signal negative input Vinn, PMOS MP2, PMOS MP6, PMOS MP7, PMOS MP12, NMOS tube MN6, NMOS tube MN7, NMOS tube MN12, NMOS tube MN3, the source level of PMOS MP2 meets voltage of supply VDD, and the leakage level of PMOS MP2 is connected with the source level of the source level of PMOS MP7, PMOS MP12 and the source level of NMOS tube MN6, the grid of PMOS MP2 is connected with the grid of PMOS MP1 and active load, the grid of PMOS MP6 is connected with the grid of NMOS tube MN6 and voltage signal negative input Vinn, the drain electrode of PMOS MP6 is connected with active load, the source level of PMOS MP6 is connected with the source level of PMOS MP12, the grid of MOS pipe MP7 is connected with the grid of NMOS tube MN7 and voltage signal electrode input end Vinp, the drain electrode of PMOS MP7 is connected with active load, the source level of PMOS MP7 is connected with the source level of PMOS MP12, the grid level of PMOS MP12 is connected with drain electrode, the grid level of PMOS MP12 is connected with the grid level of NMOS tube MN12, the leakage level of PMOS MP12 is connected with the leakage level of NMOS tube MN12, the grid level of NMOS tube MN12 is connected with drain electrode, the source level of NMOS tube MN12 and the source level of NMOS tube MN6, the source level of NMOS tube MN7 and the leakage level of NMOS tube MN3 connect, the grid level of NMOS tube MN6 meets voltage signal negative input Vinn, the leakage level of NMOS tube MN6 is connected with active load, the grid level of NMOS tube MN7 meets voltage signal electrode input end Vinp, the leakage level of NMOS tube MN7 is connected with active load, the grid of NMOS tube MN3 is connected with the grid of NMOS tube MN2, the source level ground connection of NMOS tube MN3.

Active load comprises PMOS MP3, PMOS MP4, PMOS MP8, PMOS MP9, NMOS tube MN4, NMOS tube MN5, NMOS tube MN8, NMOS tube MN9, biased voltage Vbs1 and biased voltage Vbs2, the source electrode of PMOS MP3 meets voltage of supply VDD, the grid of PMOS MP3 and the grid of PMOS MP2, the grid of PMOS MP4 and output buffer connect, the drain electrode of PMOS MP3 is connected with the leakage level of NMOS tube MN6 and the source electrode of PMOS MP8, the grid of PMOS MP8 connects one end of biased voltage Vbs1, the other end ground connection of biased voltage Vbs1, the leakage level of PMOS MP8 is connected with the leakage level of NMOS tube MN8 and output buffer, the grid of NMOS tube MN8 connects one end of biased voltage Vbs2, the other end ground connection of biased voltage Vbs2, the source electrode of NMOS tube MN8 is connected with the leakage level of PMOS MP6 and the leakage level of NMOS tube MN4, the source ground of NMOS tube MN4, the grid of NMOS tube MN4 is connected with the leakage level of the grid of NMOS tube MN5 and NMOS tube MN9, the source ground of NMOS tube MN5, the leakage level of NMOS tube MN5 is connected with the source electrode of the leakage level of PMOS MP7 and NMOS tube MN9, the grid of NMOS tube MN9 is connected with the grid level of NMOS tube MN8 and one end of biased voltage Vbs2, state the leakage level of NMOS tube MN9 to be connected with the leakage level of the grid of NMOS tube MN5 and PMOS MP9, the grid of PMOS MP9 is connected with one end of the grid of PMOS MP8 and biased voltage Vbs1, the source electrode of PMOS MP9 is connected with the leakage level of NMOS tube MN7 and the leakage level of PMOS MP4, the grid of PMOS MP4 and the grid of NMOS tube MN3, the grid of PMOS MP2 and output buffer connect, the source electrode of PMOS MP4 meets voltage of supply VDD.

Output buffer comprises PMOS MP5, PMOS MP10, PMOS MP11, NMOS tube MN10 and NMOS tube MN11, the source electrode of PMOS MP5 meets voltage of supply VDD, the grid of PMOS MP5 is connected with the grid of PMOS MP2, the leakage level of PMOS MP5 is connected with the source electrode of PMOS MP10, the grid of PMOS MP10 and the leakage level of PMOS MP8, the leakage level of NMOS tube MN8 and the grid of NMOS tube MN10 connect, the source ground of NMOS tube MN10, the leakage level of NMOS tube MN10 and the leakage level of PMOS MP10, the grid of PMOS MP1 and the grid of NMOS tube MN11 connect, the source electrode of PMOS MP11 meets voltage of supply VDD, the leakage level of PMOS MP11 is connected with the leakage level of NMOS tube MN11 and output end vo ut, the source ground of NMOS tube MN11.

In order to achieve maximumization of common mode input voltage scope, reach track to track, the input stage of the present invention adopts nmos differential input to (NMOS tube MN6 and NMOS tube MN7) and PMOS Differential Input to (PMOS MP6 and PMOS MP7) parallel-connection structure, can compare in full voltage range, achieve maximumization of common mode input voltage scope, it be described as follows:

(1) when common mode input is lower, namely when common mode voltage Vin is less than Vthn (wherein Vthn is the threshold voltage of NMOS), Vfg (voltage difference between node f and g) is relatively low, also not enough so that MN12 and MP12 conducting simultaneously, at this moment only PMOS Differential Input to work, assume Vinn < Vinp, then MP6 conducting, MP7 ends, so, it is high level by the voltage signal of MN8 and MN4 point of contact a, MN9 and MN5 point of contact b is lower level, and then be high level by MP8 and MN8 point of contact c, finally, the output buffer that voltage signal connects by adopting two-stage phase inverter, obtaining output voltage Vout is high level,Assume Vinn > Vinp, then MP6 cut-off, MP7 conducting, so, being lower level by the voltage signal of MN8 and MN4 point of contact a, MN9 and MN5 point of contact is high level, and then be lower level by MP8 and MN8 point of contact c, finally, the output buffer that voltage signal connects by adopting two-stage phase inverter, obtaining output voltage Vout is lower level.

(2) when common mode input is higher, namely when Vin is greater than VDD-Vthp (wherein Vthp is the threshold voltage of input PMOS) and is less than VDD, Vfg (voltage difference between node f and g) is relatively low, at this moment only nmos differential inputs work, assume Vinn<Vinp, then MN6 cut-off, MN7 conducting, so, it is high level by MP3 and MP8 point of contact d, MP4 and MP9 point of contact e is lower level, and then be high level by MP8 and MN8 point of contact c, finally, the output buffer that voltage signal connects by adopting two-stage phase inverter, obtaining output voltage Vout is high level, assume Vinn>Vinp, then MN6 conducting, MN7 ends, it is so lower level by MP3 and MP8 point of contact d, MP4 and MP9 point of contact e is high level, and then is lower level by MP8 and MN8 point of contact c, finally, the output buffer that voltage signal connects by adopting two-stage phase inverter, obtaining output voltage Vout is lower level.

(3) when common mode input is when middle scope, namely when Vin is between Vthn and VDD-Vthp, Vfg (voltage difference between node f and g) is higher, higher than MP12 thresholding Vthp and MN12 thresholding Vthp sum, make MN12 and MP12 conducting simultaneously, now nmos differential input to PMOS Differential Input to while conducting, assume Vinn<Vinp, then MN6 cut-off, MN7 conducting, MP6 conducting, MP7 ends, due to nmos differential input to PMOS Differential Input to being connected in parallel, therefore, the output voltage Vout finally obtained is high level; Assume Vinn>Vinp, then MN6 conducting, MN7 end, MP6 conducting, MP7 end, due to nmos differential input to PMOS Differential Input to being connected in parallel, therefore, the output voltage Vout finally obtained is lower level;

To sum up, the present invention adopt nmos differential input to PMOS Differential Input to parallel connection structure, it is possible to compare in full voltage range, it is achieved that maximumization of common mode input voltage scope, reaches track to track.

In order to realize reaching constant transconductance characteristic in whole common-mode input range, meet wireless charging control chip to the particular requirement of common-mode input range and mutual conductance.

The present invention is by appropriate design transistor (NMOS and PMOS) size, the mutual conductance in realizing circuit common-mode input range three regions (only nmos differential input to conducting, only PMOS Differential Input to conducting and NMOS with PMOS Differential Input to pipe conducting simultaneously) is the same big, namely maintains mutual conductance in whole common-mode input range constant.

As 8 times that the size of concrete scheme: a NMOS tube MN3 is NMOS tube MN1 size, the size of NMOS tube MN1 is equal with the size of NMOS tube MN2, the size of PMOS MP2 is 8 times of PMOS MP1 size, the size of PMOS MP6 is equal with the size of PMOS MP7, and the size of NMOS tube MN6 is equal with the size of NMOS tube MN7.

Constant transconductance behavioral illustrations is as follows:

If Fig. 1 is as shown, it is assumed that in biasing circuit, the size of current of bias current sources is Ibs, the gate oxide capacitance of transistor (PMOS or NMOS) unit surface is Cox, and the hole mobility of PMOS is μ_p, the pipe of PMOS MP6 is of a size of (W/L)_MP6, the electronic mobility of NMOS tube is μ_n, the pipe of NMOS tube MN6 is of a size of (W/L)_MN6;

For the ease of understanding, circuit common-mode input range can be divided into three regions, be respectively only nmos differential input to conducting, only PMOS Differential Input to conducting and NMOS and PMOS Differential Input to pipe conducting simultaneously. It is described as follows:

1). when common mode input voltage is lower, namely when Vin is less than Vthn, Vfg (voltage difference between node f and g) is relatively low, also not enough so that MN12 and MP12 conducting simultaneously, now only PMOS Differential Input, to conducting, is Ibs owing to flowing through the electric current of MP1, and the size of PMOS MP2 is N (N=4～10 of PMOS MP1 size, below with N=8 citing) doubly, it is seen that the electric current flowing through MP2 is 8*Ibs; Owing to the size of PMOS MP6 is equal with the size of PMOS MP7, being therefore 4*Ibs through the current distributing of PMOS MP2 to the electric current of MP6 (or MP7), so total mutual conductance of circuit is

$g_{m,total}=g_{m,p}=\sqrt{2{\mathrm{\&mu;}}_p{c}_{ox}{(W/L)}_{MP6}*4Ibs}$

2). common mode input voltage is higher, namely when Vin is greater than VDD-Vthp, only nmos differential inputs conducting, Vfg (voltage difference between node f and g) is relatively low, lower than MP12 thresholding Vthp and MN12 thresholding Vthp sum, not enough so that MN12 and MP12 conducting simultaneously, now only nmos differential inputs there being electric current to pass through, same, the electric current flowing through MP1 is Ibs, owing to the size of NMOS tube MN1 is equal with the size of NMOS tube MN2, the size of NMOS tube MN3 is N (N=4～10 of NMOS tube MN1 size, below with N=8 citing) doubly, therefore, the size of current flowing through NMOS tube MN2 is Ibs, the electric current flowing through MN3 is 8*Ibs, owing to the size of NMOS tube MN6 is equal with the size of NMOS tube MN7, therefore passing through shunting is 4*Ibs to the electric current of MN6 (or MN7), and so total mutual conductance of circuit is

$g_{m,total}=g_{m,n}=\sqrt{2{\mathrm{\&mu;}}_n{c}_{ox}{(W/L)}_{MN6}*4Ibs}$

3). common mode input voltage is when middle scope, namely when Vin is between Vthn and VDD-Vthp, Vfg (voltage difference between node f and g) is higher, higher than MP12 thresholding Vthp and MN12 thresholding Vthp sum, make MN12 and MP12 conducting simultaneously, the present invention is by rationally arranging the breadth-length ratio of MP12 and MN12, the electric current that the MOS pipe series connection branch road that these two diodes are connected flows through is 6*Ibs, the electric current then flowing through MP6 and MN6 is all (8*Ibs-6*Ibs)/2=Ibs, and now total mutual conductance of circuit is

$g_{m,total}=g_{m,p}+g_{m,n}=\sqrt{2{\mathrm{\&mu;}}_p{c}_{ox}{(W/L)}_{MP6}*Ibs}+\sqrt{2{\mathrm{\&mu;}}_n{c}_{ox}{(W/L)}_{MP6}*Ibs}$

In summary, the breadth-length ratio of NMOS and PMOS Differential Input pair is rationally set so that

μ_nc_ox(W/L)_MN6=μ_pc_ox(W/L)_MP6

Then the mutual conductance in above three kinds of situations is equally big, namely maintains mutual conductance in whole common-mode input range constant.

Although specifically showing in conjunction with preferred embodiment and describing the present invention; but the technician of art should be understood that; not departing from the spirit and scope of the present invention that appended claims limits; the present invention can be made a variety of changes in the form and details, be protection scope of the present invention.

Claims (6)

1. a constant transconductance track to track voltage comparator, comprises biasing circuit, double input circuit, active load and output buffer; Described biasing circuit, double input circuit, active load and output buffer are electrically connected in turn; Described biasing circuit is for providing bias current; Described double input circuit is connected with described active load, for realize within the scope of common mode input, reaching track to track and in whole common-mode input range mutual conductance constant; Described output buffer, compares signal by adopting two-stage phase inverter circuit realiration and exports; Wherein, described double input circuit comprise nmos differential input to, PMOS Differential Input to, nmos differential input to the current source of correspondence and PMOS Differential Input to the current source of correspondence, nmos differential input to PMOS Differential Input to being connected in parallel.

2. a kind of constant transconductance track to track voltage comparator according to claim 1, it is characterised in that: described double input circuit comprises voltage signal electrode input end Vinp, voltage signal negative input Vinn, PMOS MP2, PMOS MP6, PMOS MP7, PMOS MP12, NMOS tube MN6, NMOS tube MN7, NMOS tube MN12 and NMOS tube MN3, the source level of PMOS MP2 meets voltage of supply VDD, and the leakage level of PMOS MP2 is connected with the source level of the source level of PMOS MP7, PMOS MP12 and the source level of NMOS tube MN6, the grid of PMOS MP2 is connected with the grid of PMOS MP1 and active load, the grid of PMOS MP6 is connected with the grid of NMOS tube MN6 and voltage signal negative input Vinn, the drain electrode of PMOS MP6 is connected with active load, the source level of PMOS MP6 is connected with the source level of PMOS MP12, the grid of MOS pipe MP7 is connected with the grid of NMOS tube MN7 and voltage signal electrode input end Vinp, the drain electrode of PMOS MP7 is connected with active load, the source level of PMOS MP7 is connected with the source level of PMOS MP12, the grid level of PMOS MP12 is connected with drain electrode, the grid level of PMOS MP12 is connected with the grid level of NMOS tube MN12, the leakage level of PMOS MP12 is connected with the leakage level of NMOS tube MN12, the grid level of NMOS tube MN12 is connected with drain electrode, the source level of NMOS tube MN12 and the source level of NMOS tube MN6, the source level of NMOS tube MN7 and the leakage level of NMOS tube MN3 connect, the grid level of NMOS tube MN6 meets voltage signal negative input Vinn, the leakage level of NMOS tube MN6 is connected with active load, the grid level of NMOS tube MN7 meets voltage signal electrode input end Vinp, the leakage level of NMOS tube MN7 is connected with active load, the grid of NMOS tube MN3 is connected with the grid of NMOS tube MN2, the source level ground connection of NMOS tube MN3.

3. a kind of constant transconductance track to track voltage comparator according to claim 1, it is characterised in that: described biasing circuit comprises bias current sources Ibs, NMOS tube MN1, NMOS tube MN2 and PMOS MP1; The drain electrode of NMOS tube MN1 meets bias current sources Ibs; The drain electrode of NMOS tube MN1 and grid are even; The source level ground connection of NMOS tube MN1; The grid of NMOS tube MN1 is connected with the grid of NMOS tube MN2; The grid of NMOS tube MN2 is connected with double input circuit; The source level ground connection of NMOS tube MN2; The drain electrode of NMOS tube MN2 is connected with the drain electrode of PMOS MP1; The source electrode of PMOS MP1 meets voltage of supply VDD; The drain and gate of PMOS MP1 is connected.

4. a kind of constant transconductance track to track voltage comparator according to claim 1, it is characterised in that: described active load comprises PMOS MP3, PMOS MP4, PMOS MP8, PMOS MP9, NMOS tube MN4, NMOS tube MN5, NMOS tube MN8, NMOS tube MN9, biased voltage Vbs1 and biased voltage Vbs2, the source electrode of PMOS MP3 meets voltage of supply VDD, the grid of PMOS MP3 and the grid of PMOS MP2, the grid of PMOS MP4 and output buffer connect, the drain electrode of PMOS MP3 is connected with the leakage level of NMOS tube MN6 and the source electrode of PMOS MP8, the grid of PMOS MP8 connects one end of biased voltage Vbs1, the other end ground connection of biased voltage Vbs1, the leakage level of PMOS MP8 is connected with the leakage level of NMOS tube MN8 and output buffer, the grid of NMOS tube MN8 connects one end of biased voltage Vbs2, the other end ground connection of biased voltage Vbs2, the source electrode of NMOS tube MN8 is connected with the leakage level of PMOS MP6 and the leakage level of NMOS tube MN4, the source ground of NMOS tube MN4, the grid of NMOS tube MN4 is connected with the leakage level of the grid of NMOS tube MN5 and NMOS tube MN9, the source ground of NMOS tube MN5, the leakage level of NMOS tube MN5 is connected with the source electrode of the leakage level of PMOS MP7 and NMOS tube MN9, the grid of NMOS tube MN9 is connected with the grid level of NMOS tube MN8 and one end of biased voltage Vbs2, state the leakage level of NMOS tube MN9 to be connected with the leakage level of the grid of NMOS tube MN5 and PMOS MP9, the grid of PMOS MP9 is connected with one end of the grid of PMOS MP8 and biased voltage Vbs1, the source electrode of PMOS MP9 is connected with the leakage level of NMOS tube MN7 and the leakage level of PMOS MP4, the grid of PMOS MP4 and the grid of NMOS tube MN3, the grid of PMOS MP2 and output buffer connect, the source electrode of PMOS MP4 meets voltage of supply VDD.

5. a kind of constant transconductance track to track voltage comparator according to claim 1, it is characterised in that: described output buffer comprises PMOS MP5, PMOS MP10, PMOS MP11, NMOS tube MN10 and NMOS tube MN11, the source electrode of PMOS MP5 meets voltage of supply VDD, the grid of PMOS MP5 is connected with the grid of PMOS MP2, the leakage level of PMOS MP5 is connected with the source electrode of PMOS MP10, the grid of PMOS MP10 and the leakage level of PMOS MP8, the leakage level of NMOS tube MN8 and the grid of NMOS tube MN10 connect, the source ground of NMOS tube MN10, the leakage level of NMOS tube MN10 and the leakage level of PMOS MP10, the grid of PMOS MP1 and the grid of NMOS tube MN11 connect, the source electrode of PMOS MP11 meets voltage of supply VDD, the leakage level of PMOS MP11 is connected with the leakage level of NMOS tube MN11 and output end vo ut, the source ground of NMOS tube MN11.

6. a kind of constant transconductance track to track voltage comparator according to claim 1, it is characterized in that: the size of described NMOS tube MN3 is N (N=4～10) times of NMOS tube MN1 size, the size of described NMOS tube MN1 is equal with the size of NMOS tube MN2, the size of described PMOS MP2 is N (N=4～10) times of PMOS MP1 size, the size of described PMOS MP6 is equal with the size of PMOS MP7, and the size of described NMOS tube MN6 is equal with the size of NMOS tube MN7.