CN111697935B - Low-voltage rail-to-rail input and output operational amplifier - Google Patents
Low-voltage rail-to-rail input and output operational amplifier Download PDFInfo
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- CN111697935B CN111697935B CN202010617852.0A CN202010617852A CN111697935B CN 111697935 B CN111697935 B CN 111697935B CN 202010617852 A CN202010617852 A CN 202010617852A CN 111697935 B CN111697935 B CN 111697935B
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Abstract
The invention discloses a low-voltage rail-to-rail input and output operational amplifier which comprises a rail-to-rail low-impedance input stage circuit, a low-impedance diode common source circuit, a two-stage amplification stage circuit and a trans-impedance amplifier which are sequentially connected in series. The invention utilizes two half-Cascode as a rail-to-rail input stage, a low-impedance Diode common source stage and a transimpedance amplifier, so that the whole circuit can easily work under the voltage of 1.8V through perfect combination, each position in the circuit is in a low-impedance node, and a main pole is in an output stage, thereby enabling the frequency compensation to be very simple.
Description
Technical Field
The invention relates to a low-voltage rail-to-rail input and output operational amplifier.
Background
Rail-to-rail input/output operational amplifier circuits are widely used in integrated circuits, and stability, gain, and bandwidth are one of the important indicators of operational amplifiers. The traditional rail-to-rail input/output operational amplifier utilizes a pair of NMOS tubes and a pair of PMOS tubes to connect a high-impedance Cacode structure and a floating gate structure to control rail-to-rail output, so that the structure is complex, the bandwidth is low, and the key point is that the operation under low voltage is very difficult.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a low-voltage rail-to-rail input/output operational amplifier with simple structure, safety and reliability.
The technical scheme for solving the problems is as follows: a low-voltage rail-to-rail input and output operational amplifier comprises a rail-to-rail low-impedance input stage circuit, a low-impedance diode common-source circuit, a two-stage amplification stage circuit and a transimpedance amplifier, wherein an input signal is connected with the input end of the rail-to-rail low-impedance input stage circuit, the output end of the rail-to-rail low-impedance input stage circuit is connected with the input end of the low-impedance diode common-source circuit, the output end of the low-impedance diode common-source circuit is connected with the input end of the two-stage amplification stage circuit, the output end of the two-stage amplification stage circuit is connected with the input end of the transimpedance amplifier.
The rail-to-rail low impedance input/output operational amplifier comprises a rail-to-rail low impedance input stage circuit, a rail-to-rail low impedance input stage circuit and a rail-to-rail low impedance operational amplifier, wherein the rail-to-rail low impedance input stage circuit comprises a first PMOS tube, a second PMOS tube and a first NMOS tube, the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are connected together to be used as a positive input end of the rail-to-rail low impedance input stage circuit, the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube are connected together to be used as a negative input end of the rail-to-rail low impedance input stage circuit, the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and the drain electrode of the third PMOS tube, the drain electrode of the first PMOS tube is connected with a bias voltage Vb4, the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube are connected with a power supply Vdd, the drain electrode of the second PMOS tube is connected, A source electrode of the eighth PMOS tube, a source electrode of the first NMOS tube is connected with a source electrode of the second NMOS tube and a drain electrode of the third NMOS tube, a drain electrode of the second NMOS tube is connected with a drain electrode of the seventh PMOS tube and a source electrode of the ninth PMOS tube, a grid electrode of the third NMOS tube is connected with a bias voltage Vb2, and a source electrode of the third NMOS tube, a source electrode of the eighth NMOS tube and a source electrode of the ninth NMOS tube are grounded; the grid electrode of the fourth PMOS tube, the drain electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube, the drain electrode of the fourth NMOS tube and the drain electrode of the fifth NMOS tube are connected together, the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fifth NMOS tube and is connected with bias voltage Vb1, the grid electrode of the sixth NMOS tube is connected with the grid electrode of the seventh NMOS tube and is connected with bias voltage Vb2, and the source electrode of the airflow NMOS tube and the source electrode of the seventh NMOS tube are grounded; the source electrode of the sixth PMOS tube and the source electrode of the seventh PMOS tube are connected with a power supply Vdd, the grid electrode of the sixth PMOS tube is connected with the grid electrode of the seventh PMOS tube and is connected with a bias voltage Vb4, the grid electrode of the eighth PMOS tube is connected with the grid electrode of the ninth PMOS tube and is connected with a bias voltage Vb3, and the drain electrode of the eighth PMOS tube, the drain electrode of the eighth NMOS tube, the grid electrode of the eighth NMOS tube, the drain electrode of the ninth PMOS tube, the drain electrode of the ninth NMOS tube and the grid electrode of the ninth NMOS tube are connected together.
The low-voltage rail-to-rail input and output operational amplifier comprises a low-impedance diode common-source circuit and a low-impedance diode common-source circuit, wherein the low-impedance diode common-source circuit comprises tenth to thirteenth PMOS tubes and tenth to eleventh NMOS tubes, the source electrodes of the tenth to thirteenth PMOS tubes are all connected with a power supply Vdd, the grid electrode of the tenth PMOS tube is connected with the grid electrode of the fourth PMOS tube, the drain electrode of the tenth PMOS tube, the grid electrode of the eleventh PMOS tube, the drain electrode of the eleventh PMOS tube and the source electrode of the tenth NMOS tube are connected together, the grid electrode of the twelfth PMOS tube is connected with the grid electrode of the fifth PMOS tube, the drain electrode of the twelfth PMOS tube, the grid electrode of the thirteenth PMOS tube, the drain electrode of the thirteenth PMOS tube and the source electrode of the eleventh NMOS tube are connected together, the grid electrode of the tenth NMOS tube is connected with the grid electrode of the eighth NMOS tube, the grid electrode of the eleventh NMOS tube is connected with the grid electrode of the ninth NMOS.
The two-stage amplifier stage circuit comprises fourteenth to seventeenth PMOS transistors and twelfth to seventeenth NMOS transistors, wherein the sources of the fourteenth to seventeenth PMOS transistors are all connected to a power supply Vdd, the gate of the fourteenth PMOS transistor, the drain of the twelfth NMOS transistor, the gate of the fourteenth NMOS transistor, the gate of the fifteenth PMOS transistor, the drain of the fifteenth PMOS transistor, the gate of the fifteenth NMOS transistor and the drain of the thirteenth NMOS transistor are connected together, the gate of the twelfth NMOS transistor is connected to the source of the tenth NMOS transistor, the source of the twelfth NMOS transistor is connected to the source of the thirteenth NMOS transistor and the drain of the sixteenth NMOS transistor, the gate of the thirteenth NMOS transistor is connected to the source of the eleventh NMOS transistor, the gate of the sixteenth NMOS transistor and the gate of the seventeenth NMOS transistor are connected to a bias voltage Vb2, the source of the sixteenth NMOS transistor and the source of the seventeenth NMOS transistor are grounded, the gates of the sixteenth PMOS transistor and the gate of the fifteenth PMOS transistor are connected to a power supply Vdd, The drain electrode of the sixteenth PMOS tube, the drain electrode of the seventeenth NMOS tube, the grid electrode of the seventeenth PMOS tube, the drain electrode of the seventeenth PMOS tube and the drain electrode of the fifteenth NMOS tube are connected together, and the source electrode of the fourteenth NMOS tube, the source electrode of the fifteenth NMOS tube and the drain electrode of the seventeenth NMOS tube are connected together.
The low-voltage rail-to-rail input and output operational amplifier comprises eighteenth to twenty-first PMOS tubes, eighteenth to twenty-second NMOS tubes and a capacitor, wherein the sources of the eighteenth to twenty-first PMOS tubes are all connected with a power supply Vdd, the grid of the eighteenth PMOS tube, the grid of the nineteenth PMOS tube, the drain of the nineteenth PMOS tube and the drain of the nineteenth NMOS tube are connected together, the drain of the eighteenth PMOS tube, the grid of the eighteenth NMOS tube, the drain of the eighteenth NMOS tube and the grid of the twenty-second NMOS tube are connected together, the grid of the nineteenth NMOS tube is connected with the drain of the fourteenth NMOS tube, the source of the nineteenth NMOS tube, the source of the twentieth NMOS tube and the drain of the twenty-first NMOS tube are connected together, the grid of the twenty-first NMOS tube is connected with a bias voltage Vb2, the source of the twenty-first NMOS tube, the source of the twenty-second NMOS tube and one end of the capacitor are grounded, and the grids of the twentieth, The drain electrode of the twentieth PMOS tube, the grid electrode of the twenty-first PMOS tube and the drain electrode of the twentieth NMOS tube are connected together, the grid electrode of the twentieth NMOS tube is connected with the drain electrode of the fifteenth NMOS tube, and the drain electrode of the twenty-first PMOS tube, the drain electrode of the twenty-second NMOS tube and the other end of the capacitor are connected together and serve as the output end of the whole operational amplifier.
In the low-voltage rail-to-rail input and output operational amplifier, the rail-to-rail low-impedance input stage circuit comprises two half-Cascode structures, wherein the first half-Cascode structure is composed of a fourth PMOS (P-channel metal oxide semiconductor) transistor, a fifth PMOS transistor and fourth to seventh NMOS (N-channel metal oxide semiconductor) transistors, and the fourth PMOS transistor and the fifth PMOS transistor are connected into a Diode structure; the second half Cascode structure is composed of sixth to ninth PMOS tubes, eighth NMOS tube and ninth NMOS tube, and the eighth NMOS tube and the ninth NMOS tube are connected to form a Diode structure.
The invention has the beneficial effects that: the invention does not depend on the high-impedance rail-to-rail input of the traditional structure and the rail-to-rail output controlled by the floating gate structure, but perfectly utilizes two half-Cascode as the rail-to-rail input stage, the low-impedance Diode common source stage and the transimpedance amplifier, so that the whole circuit can easily work under the voltage of 1.8V through the perfect combination, each part in the circuit is in the low-impedance node, and the main pole is in the output stage, thereby the frequency compensation is very simple, and in the equivalent gain amplifier, the invention has the outstanding advantages of high bandwidth, high power supply rejection ratio, low noise and the like.
Drawings
Fig. 1 is a circuit diagram of the present invention.
FIG. 2 is a graph of gain simulation of the present invention.
FIG. 3 is a noise simulation diagram of the present invention.
Fig. 4 is a simulation diagram of the power supply rejection ratio of the present invention.
FIG. 5 is a circuit linearity simulation diagram of the present invention.
Detailed Description
The invention is further described below with reference to the figures and examples.
As shown in fig. 1, a low-voltage rail-to-rail input/output operational amplifier includes a rail-to-rail low-impedance input stage circuit, a low-impedance diode common-source circuit, a two-stage amplifier stage circuit, and a transimpedance amplifier, wherein an input signal is connected to an input terminal of the rail-to-rail low-impedance input stage circuit, an output terminal of the rail-to-rail low-impedance input stage circuit is connected to an input terminal of the low-impedance diode common-source circuit, an output terminal of the low-impedance diode common-source circuit is connected to an input terminal of the two-stage amplifier stage circuit, an output terminal of the two-stage amplifier stage circuit is connected to an input terminal of the transimpedance.
The rail-to-rail low-impedance input stage circuit comprises a first PMOS tube Mp1, a second PMOS tube Mp2, a third PMOS tube Mp3, a fourth PMOS tube Mp4, a fifth PMOS tube Mp5, a sixth PMOS tube Mp6, a seventh PMOS tube Mp7, an eighth PMOS tube Mp8, a ninth PMOS tube Mp9, a first NMOS tube Mn1, a second NMOS tube Mn2, a third NMOS tube Mn3, a fourth NMOS tube Mn4, a fifth NMOS tube Mn5, a sixth NMOS tube Mn6, a seventh NMOS tube Mn7, an eighth NMOS tube Mn7, a ninth NMOS tube Mn7, a gate of the first PMOS tube Mp7, a gate of the first NMOS tube Mn7 are connected together to serve as a positive input end of the rail-to-rail low-impedance input stage circuit, a gate of the second PMOS tube Mp7 and a gate of the second NMOS tube Mn7 are connected together to serve as a drain of the first PMOS tube Mp7, a drain of the fourth PMOS tube Mn7 is connected to a drain of the fourth PMOS tube Mp7, a drain of the drain 7, the grid electrode of the third PMOS tube Mp3 is connected with a bias voltage Vb4, the source electrode of the third PMOS tube Mp3, the source electrode of the fourth PMOS tube Mp4 and the source electrode of the fifth PMOS tube Mp5 are connected with a power supply Vdd, the drain electrode of the second PMOS tube Mp2 is connected with the source electrode of the fifth NMOS tube Mn5 and the drain electrode of the seventh NMOS tube Mn7, the drain electrode of the first NMOS tube Mn1 is connected with the drain electrode of the sixth PMOS tube Mp6 and the source electrode of the eighth PMOS tube Mp8, the source electrode of the first NMOS tube Mn1 is connected with the source electrode of the second NMOS tube Mn2 and the drain electrode of the third NMOS tube Mn3, the drain electrode of the second NMOS tube Mn2 is connected with the drain electrode of the seventh PMOS tube Mp 42 and the source electrode of the ninth PMOS tube Mp9, the grid electrode of the third NMOS tube Mn3 is connected with a bias voltage Vb2, the source electrode of the third NMOS tube Mn3, the source electrode of the eighth NMOS tube Mn8 and the source electrode of the ninth NMOS; the grid electrode of the fourth PMOS tube Mp4, the drain electrode of the fourth PMOS tube Mp4, the grid electrode of the fifth PMOS tube Mp5, the drain electrode of the fifth PMOS tube Mp5, the drain electrode of the fourth NMOS tube Mn4 and the drain electrode of the fifth NMOS tube Mn5 are connected together, the grid electrode of the fourth NMOS tube Mn4 is connected with the grid electrode of the fifth NMOS tube Mn5 and connected with a bias voltage Vb1, the grid electrode of the sixth NMOS tube Mn6 is connected with the grid electrode of the seventh NMOS tube Mn7 and connected with a bias voltage Vb2, and the source electrode of the airflow NMOS tube and the source electrode of the seventh NMOS tube Mn7 are grounded; the source electrode of the sixth PMOS tube Mp6 and the source electrode of the seventh PMOS tube Mp7 are connected with a power supply Vdd, the gate electrode of the sixth PMOS tube Mp6 is connected with the gate electrode of the seventh PMOS tube Mp7 and is connected with a bias voltage Vb4, the gate electrode of the eighth PMOS tube Mp8 is connected with the gate electrode of the ninth PMOS tube Mp9 and is connected with a bias voltage Vb3, and the drain electrode of the eighth PMOS tube Mp8, the drain electrode of the eighth NMOS tube Mn8, the gate electrode of the eighth NMOS tube Mn8, the drain electrode of the ninth PMOS tube Mp9, the drain electrode of the ninth NMOS tube Mn9 and the gate electrode of the ninth NMOS tube Mn9 are connected together. The rail-to-rail low-impedance input stage circuit comprises two half-Cascode structures, wherein the first half-Cascode structure is composed of a fourth PMOS tube Mp4, a fifth PMOS tube Mp5 and fourth to seventh NMOS tubes Mn7, and the fourth PMOS tube Mp4 and the fifth PMOS tube Mp5 are connected to form a Diode structure; the second half Cascode structure is formed by connecting sixth to ninth PMOS transistors Mp9, eighth NMOS transistor Mn8, and ninth NMOS transistor Mn9, and the eighth NMOS transistor Mn8 and the ninth NMOS transistor Mn9 are connected to form a Diode structure.
The low-impedance diode common-source circuit comprises a tenth PMOS tube Mp10, an eleventh PMOS tube Mp11, a twelfth PMOS tube Mp12, a thirteenth PMOS tube Mp13, a tenth NMOS tube Mn10, an eleventh NMOS tube Mn11, a tenth PMOS tube Mp10, an eleventh PMOS tube Mp11, a twelfth PMOS tube Mp12, and a thirteenth PMOS tube Mp13, the sources of which are all connected with a power supply Vdd, the gate of the tenth PMOS tube Mp10 is connected with the gate of the fourth PMOS tube Mp4, the drain of the tenth PMOS tube Mp10, the gate of the eleventh PMOS tube Mp11, the drain of the eleventh PMOS tube Mp11, and the source of the tenth NMOS tube Mn10 are connected together, the gate of the twelfth PMOS tube Mp12 is connected with the gate of the fifth PMOS tube Mp5, the drain of the twelfth PMOS tube Mp12, the gate of the thirteenth tube Mp12, the source of the thirteenth tube Mp12, the eleventh NMOS tube Mn12, the gate of the eleventh PMOS tube Mp12 is connected with the gate of the eleventh NMOS tube Mn12, the drain of the eleventh PMOS tube Mn12 is connected with the drain of the eleventh NMOS tube Mn12, the drain of the eleventh tube Mn12, the drain of the NMOS tube Mn12, The drain of the eleventh NMOS transistor Mn11 is grounded. The Mp11 is connected to the Mp10 in a mode of a Diode connection, the Mp13 is connected to the Mp12 in a mode of a Diode connection, and signals are output from drain terminals of Mn10 and Mn11 and are connected to the next stage.
The two-stage amplification stage circuit comprises a fourteenth PMOS tube Mp14, a fifteenth PMOS tube Mp15, a sixteenth PMOS tube Mp16, a seventeenth PMOS tube Mp17, a twelfth NMOS tube Mn12, a thirteenth NMOS tube Mn13, a fourteenth NMOS tube Mn14, a fifteenth NMOS tube Mn15, a sixteenth NMOS tube Mn16, a seventeenth NMOS tube Mn17, a fourteenth PMOS tube Mp14, a fifteenth PMOS tube Mp15, a sixteenth PMOS tube Mp16, and a seventeenth PMOS tube Mp16, wherein the sources of the fourteenth PMOS tube Mp16, the drain of the twelfth PMOS tube Mn16, the gate of the fourteenth NMOS tube Mn16, the gate of the fifteenth PMOS tube Mp16, the gate of the fifteenth NMOS tube Mp16, the fifteenth PMOS tube Mp16, the drain of the fifteenth NMOS tube Mn16, the drain of the thirteenth NMOS tube Mn16, the source of the thirteenth NMOS tube Mn16, the eleventh NMOS tube Mn16, the source of the thirteenth NMOS tube Mn16, the source of the twelfth NMOS tube Mn16, the twelfth NMOS, the gate of the sixteenth NMOS transistor Mn16 and the gate of the seventeenth NMOS transistor Mn17 are connected to the bias voltage Vb2, the source of the sixteenth NMOS transistor Mn16 and the source of the seventeenth NMOS transistor Mn17 are grounded, the gate of the sixteenth PMOS transistor Mp16, the drain of the sixteenth PMOS transistor Mp16, the drain of the seventeenth NMOS transistor Mn17, the gate of the seventeenth PMOS transistor Mp17, the drain of the seventeenth PMOS transistor Mp17 and the drain of the fifteenth NMOS transistor Mn15 are connected together, and the source of the fourteenth NMOS transistor Mn14, the source of the fifteenth NMOS transistor Mn15 and the drain of the seventeenth NMOS transistor Mn17 are connected together. The two-stage amplification stage circuit consists of two stages of five-tube amplifiers, Mn12 and Mn13 form a first-stage input pair tube, Mp14 and Mp15 are connected into a Diode to form a first-stage output load, Mn14 and Mn15 form a second-stage input pair tube, and Mp16 and Mp17 are connected into a Diode to form a second-stage output load.
The transimpedance amplifier comprises an eighteenth PMOS tube Mp18, a nineteenth PMOS tube Mp19, a twentieth PMOS tube Mp20, a twenty-first PMOS tube Mp21, an eighteenth NMOS tube Mn18, a nineteenth NMOS tube Mn19, a twentieth NMOS tube Mn20, a twenty-first NMOS tube Mn21, a twenty-second NMOS tube Mn22, a capacitor C0, an eighteenth PMOS tube Mp18, a nineteenth PMOS tube Mp19, a twentieth PMOS tube Mp20 and a twenty-first PMOS tube Mp21, wherein the sources of the eighteenth PMOS tube Mp18, the gate of the nineteenth PMOS tube Mp19, the drain of the nineteenth PMOS tube Mp19, the drain of the nineteenth NMOS tube Mn19 are all connected with a power supply Vdd, the gate of the eighteenth PMOS tube Mp18, the drain of the eighteenth NMOS tube Mn18, the drain of the twenty-second NMOS tube Mn18, the drain of the twenty-ninth NMOS tube Mn18 and the drain of the twenty-first NMOS tube Mn18 are connected together, the grid electrode of the twenty-first NMOS tube Mn21 is connected with the bias voltage Vb2, the source electrode of the twenty-first NMOS tube Mn21, the source electrode of the twenty-second NMOS tube Mn22 and one end of the capacitor C0 are grounded, the grid electrode of the twentieth PMOS tube Mp20, the drain electrode of the twentieth PMOS tube Mp20, the grid electrode of the twenty-first PMOS tube Mp21 and the drain electrode of the twentieth NMOS tube Mn20 are connected together, the grid electrode of the twentieth NMOS tube Mn20 is connected with the drain electrode of the fifteenth NMOS tube Mn15, and the drain electrode of the twenty-first PMOS tube Mp21, the drain electrode of the twenty-second NMOS tube Mn22 and the other end of the capacitor C0 are connected together and serve as the output end of the whole. Mp19, Mn20 form the input pair of transistors of the OTA, the drain terminals of Mp21, Mn22 serve as output terminals, and all nodes except the input and output nodes are connected to either a gate-drain connected transistor or a voltage source.
The working principle of the invention is as follows: the input signals are input from the gates of Mp1, Mp2, Mn1 and Mn2, and the range of the input signals can be from the power supply to the ground because the structure is that Mp1 and Mn1 are connected together, and Mp2 and Mn2 are connected together. When the input signal is close to the power supply, the input pair transistors Mp1 and Mp2 are conductive, when the input signal is close to the ground, the input pair transistors Mn1 and Mn2 are conductive, and when the input signal is near 1/2Vdd, both pairs of input transistors are conductive. In summary, Mn1, Mn2 and Mp1, Mp2 turn on in turn or together during the entire input signal. Signals pass through the first part and are output from A, B, C, D four points of two half-Cascode, because the four tubes Mp4, Mp5, Mn8 and Mn9 are all connected by a Diode, and the corresponding output resistance is:
RA (point a output resistance) =1/gmp4// gmn4 (ron4 ron6) =1/gmp4 (1)
RB (point B output resistance) =1/gmp5// gmn5 (ron5 ron7) =1/gmp5 (2)
RC (C point output resistance) =1/gmn8// gmp8 (rop8 rop6) =1/gmn8 (3)
RD (D point output resistance) =1/gmn9// gmp9 (rop7 rop9) =1/gmn9 (4)
Wherein, gmp4, gmn4, gmp5, gmn5, gmp8, gmn8, gmp9, and gmn9 are transconductance of Mp4, Mn4, Mp5, Mn5, Mp8, Mn8, Mp9, and Mn9, respectively, and ron4, ron5, ron6, ron7, rop6, rop7, rop8, rop9 are small signal output resistance of Mn4, Mn5, Mn6, Mn7, Mp6, Mp7, Mp8, and Mp9, respectively.
From the output resistance formula, we can see that the four points are all low-impedance nodes, so that the dominant pole does not appear in the first part, and the nodes are all high-frequency poles, which provides a condition for high bandwidth.
The second part is a low-impedance common-source structure, because Mp11 and Mp13 are connected in a Diode structure and connected to two ends of Mp10 and Mp12, the common-source output end E, F becomes a low-impedance node:
RE (E point output resistance) =1/gmp11// rop10// ron10=1/gmp11 (5)
RF (F point output resistance) =1/gmp13// rop12// ron11=1/gmp13 (6)
Wherein gmp11 and gmp13 are transconductance of Mp11 and Mp13, respectively, and ron10, ron11, rop10 and rop12 are small-signal output resistances of Mn10, Mn11, Mp10 and Mp12, respectively.
Signals enter from Mp10, Mn10, Mp12 and Mn12, and a circulation path is provided for two half-cascodes, and the part is always in a conducting state during the whole signal input period.
The third section is a two-stage conventional five-tube amplifier, the load is no longer a common current source, but the Diode is used as the load, the output node G, H, I, J is intentionally made to be a low impedance output, where the output node resistance:
RG (G dot output resistance) =1/gmp14// ron12=1/gmp14 (7)
RH (H point output resistance) =1/gmp15// ron13=1/gmp15 (8)
RI (I point output resistance) =1/gmp16// ron14=1/gmp16 (9)
RJ (J point output resistance) =1/gmp17// ron15=1/gmp17 (10)
Wherein gmp14, gmp15, gmp16 and gmp17 are transconductance of Mp14, Mp15, Mp16 and Mp17 respectively, and ron12, ron13, ron14 and ron15 are small signal output resistances of Mn14, Mn15, Mn16 and Mn17 respectively.
This part is mainly to provide part of the gain, in addition to providing a circulation path for the signal.
The fourth part is a transimpedance amplifier OTA, all nodes except an output node of the transimpedance amplifier are low-impedance nodes, most of gain is provided in the whole circuit, the output node is the dominant pole of the whole circuit, frequency compensation is simple, and only one compensation capacitor needs to be added at the output end. The output node resistance is:
RK (K dot output resistance) = rop21// rop22 (11)
Here, rop21 and rop22 are small signal output resistances of Mp21 and Mp22, respectively.
The circuit bandwidth mainly depends on the output impedance and the output compensation capacitor C, because the output voltage is:
Vout=Iout*(1/jw*C0)=gm*Vin*(1/jw*C0) (12)
where Iout is the output current, jw is the angular frequency, gm is the input transconductance of the amplifier, C0 is the compensation capacitor, and Vin is the input voltage.
It can then be derived:
Vout/Vin=gm/jw*C0 (13)
since the unity gain is defined as the corresponding frequency when the open loop gain is unity, the following formula:
gm/(2π*f*C0)=1 (14)
where f is the frequency.
To obtain:
f=gm/(2π*C0) (15)
in the whole circuit design, in order to ensure the light operation under low voltage, the number of the serial NMOS or PMOS between the power supply Vdd and the ground Vss of each partial circuit is not more than 3,
|vds1|+|vds2|+|vd3|<Vdd (1.8 V) (16)
wherein vds is the drain-source voltage of the MOS transistor DE 1.
In order to ensure the gain is 90 dB, the circuit uses 5 stages of amplifiers, wherein the gain of each stage of the first 4 stages of amplifiers does not exceed 6 dB, and the gain of the last stage of amplifiers is maximized, and the aim of the circuit is to minimize the noise output by the amplifiers. It is known that noise passes through the first stage and then is amplified stage by stage, so that the gain of the front stage is important, the noise is most important in the first stage, and the influence of the noise is smaller as the noise goes to the amplifier of the later stage.
Since each node of each stage circuit except the last stage is specially made to be a low-impedance node in the whole design, a dominant pole exists in the circuit and is at the output stage of the last stage. Thus, the bandwidth of the whole circuit is much wider than that of other equivalent amplifiers, and the circuit can provide 95 dB gain and 18M bandwidth by simulating the situation shown in FIG. 2.
Just as the gain settings of the previous stages minimize the output noise, the noise simulation diagram is shown in fig. 3. By integrating the noise curve of fig. 3 from 1 to 1T, the output noise voltage is 175 μ V, and this circuit structure makes the output noise very small, so that it is very suitable for an amplifying circuit with high noise requirement.
The power supply rejection ratio simulation diagram of the circuit diagram is shown in fig. 4. From the simulation, the power supply rejection ratio is very good in the whole frequency range, the power supply rejection ratio in the bandwidth of 0 to 1M is 105 dB, the power supply rejection ratio of 1M to 1T can reach 88 dB, and the power supply rejection ratio of the circuit is very high even in the high frequency range.
Fig. 5 is a simulation diagram of circuit linearity. The input signal is input from 0 to 1.8V of the power supply voltage, the output signal is seen to follow the input voltage and is output from 0 to 1.8V, the linearity is good in the whole process, particularly, the difference between the input and the output is only about 180 mu V between 0.4V and 1.4V, and the linearity is very good in the range.
From the principle analysis and the simulation result, the circuit completely abandons the traditional Cascode high-impedance rail-to-rail input and floating gate controlled rail-to-rail output structure, and the traditional structure is very difficult to work under low voltage. The circuit completely uses a brand new structure mode, successfully eliminates the traditional Cascode structure, has simple structure, is easy to analyze, and adopts two half Cascode structures with low impedance input. In order to enable the whole rail-to-rail input to completely flow and ensure that no high impedance node exists, two common source circuits are used for simultaneously connecting the outputs of two half-Cascode circuits, and a Diode structure is connected in parallel on the common source circuits. Therefore, the whole circuit is all low-impedance nodes except the high impedance of the output node, so that only one dominant pole is arranged at the output end, the frequency compensation is easy, and the bandwidth is better than that of the similar amplifier. Due to the characteristics of gain setting of each stage and the frequency compensation capacitor connected to the output end, the circuit has low noise, good power supply rejection ratio at high frequency and good linearity of the whole circuit. According to the series of advantages, the circuit is suitable for circuits which need low noise, high bandwidth, high gain and good linearity, and particularly works in a low-voltage data converter ADC signal input BUFFER.
Claims (5)
1. A low voltage rail-to-rail input-output operational amplifier, comprising: the low-impedance input circuit comprises a rail-to-rail low-impedance input stage circuit, a low-impedance diode common-source circuit, a two-stage amplification stage circuit and a transimpedance amplifier, wherein an input signal is connected with the input end of the rail-to-rail low-impedance input stage circuit, the output end of the rail-to-rail low-impedance input stage circuit is connected with the input end of the low-impedance diode common-source circuit, the output end of the low-impedance diode common-source circuit is connected with the input end of the two-stage amplification stage circuit, the output end of the two-stage amplification stage circuit is connected with the input end of the;
the rail-to-rail low-impedance input stage circuit comprises first to ninth PMOS tubes and first to ninth NMOS tubes, wherein the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are connected together to serve as a positive input end of the rail-to-rail low-impedance input stage circuit, the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube are connected together to serve as a negative input end of the rail-to-rail low-impedance input stage circuit, the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and the drain electrode of the third PMOS tube, the drain electrode of the first PMOS tube is connected with the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube and the drain electrode of the sixth NMOS tube, the grid electrode of the third PMOS tube is connected with a bias voltage Vb4, the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube are connected with a power supply Vdd, the drain electrode of the second PMOS tube is connected with the source electrode of the fifth NMOS tube and the drain electrode of the seventh NMOS tube, the drain electrode, The drain electrode of the third NMOS tube, the drain electrode of the second NMOS tube is connected with the drain electrode of the seventh PMOS tube and the source electrode of the ninth PMOS tube, the grid electrode of the third NMOS tube is connected with a bias voltage Vb2, and the source electrode of the third NMOS tube, the source electrode of the eighth NMOS tube and the source electrode of the ninth NMOS tube are grounded; the grid electrode of the fourth PMOS tube, the drain electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube, the drain electrode of the fourth NMOS tube and the drain electrode of the fifth NMOS tube are connected together, the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fifth NMOS tube and connected with bias voltage Vb1, the grid electrode of the sixth NMOS tube is connected with the grid electrode of the seventh NMOS tube and connected with bias voltage Vb2, and the source electrode of the sixth NMOS tube and the source electrode of the seventh NMOS tube are grounded; the source electrode of the sixth PMOS tube and the source electrode of the seventh PMOS tube are connected with a power supply Vdd, the grid electrode of the sixth PMOS tube is connected with the grid electrode of the seventh PMOS tube and is connected with a bias voltage Vb4, the grid electrode of the eighth PMOS tube is connected with the grid electrode of the ninth PMOS tube and is connected with a bias voltage Vb3, and the drain electrode of the eighth PMOS tube, the drain electrode of the eighth NMOS tube, the grid electrode of the eighth NMOS tube, the drain electrode of the ninth PMOS tube, the drain electrode of the ninth NMOS tube and the grid electrode of the ninth NMOS tube are connected together.
2. The low-voltage rail-to-rail input-output operational amplifier according to claim 1, wherein: the low-impedance diode common-source circuit comprises tenth to thirteenth PMOS tubes and tenth to eleventh NMOS tubes, wherein the sources of the tenth to thirteenth PMOS tubes are all connected with a power supply Vdd, the grid electrode of the tenth PMOS tube is connected with the grid electrode of the fourth PMOS tube, the drain electrode of the tenth PMOS tube, the grid electrode of the eleventh PMOS tube, the drain electrode of the eleventh PMOS tube and the source electrode of the tenth NMOS tube are connected together, the grid electrode of the twelfth PMOS tube is connected with the grid electrode of the fifth PMOS tube, the drain electrode of the twelfth PMOS tube, the grid electrode of the thirteenth PMOS tube, the drain electrode of the thirteenth PMOS tube and the source electrode of the eleventh NMOS tube are connected together, the grid electrode of the tenth NMOS tube is connected with the grid electrode of the eighth NMOS tube, the grid electrode of the eleventh NMOS tube is connected with the grid electrode of the ninth NMOS tube, and the drain electrodes of the tenth and the eleventh NMOS tube are grounded.
3. The low voltage rail-to-rail input-output operational amplifier of claim 2, wherein: the two-stage amplification stage circuit comprises fourteenth to seventeenth PMOS tubes and twelfth to seventeenth NMOS tubes, wherein source electrodes of the fourteenth to seventeenth PMOS tubes are all connected with a power supply Vdd, a grid electrode of the fourteenth PMOS tube, a drain electrode of the twelfth NMOS tube, a grid electrode of the fourteenth NMOS tube, a grid electrode of the fifteenth PMOS tube, a drain electrode of the fifteenth PMOS tube, a grid electrode of the fifteenth NMOS tube and a drain electrode of the thirteenth NMOS tube are connected together, a grid electrode of the twelfth NMOS tube is connected with a source electrode of the tenth NMOS tube, a source electrode of the twelfth NMOS tube is connected with a source electrode of the thirteenth NMOS tube and a drain electrode of the sixteenth NMOS tube, a grid electrode of the thirteenth NMOS tube and a grid electrode of the seventeenth NMOS tube are connected with a bias voltage Vb2, a source electrode of the sixteenth NMOS tube and a source electrode of the seventeenth NMOS tube are grounded, a grid electrode of the sixteenth PMOS tube, a drain electrode of the seventeenth NMOS tube, a drain electrode of, The grid electrode of the seventeenth PMOS tube, the drain electrode of the seventeenth PMOS tube and the drain electrode of the fifteenth NMOS tube are connected together, and the source electrode of the fourteenth NMOS tube, the source electrode of the fifteenth NMOS tube and the drain electrode of the seventeenth NMOS tube are connected together.
4. The low-voltage rail-to-rail input-output operational amplifier according to claim 3, wherein: the transimpedance amplifier comprises eighteenth to twenty-first PMOS tubes, eighteenth to twenty-second NMOS tubes and a capacitor, wherein the sources of the eighteenth to twenty-first PMOS tubes are all connected with a power supply Vdd, the grids of the eighteenth PMOS tubes, the grid of the nineteenth PMOS tube, the drain of the nineteenth PMOS tube and the drain of the nineteenth NMOS tube are connected together, the drain of the eighteenth PMOS tube, the grid of the eighteenth NMOS tube, the drain of the eighteenth NMOS tube and the grid of the twenty-second NMOS tube are connected together, the grid of the nineteenth NMOS tube is connected with the drain of the fourteenth NMOS tube, the source of the nineteenth NMOS tube, the source of the twentieth NMOS tube and the drain of the twenty-first NMOS tube are connected together, the grid of the twenty-first NMOS tube is connected with a bias voltage Vb2, the source of the twenty-first NMOS tube, the source of the twenty-second NMOS tube and one end of the capacitor are grounded, the grid of the twentieth PMOS tube, the drain, The drain electrodes of the twenty-first PMOS tube, the drain electrode of the twenty-second NMOS tube and the other end of the capacitor are connected together and serve as the output end of the whole operational amplifier.
5. The low-voltage rail-to-rail input-output operational amplifier according to claim 1, wherein: the rail-to-rail low-impedance input stage circuit comprises two half-Cascode structures, wherein the first half-Cascode structure is composed of a fourth PMOS (P-channel metal oxide semiconductor) tube, a fifth PMOS tube and fourth to seventh NMOS (N-channel metal oxide semiconductor) tubes, and the fourth PMOS tube and the fifth PMOS tube are connected into a Diode structure; the second half Cascode structure is composed of sixth to ninth PMOS tubes, eighth NMOS tube and ninth NMOS tube, and the eighth NMOS tube and the ninth NMOS tube are connected to form a Diode structure.
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| US6710660B1 (en) * | 2002-09-17 | 2004-03-23 | National Semiconductor Corporation | Class B power buffer with rail to rail output swing and small deadband |
| CN101047362A (en) * | 2006-03-28 | 2007-10-03 | 株式会社理光 | Operation amplifier |
| CN110943705A (en) * | 2020-01-02 | 2020-03-31 | 电子科技大学 | Rail-to-rail input and output operational amplifier based on bipolar process |
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| US6710660B1 (en) * | 2002-09-17 | 2004-03-23 | National Semiconductor Corporation | Class B power buffer with rail to rail output swing and small deadband |
| CN101047362A (en) * | 2006-03-28 | 2007-10-03 | 株式会社理光 | Operation amplifier |
| CN110943705A (en) * | 2020-01-02 | 2020-03-31 | 电子科技大学 | Rail-to-rail input and output operational amplifier based on bipolar process |
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