CN103825557B - Transconductance amplifier with low power consumption and high linearity - Google Patents

Abstract

The invention relates to the technical field of simulative integrated operational amplifiers, in particular to a Push-Pull transconductance amplifier with low power consumption and high linearity. The transconductance amplifier comprises a biasing circuit, a Rail-to-Rail input stage and a Push-Pull output stage which are connected in sequence, wherein the biasing circuit is formed by an image current telescope and is used for providing bias voltage for the Rail-to-Rail input stage and the Push-Pull output stage; the Rail-to-Rail input stage adopts a folding NMOS (N-Channel Metal Oxide Semiconductor) differential pair and a PMOS (P-Channel Metal Oxide Semiconductor) differential pair to realize rail-to-rail in a common-mode input range, and adopts negative feedback of a source electrode to realize linear transconductance; the Push-Pull output stage adopts bias with low power consumption to realize push-pull output with low power consumption, and adopts image current amplification to improve the output driving capacity. The transconductance amplifier has the advantages of simple structure, high linearity, low power consumption, high power supply rejection ratio, small chip area and the like, and is particularly suitable for the transconductance amplifier.

Description

A kind of low-power consumption high linearity trsanscondutance amplifier

Technical field

The present invention relates to Analog Integrated Operation amplifier technical field, be specifically related to a kind of low-power consumption high linearity Push-Pull mutual conductance and amplify Device.

Background technology

Operation transconductance amplifier (OTA), as one of basis important in analog circuitry system and key modules, is widely used in electricity In the systems such as source, power amplification, signal processing, the performance level of amplifier directly determines the quality of whole system performance.Due to Different application occasion is different to the requirement of operation transconductance amplifier index parameter, and the design of operation transconductance amplifier is many based on answering With the system requirement to its performance indications.

In field of switch power, as the error amplifier of voltage control loop core, its index request is tied in different system topology Under structure, different feedback signal type the most different.Low merit will be used under some system topology and feedback signal type The error amplifier of consumption high linearity constitutes voltage control loop, such as be AC signal when feedback signal type in actual application Time, error amplifier is accomplished by accepting wide scope input, and the nonlinear problem that wide input range introduces is also required to designer and considers； When the output of error amplifier drives PWM(Pulse Width Modulation) controller is when requiring big range of accommodation, by mistake Difference amplifier is accomplished by big output voltage swing；When chip to the requirement of power consumption the strictest time, the design of error amplifier will be use up Possible reduction power consumption.It is based on this kind of application demand, designs and can make the low-power consumption high linearity mutual conductance of error amplifier and put Big utensil has good realistic meaning.

The OTA linearity that tradition source electrode coupled difference structure for amplifying realizes is limited to tail current I_SSAnd βIf Want that improving linear input range is necessary for increasing tail current I_SSOr reduce β；Contradiction is to increase I_SSPower consumption can be increased, reduce β Can reduce common-mode input range, thus traditional amplifier does not the most possess and has high linearity, low-power consumption and wide input range simultaneously.

Summary of the invention

To be solved by this invention, it is simply that the problem existed for above-mentioned Conventional amplifiers, simultaneously in order to realize supply voltage switch Control loop to error amplifier low-power consumption and the requirement of high linearity, it is proposed that a kind of low-power consumption height line making error amplifier Property degree Push-Pull trsanscondutance amplifier.

The present invention solves above-mentioned technical problem and be the technical scheme is that a kind of low-power consumption high linearity trsanscondutance amplifier, and it is special Levy and be, including the biasing circuit being sequentially connected with, Rail-to-Rail input stage and Push-Pull output stage；Described biased electrical Route image current telescope composition, provides bias voltage for Rail-to-Rail input stage and Push-Pull output stage；Described Rail-to-Rail input stage use collapsible nmos differential to and PMOS differential pair realize common-mode input range rail-to-rail, and adopt Linearisation mutual conductance is realized by source negative feedback；Described Push-Pull output stage uses low-power consumption biasing to realize low-power consumption and recommends output, And use image current to amplify raising output driving force.

Concrete, described biasing circuit include the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the Four PMOS MP4, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3 and current source；

Described Rail-to-Rail input stage include the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7, 8th PMOS MP8, the 9th PMOS MP9, the tenth PMOS MP10, the 11st PMOS MP11, the 12nd PMOS Pipe MP12, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS Pipe MN8, the 9th NMOS tube MN9, the tenth NMOS tube MN10, the 11st NMOS tube MN11, the first resistance RSN and second electricity Resistance RSP；

Described Push-Pull output stage includes the 13rd PMOS MP13, the 14th PMOS MP14, the 15th PMOS MP15, the 16th PMOS MP16, the 17th PMOS MP17, the 18th PMOS MP18, the 12nd NMOS tube MN12, 13rd NMOS tube MN13, the 14th NMOS tube MN14, the 15th NMOS tube MN15, the 16th NMOS tube MN16, 17 NMOS tube MN17, the 3rd resistance RBP and the 4th resistance RBN；Wherein,

First PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 9th PMOS MP9, the tenth PMOS MP10, the 15th PMOS MP15, the 16th PMOS MP16 source lining end and the 11st PMOS MP11, the 12nd PMOS MP12, the 17th PMOS MP17, The lining termination power voltage of the 18th PMOS MP18；

The grid leak end of the first PMOS MP1, the grid end of the second PMOS MP2, the grid end of the 3rd PMOS MP3, the 5th The grid end of PMOS MP5, the grid end of the 6th PMOS MP6 all connect current source forward end, current source negative end earthing potential；

The grid leak end of the first NMOS tube MN1, the grid end of the tenth NMOS tube MN10, the grid end of the 11st NMOS tube MN11, The grid end of 16 NMOS tube MN16, grid end all drain terminals with the second PMOS MP2 of the 17th NMOS tube MN17 are connected；

The grid leak end of the second NMOS tube MN2, the grid end of the 3rd NMOS tube MN3, the grid end of the 4th NMOS tube MN4, the 5th The grid of NMOS tube MN5, the grid end of the 8th NMOS tube MN8, the 9th NMOS tube MN9 grid end all with the 3rd PMOS MP3 Drain terminal be connected；

The grid leak end of the 4th PMOS MP4, the grid end of the 11st PMOS MP11, the grid end of the 12nd PMOS MP12, The grid end of the 17th PMOS MP17, grid end all drain terminals with the 3rd NMOS tube MN3 of the 18th PMOS MP18 are connected；

The grid end of the 6th NMOS tube MN6 and the grid end of the 7th PMOS MP7 are connected as an input, the 7th NMOS tube The grid end of MN7 and the grid end of the 8th PMOS MP8 are connected as another input, the source lining end of the 6th NMOS tube MN6, The source lining end of the 7th NMOS tube MN7 is connected also with drain terminal, the drain terminal of the 5th NMOS tube MN5 of the 4th NMOS tube MN4 respectively Bridged by the first resistance RSN；

The source lining end of the 7th PMOS MP7, the 8th PMOS MP8 source lining end respectively with the drain terminal of the 5th PMOS MP5, The drain terminal of the 6th PMOS MP6 is connected and passes through the second resistance RSP bridging；

The drain terminal of the 9th PMOS MP9, the source of the 11st PMOS MP11 are connected with the drain terminal of the 7th NMOS tube MN7； The drain terminal of the tenth PMOS MP10, the source of the 12nd PMOS MP12 are connected with the drain terminal of the 6th NMOS tube MN6；

The drain terminal of the 8th NMOS tube MN8, the source of the tenth NMOS tube MN10 are connected with the drain terminal of the 8th PMOS MP8； The drain terminal of the 9th NMOS tube MN9, the source of the 11st NMOS tube MN11 are connected with the drain terminal of the 7th PMOS MP7；

The grid end of the 9th PMOS MP9, the grid end of the tenth PMOS MP10, the 11st PMOS MP11 drain terminal all with The drain terminal of ten NMOS tube MN10 is connected；The drain terminal of the 12nd PMOS MP12, the 14th PMOS MP14 source lining end, The source of the 13rd NMOS tube MN13 all drain terminals with the 11st NMOS tube MN11 are connected；

12nd NMOS tube MN12 drain-gate end, the 13rd NMOS tube MN13 grid termination the 3rd resistance RBP are to power supply；13rd PMOS MP13 drain-gate end, the 14th PMOS MP14 grid termination the 4th resistance RBN to earth potential, the 12nd NMOS tube MN12 Source connect the 13rd PMOS MP13 source lining end；

The grid end of the 15th PMOS MP15, the grid end of the 16th PMOS MP16, the drain terminal of the 17th PMOS MP17 All drain terminals with the 13rd NMOS tube MN13 are connected；The grid end of the 14th NMOS tube MN14, the 15th NMOS tube MN15 Grid end, drain terminal all drain terminals with the 14th PMOS MP14 of the 16th NMOS tube MN16 are connected；

The drain terminal of the 15th PMOS MP15, the 16th PMOS MP16 drain terminal respectively with the 17th PMOS MP17 Source, the source of the 18th PMOS MP18 are connected；

The drain terminal of the 14th NMOS tube MN14, the 15th NMOS tube MN15 drain terminal respectively with the 16th NMOS tube MN16 Source, the source of the 17th NMOS tube MN17 are connected；The drain terminal of the 17th NMOS tube MN17 and the 18th PMOS MP18 Drain terminal be connected as outfan；

First NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 8th NMOS tube MN8, the 9th NMOS tube MN9, the 14th NMOS tube MN14, the source of the 15th NMOS tube MN15 Lining end and the tenth NMOS tube MN10, the 11st NMOS tube MN11, the 12nd NMOS tube MN12, the 13rd NMOS tube MN13, 16th NMOS tube MN16, the equal earthing potential of lining end of the 17th NMOS tube MN17.

Beneficial effects of the present invention is, has simple in construction, high linearity, low-power consumption, high PSRR, chip area little Etc. advantage.Compared with prior art, described low-power consumption high linearity Push-Pull trsanscondutance amplifier overcomes as improving the linearity And increase the problems such as the structure that additional circuit causes is complicated, power consumption is big, chip area is big, control ring meeting supply voltage switch Under the application conditions that error amplifier is required by road, it is achieved that the compact circuit design of high linearity low-power consumption.

Accompanying drawing explanation

Fig. 1 is the source resistance cross connection type negative feedback structure schematic diagram of linearisation mutual conductance；

Fig. 2 is the source resistance separate type negative feedback structure schematic diagram of linearisation mutual conductance；

Fig. 3 is the low-power consumption high linearity trsanscondutance amplifier integrated circuit structural representation of the present invention.

Detailed description of the invention

Below in conjunction with the accompanying drawings, technical scheme is described in detail:

The low-power consumption high linearity trsanscondutance amplifier of the present invention, recommends output including Rail-to-Rail input stage, Push-Pull Level and biasing circuit, wherein low-power consumption high linearity Push-Pull trsanscondutance amplifier uses source resistance cross connection type negative feedback structure (Fig. 1) realizing High Linear mutual conductance, source pressure drop will not raise compared with source resistance separate type negative feedback structure (Fig. 2), protects Demonstrate,prove the Double deference coefficient common mode electrical level wide ranges to pipe；Low-power consumption high linearity Push-Pull trsanscondutance amplifier simultaneously Using electric current transmission to amplify push-pull output stage makes output driving force big, it is possible to drive PWM controller to realize big duty cycle adjustment Scope；Low-power consumption high linearity Push-Pull trsanscondutance amplifier output stage uses low-power consumption biasing can reduce circuit power consumption, imitative True display 25 DEG C power consumption in typical case only has 708uw；The letter of low-power consumption high linearity Push-Pull transconductance amplifier circuit structure Single, domain compact design, use BCD350 technique chip area to only have 300 × 270um²；It addition, input and output level is all adopted Cascode(cascade) structure can obtain high PSRR, in emulation display 100kHz frequency range, PSRR is at 45db Above, system requirements is met.

As it is shown on figure 3, be the circuit structure of the low-power consumption high linearity trsanscondutance amplifier entirety of the present invention, described biasing circuit bag Include the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3 and current source；

Described Rail-to-Rail input stage include the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7, 8th PMOS MP8, the 9th PMOS MP9, the tenth PMOS MP10, the 11st PMOS MP11, the 12nd PMOS Pipe MP12, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS Pipe MN8, the 9th NMOS tube MN9, the tenth NMOS tube MN10, the 11st NMOS tube MN11, the first resistance RSN and second electricity Resistance RSP；

Described Push-Pull output stage includes the 13rd PMOS MP13, the 14th PMOS MP14, the 15th PMOS MP15, the 16th PMOS MP16, the 17th PMOS MP17, the 18th PMOS MP18, the 12nd NMOS tube MN12, 13rd NMOS tube MN13, the 14th NMOS tube MN14, the 15th NMOS tube MN15, the 16th NMOS tube MN16, 17 NMOS tube MN17, the 3rd resistance RBP and the 4th resistance RBN；Wherein,

First PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 9th PMOS MP9, the tenth PMOS MP10, the 15th PMOS MP15, the 16th PMOS MP16 source lining end and the 11st PMOS MP11, the 12nd PMOS MP12, the 17th PMOS MP17, The lining termination power voltage of the 18th PMOS MP18；

The grid leak end of the first PMOS MP1, the grid end of the second PMOS MP2, the grid end of the 3rd PMOS MP3, the 5th The grid end of PMOS MP5, the grid end of the 6th PMOS MP6 all connect current source forward end, current source negative end earthing potential；

The grid leak end of the first NMOS tube MN1, the grid end of the tenth NMOS tube MN10, the grid end of the 11st NMOS tube MN11, The grid end of 16 NMOS tube MN16, grid end all drain terminals with the second PMOS MP2 of the 17th NMOS tube MN17 are connected；

The grid leak end of the second NMOS tube MN2, the grid end of the 3rd NMOS tube MN3, the grid end of the 4th NMOS tube MN4, the 5th The grid of NMOS tube MN5, the grid end of the 8th NMOS tube MN8, the 9th NMOS tube MN9 grid end all with the 3rd PMOS MP3 Drain terminal be connected；

The grid leak end of the 4th PMOS MP4, the grid end of the 11st PMOS MP11, the grid end of the 12nd PMOS MP12, The grid end of the 17th PMOS MP17, grid end all drain terminals with the 3rd NMOS tube MN3 of the 18th PMOS MP18 are connected；

The grid end of the 6th NMOS tube MN6 and the grid end of the 7th PMOS MP7 are connected as an input, the 7th NMOS tube The grid end of MN7 and the grid end of the 8th PMOS MP8 are connected as another input, the source lining end of the 6th NMOS tube MN6, The source lining end of the 7th NMOS tube MN7 is connected also with drain terminal, the drain terminal of the 5th NMOS tube MN5 of the 4th NMOS tube MN4 respectively Bridged by the first resistance RSN；

The source lining end of the 7th PMOS MP7, the 8th PMOS MP8 source lining end respectively with the drain terminal of the 5th PMOS MP5, The drain terminal of the 6th PMOS MP6 is connected and passes through the second resistance RSP bridging；

The drain terminal of the 9th PMOS MP9, the source of the 11st PMOS MP11 are connected with the drain terminal of the 7th NMOS tube MN7； The drain terminal of the tenth PMOS MP10, the source of the 12nd PMOS MP12 are connected with the drain terminal of the 6th NMOS tube MN6；

The drain terminal of the 8th NMOS tube MN8, the source of the tenth NMOS tube MN10 are connected with the drain terminal of the 8th PMOS MP8； The drain terminal of the 9th NMOS tube MN9, the source of the 11st NMOS tube MN11 are connected with the drain terminal of the 7th PMOS MP7；

The grid end of the 9th PMOS MP9, the grid end of the tenth PMOS MP10, the 11st PMOS MP11 drain terminal all with The drain terminal of ten NMOS tube MN10 is connected；The drain terminal of the 12nd PMOS MP12, the 14th PMOS MP14 source lining end, The source of the 13rd NMOS tube MN13 all drain terminals with the 11st NMOS tube MN11 are connected；

12nd NMOS tube MN12 drain-gate end, the 13rd NMOS tube MN13 grid termination the 3rd resistance RBP are to power supply；13rd PMOS MP13 drain-gate end, the 14th PMOS MP14 grid termination the 4th resistance RBN to earth potential, the 12nd NMOS tube MN12 Source connect the 13rd PMOS MP13 source lining end；

The grid end of the 15th PMOS MP15, the grid end of the 16th PMOS MP16, the drain terminal of the 17th PMOS MP17 All drain terminals with the 13rd NMOS tube MN13 are connected；The grid end of the 14th NMOS tube MN14, the 15th NMOS tube MN15 Grid end, drain terminal all drain terminals with the 14th PMOS MP14 of the 16th NMOS tube MN16 are connected；

The drain terminal of the 15th PMOS MP15, the 16th PMOS MP16 drain terminal respectively with the 17th PMOS MP17 Source, the source of the 18th PMOS MP18 are connected；

The drain terminal of the 14th NMOS tube MN14, the 15th NMOS tube MN15 drain terminal respectively with the 16th NMOS tube MN16 Source, the source of the 17th NMOS tube MN17 are connected；The drain terminal of the 17th NMOS tube MN17 and the 18th PMOS MP18 Drain terminal be connected as outfan；

First NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 8th NMOS tube MN8, the 9th NMOS tube MN9, the 14th NMOS tube MN14, the source of the 15th NMOS tube MN15 Lining end and the tenth NMOS tube MN10, the 11st NMOS tube MN11, the 12nd NMOS tube MN12, the 13rd NMOS tube MN13, 16th NMOS tube MN16, the equal earthing potential of lining end of the 17th NMOS tube MN17

Wherein, described current source IB, NMOS tube MN1, MN2, MN3 and PMOS MP1, MP2, MP3, MP4 form biasing Circuit.Power vd D powers on, and can to produce bias voltage VB1, VB2, VB3, VB4 be Rail-to-Rail input stage and Push-Pull Output stage provides bias voltage.

Described NMOS tube MN4～MN11, PMOS MP5～MP12, resistance RSN, RSP form Rail-to-Rail input stage. Use the input of double folding differential pair can realize ICMR rail-to-rail, use source side resistance cross connection type negative feedback can realize linearisation Mutual conductance, uses cascade cascode structure to be possible not only to improve electric current transmission degree of accuracy and can also improve PSRR.

Described NMOS tube MN12～MN17, PMOS MP13～MP18, resistance RBN, RBP form Push-Pull output stage. Wherein MN12, MP13, RBP, RBN can be that MN13, MP14 provide low-power consumption biasing, by the regulation big I of RBP, RBN To realize the compromise of chip area and power consumption, NMOS tube MN14～MN17, PMOS MP15～MP18 current mirror structure can be real Existing Current amplifier, improves the ability driving load.

The operation principle of the present invention:

For biasing circuit, all pipes are set and are all operated in saturation region.In order to ensure that nmos differential is to MN6, MN7 and PMOS Differential pair MP7, MP8 have identical tail current source thus ensure to have identical mutual conductance, must arrange(W/L)_N2=(W/L)_N4=(W/L)_N5；In order to ensure that cascade pipe biases Suitable so that swing range maximizes, must (W/L) be set_N1It is about (W/L)_N2'sIn order to ensure the accurate of image current Property, the ditch length of mirror image pipe must be arranged bigger to reduce the impact of channel-length modulation.

For Rail-to-Rail input stage circuit, all pipe works are set in saturation region.Nmos differential is to realizing altogether Mould input range (V_GSN6,7+V_DSATN4,5)～VDD, PMOS differential pair can realize common-mode input range VSS～(VDD-V_DSATP5,6-V_GS7,8), Double deference can be easily achieved common-mode input range rail-to-rail to structure, in order to make Double deference is bigger to common effect interval, uses resistance cross connection type structure (shown in Fig. 1) to realize linearisation mutual conductance, now Common effect interval is (V_GSN6,7+V_DSATN4,5)～(VDD-V_DSATP5,6-V_GS7,8), and use resistance separate type structure (Fig. 2 institute Show) common effect interval be (V_GSN6,7+V_DSATN4,5+V_RSN)～(VDD-V_DSATP5,6-V_GS7,8-V_RSP), it is evident that Fig. 1 institute Show that structure can obtain and bigger jointly act on interval；RSN=RSP=RS is set, then has:

$G_{\mathrm{mN}\mathrm{6,7}}=G_{\mathrm{mP}\mathrm{7,8}}\≈\frac{2}{\mathrm{RS}}---\left(3\right)$

Wherein G_mN6,7And G_mP7,8Equivalent transconductance and PMOS after expression nmos differential adds source negative feedback to MN6, MN7 respectively are poor Divide the equivalent transconductance after MP7, MP8 are added source negative feedback, g_mNi、r_dsNiRepresent the mutual conductance of i-th NMOS tube, drain-source respectively Resistance, g_mPi、r_dsPiRepresent the mutual conductance of i-th PMOS, drain-source resistance respectively.

Can be seen that by expression formula (3) mutual conductance of input difference pair is only determined by source bridging resistance, it is achieved that linearisation, domain The isolated resistance of upper employing and matching technique can make nmos differential to and PMOS differential pair mutual conductance more accurate, linearisation is more preferable.

For Push-Pull output-stage circuit, mainly realize electric current transmission and amplify, use current buffer and current mirror As structure for amplifying.The connection of MN12 diode, the connection of MP13 diode, RBN, RBP be current buffer metal-oxide-semiconductor MN13, MP14 provides low-power consumption biasing, and the resistance increasing RBN, RBP can reduce power consumption；The output of input stage is from MN13, MP14 Through the current mirror scaling electric current of structure for amplifying MN14～MN17 and MP15～MP18 after source input, drain terminal output；Big signal Time input stage exporting change Amplitude Ratio relatively big, MN13, MP14 can be made to have individual pipe to enter cut-off region, thus output is recommended in realization；

It can be seen that a kind of low-power consumption high linearity Push-Pull trsanscondutance amplifier simple in construction that the present invention proposes, only use 17 NMOS, 18 PMOS and 4 resistance, be highly suitable to be applied for field of switch power as voltage control loop core Error amplifier.

Claims (1)

1. a low-power consumption high linearity trsanscondutance amplifier, it is characterised in that the biasing circuit that includes being sequentially connected with, Rail-to-Rail input stage and Push-Pull output stage；Described biasing circuit is made up of image current telescope, for Rail-to-Rail input stage and Push-Pull output stage provide bias voltage；Described Rail-to-Rail input stage uses folding Stacked nmos differential to and PMOS differential pair realize common-mode input range rail-to-rail, and use source negative feedback realize linearisation across Lead；Described Push-Pull output stage uses low-power consumption biasing to realize low-power consumption and recommends output, and uses image current to amplify raising Output driving force；

Described biasing circuit includes the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3 and current source；

Described Rail-to-Rail input stage include the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7, 8th PMOS MP8, the 9th PMOS MP9, the tenth PMOS MP10, the 11st PMOS MP11, the 12nd PMOS Pipe MP12, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS Pipe MN8, the 9th NMOS tube MN9, the tenth NMOS tube MN10, the 11st NMOS tube MN11, the first resistance RSN and second electricity Resistance RSP；

Described Push-Pull output stage includes the 13rd PMOS MP13, the 14th PMOS MP14, the 15th PMOS MP15, the 16th PMOS MP16, the 17th PMOS MP17, the 18th PMOS MP18, the 12nd NMOS tube MN12, 13rd NMOS tube MN13, the 14th NMOS tube MN14, the 15th NMOS tube MN15, the 16th NMOS tube MN16, 17 NMOS tube MN17, the 3rd resistance RBP and the 4th resistance RBN；Wherein,

First PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 9th PMOS MP9, the tenth PMOS MP10, the 15th PMOS MP15, the 16th PMOS MP16 source lining end and the 11st PMOS MP11, the 12nd PMOS MP12, the 17th PMOS MP17, The lining termination power voltage of the 18th PMOS MP18；

The grid leak end of the first PMOS MP1, the grid end of the second PMOS MP2, the grid end of the 3rd PMOS MP3, the 5th The grid end of PMOS MP5, the grid end of the 6th PMOS MP6 all connect current source forward end, current source negative end earthing potential；

The grid leak end of the first NMOS tube MN1, the grid end of the tenth NMOS tube MN10, the grid end of the 11st NMOS tube MN11, The grid end of 16 NMOS tube MN16, grid end all drain terminals with the second PMOS MP2 of the 17th NMOS tube MN17 are connected；

The grid leak end of the second NMOS tube MN2, the grid end of the 3rd NMOS tube MN3, the grid end of the 4th NMOS tube MN4, the 5th The grid of NMOS tube MN5, the grid end of the 8th NMOS tube MN8, the 9th NMOS tube MN9 grid end all with the 3rd PMOS MP3 Drain terminal be connected；

The grid leak end of the 4th PMOS MP4, the grid end of the 11st PMOS MP11, the grid end of the 12nd PMOS MP12, The grid end of the 17th PMOS MP17, grid end all drain terminals with the 3rd NMOS tube MN3 of the 18th PMOS MP18 are connected；

The grid end of the 6th NMOS tube MN6 and the grid end of the 7th PMOS MP7 are connected as an input, the 7th NMOS tube The grid end of MN7 and the grid end of the 8th PMOS MP8 are connected as another input, the source lining end of the 6th NMOS tube MN6, The source lining end of the 7th NMOS tube MN7 is connected also with drain terminal, the drain terminal of the 5th NMOS tube MN5 of the 4th NMOS tube MN4 respectively Bridged by the first resistance RSN；

The source lining end of the 7th PMOS MP7, the 8th PMOS MP8 source lining end respectively with the drain terminal of the 5th PMOS MP5, The drain terminal of the 6th PMOS MP6 is connected and passes through the second resistance RSP bridging；

The drain terminal of the 9th PMOS MP9, the source of the 11st PMOS MP11 are connected with the drain terminal of the 7th NMOS tube MN7； The drain terminal of the tenth PMOS MP10, the source of the 12nd PMOS MP12 are connected with the drain terminal of the 6th NMOS tube MN6；

The drain terminal of the 8th NMOS tube MN8, the source of the tenth NMOS tube MN10 are connected with the drain terminal of the 8th PMOS MP8； The drain terminal of the 9th NMOS tube MN9, the source of the 11st NMOS tube MN11 are connected with the drain terminal of the 7th PMOS MP7；

The grid end of the 9th PMOS MP9, the grid end of the tenth PMOS MP10, the 11st PMOS MP11 drain terminal all with The drain terminal of ten NMOS tube MN10 is connected；The drain terminal of the 12nd PMOS MP12, the 14th PMOS MP14 source lining end, The source of the 13rd NMOS tube MN13 all drain terminals with the 11st NMOS tube MN11 are connected；

12nd NMOS tube MN12 drain-gate end, the 13rd NMOS tube MN13 grid termination the 3rd resistance RBP are to power supply；13rd PMOS MP13 drain-gate end, the 14th PMOS MP14 grid termination the 4th resistance RBN to earth potential, the 12nd NMOS tube MN12 Source connect the 13rd PMOS MP13 source lining end；

The grid end of the 15th PMOS MP15, the grid end of the 16th PMOS MP16, the drain terminal of the 17th PMOS MP17 All drain terminals with the 13rd NMOS tube MN13 are connected；The grid end of the 14th NMOS tube MN14, the 15th NMOS tube MN15 Grid end, drain terminal all drain terminals with the 14th PMOS MP14 of the 16th NMOS tube MN16 are connected；

The drain terminal of the 15th PMOS MP15, the 16th PMOS MP16 drain terminal respectively with the 17th PMOS MP17 Source, the source of the 18th PMOS MP18 are connected；

The drain terminal of the 14th NMOS tube MN14, the 15th NMOS tube MN15 drain terminal respectively with the 16th NMOS tube MN16 Source, the source of the 17th NMOS tube MN17 are connected；The drain terminal of the 17th NMOS tube MN17 and the 18th PMOS MP18 Drain terminal be connected as outfan；

First NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 8th NMOS tube MN8, the 9th NMOS tube MN9, the 14th NMOS tube MN14, the source of the 15th NMOS tube MN15 Lining end and the tenth NMOS tube MN10, the 11st NMOS tube MN11, the 12nd NMOS tube MN12, the 13rd NMOS tube MN13, 16th NMOS tube MN16, the equal earthing potential of lining end of the 17th NMOS tube MN17.