CN105958948A - Low-power-consumption wide-range operational transconductance amplifier - Google Patents

Low-power-consumption wide-range operational transconductance amplifier Download PDF

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Publication number
CN105958948A
CN105958948A CN201610265136.4A CN201610265136A CN105958948A CN 105958948 A CN105958948 A CN 105958948A CN 201610265136 A CN201610265136 A CN 201610265136A CN 105958948 A CN105958948 A CN 105958948A
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China
Prior art keywords
transistor
nmos pass
pass transistor
pmos transistor
pmos
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CN201610265136.4A
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Chinese (zh)
Inventor
李娅妮
汤子月
朱樟明
杨银堂
王旭
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Xidian University
Kunshan Innovation Institute of Xidian University
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Xidian University
Kunshan Innovation Institute of Xidian University
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Priority to CN201610265136.4A priority Critical patent/CN105958948A/en
Publication of CN105958948A publication Critical patent/CN105958948A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H03F1/48—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers
    • H03F1/483—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/331—Sigma delta modulation being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21148—An output signal of a power amplifier being controlled by controlling current signal, e.g. by controlled current mirror

Abstract

The invention discloses a low-power-consumption wide-range operational transconductance amplifier which comprises a first stage of differential input stage, a second stage of differential input stage, a gain stage, an output stage and a self-biased circuit. An input signal is input into an input end of the first stage of differential input stage; a bias voltage vb3 loaded to the first stage of differential input stage is generated by the self-biased circuit; an output end of the first stage of differential input stage is connected to an input end of the second stage of differential input stage; bias voltages vb1 and vb2 required by the second stage of differential input stage are generated by the self-biased circuit; an output end of the second stage of differential input stage is connected to an input end of the gain stage; and an output end of the gain stage is connected to an output amplifier in the output stage and a compensation and overcurrent protection circuit. The low-power-consumption wide-range operational transconductance amplifier has the beneficial effects that 1, the low-power-consumption wide-range operational transconductance amplifier has lower power consumption; 2, the low-power-consumption wide-range operational transconductance amplifier has a wider input and output range; and 3, the low-power-consumption wide-range operational transconductance amplifier has a higher gain bandwidth.

Description

A kind of low-power consumption width scope operational transconductance amplifier
Technical field
The present invention relates to a kind of multistage operational transconductance amplifier, be specifically related to a kind of low-power consumption width model The multistage operational transconductance amplifier enclosed, belongs to electroporation field.
Background technology
Semiconductor technology characteristic size and the continuous progress of integrated level, for portable medical product Exploitation provides reliable technical support, thus has promoted small size, low cost, man-machine interaction Friendly interface, can smoothly complete some daily monitoring demand portable ecg monitor device send out Exhibition, can carry out good data acquisition to the vital sign needing monitoring, store, send and connect Receive, and user is made feedback.Wherein, Σ Δ ADC uses over-sampling, noise shaping and company The technology such as continuous time loop filtering, can realize high-resolution and the sampling on a large scale of 8～24 Rate, has the advantages such as high accuracy, low-power consumption, high linearity and high integration, is that high accuracy should With field, particularly one of the important technical in biopotential monitoring field.
The range of monitor and application mode propose low-voltage and low-power dissipation to circuit and want Ask.Low supply voltage can reduce systematic function, including the reduction of operating current, operating rate Decline, dynamic range and the reduction etc. of noise margin, precision and power consumption to Σ Δ ADC propose Higher requirement, especially in the problems such as frequency alias, noise shaping and quiescent dissipation.For Reduce the power consumption of Σ Δ ADC, constantly have new design theory and implementation method to occur.The most several Nian Lai, the representative technology effectively reducing Σ Δ ADC overall power or structure have: new The coarse-fine Sampling techniques of type, DT-sigma Delta modulator structure, MASH structure and split time coding Device, high-order digit filtering technique etc..
One complete over-sampling and noise shaping procedure include: anti-aliasing filter, sample and protect Hold, quantify, down-sampled digital filtering, its nucleus module includes Deltasigma modulator and digital filtering Device.As it is shown in figure 1, the structure of a single order Deltasigma modulator include an integrator, one The ADC of one and the DAC composition of, input signal is changed through DAC with output signal After signal subtraction, after integrated device integration enter quantizer.
In integrating circuit, the such as gain, bandwidth of the performance of amplifier, noise, output area etc. refer to Mark directly affects the performance of ADC: amplifier gain deficiency can reduce integrator gain and Introducing integration leaks, and reduces the output accuracy of residue-gain-circuit；Amplifier is in output voltage swing Nonlinear gain can draw distortion；Slew Rate and unity gain bandwidth are the important fingers that amplifier sets up behavior Mark, requires in high-precision applications that amplifier has and the fastest sets up behavior, in Slew Rate restricted area, fortune Put and be output as inelastic region；In Bandwidth-Constrained district, amplifier is linear；The limited band of amplifier Width can produce incomplete foundation, causes the Transfer Error of electric charge；The Slew Rate of amplifier is big not, The most non-linear foundation can cause harmonic distortion.Therefore, amplifier high-gain to be met, wide output pendulum The requirement such as width, high gain-bandwidth, time of setting up are short.
Switched-capacitor circuit refers to comprise the circuit of electric capacity, switch and operational amplifier, its structure As shown in Figure 2.The application scenario of switched capacitor amplifier is quite varied, is commonly used to highly integrated The mixed signal of degree processes in circuit.Some more basic modular circuits, such as: integrator, In-phase amplifier, comparator, sampling hold circuit, residue-gain-circuit etc. are all switching capacities The application of amplifier, these basic circuits can construct more complicated circuit, as wave filter, Analog-digital converters etc., wherein, amplifier is nucleus module, determines the performance of switched-capacitor circuit. But the threshold voltage of MOSFET limits amplifier application in a low pressure environment, its power consumption, The performances such as input/output bound, gain, arithmetic speed, operational precision are all restricted.Therefore The switched capacitor amplifier how designing high-gain width scope under the requirement of low-voltage and low-power dissipation shows Must be even more important.
Summary of the invention
It is an object of the invention to provide a kind of low-power consumption width being applicable to low pressure Σ Δ adc circuit Scope operational transconductance amplifier, it can not only effectively reduce running voltage thus reduce power consumption, And it is capable of bigger input/output bound.
In order to realize above-mentioned target, the present invention adopts the following technical scheme that:
A kind of low-power consumption width scope operational transconductance amplifier, it is characterised in that including: difference is defeated Entering level, gain stage, output stage and auto bias circuit, wherein, aforementioned differential input stage is by One-level differential input stage and second level differential input stage composition, aforementioned output stage is by out amplifier With compensate and current foldback circuit composition, aforementioned auto bias circuit can produce vb1, vb2, Vb3 tri-bias,
The electrical connection of whole circuit is: the input of first order differential input stage accesses input Signal, the bias voltage vb3 of its load is produced by auto bias circuit, first order differential input stage Outfan be connected to the input of second level differential input stage, second level differential input stage needed for Bias voltage vb1 and vb2 produced by auto bias circuit, the output of second level differential input stage End is connected to the input of gain stage, and the output that the outfan of gain stage is connected in output stage is put On big device and compensation and current foldback circuit.
Aforesaid low-power consumption width scope operational transconductance amplifier, it is characterised in that at Differential Input In Ji, aforementioned first order differential input stage is the source follower structure of cascade, and it is by NMOS Transistor MN1, nmos pass transistor MN2, nmos pass transistor MN3, NMOS crystalline substance Body pipe MN4, nmos pass transistor MN5, nmos pass transistor MN6 and resistance R1, electricity Resistance R2, resistance R3, resistance R4 composition:
The substrate of nmos pass transistor MN1, the substrate of nmos pass transistor MN2, NMOS The substrate of transistor MN3, the substrate of nmos pass transistor MN4, nmos pass transistor MN5 Substrate and the substrate of nmos pass transistor MN6 be all connected to GND, nmos pass transistor The drain terminal of MN1 is commonly connected to supply voltage VDD with the drain terminal of nmos pass transistor MN3, The source of nmos pass transistor MN1 is connected with the drain terminal of nmos pass transistor MN2, NMOS The grid end of transistor MN1 is connected resistance R1 jointly with the grid end of nmos pass transistor MN2 One end, the other end of resistance R1 is the inverting input vinn, NMOS of operational amplifier The source of transistor MN2 is connected with one end of resistance R3, and the other end of resistance R3 connects The drain terminal of nmos pass transistor MN5, the source of nmos pass transistor MN3 is brilliant with NMOS The drain terminal of body pipe MN4 is connected, the grid end of nmos pass transistor MN3 and nmos pass transistor The grid end of MN4 connects one end of resistance R2 jointly, and the other end of resistance R2 is operation amplifier One end of the in-phase input end vinp of device, the source of nmos pass transistor MN4 and resistance R4 Being connected, the other end of resistance R4 connects the drain terminal of nmos pass transistor MN6, and NMOS is brilliant The source of body pipe MN5 and the source of nmos pass transistor MN6 are commonly connected to GND, The grid end of nmos pass transistor MN5 is commonly connected to the grid end of nmos pass transistor MN6 Auto bias circuit produce bias vb3, wherein, the source of nmos pass transistor MN2 and The source of nmos pass transistor MN4 is two outfans of first order differential input stage.
Aforesaid low-power consumption width scope operational transconductance amplifier, it is characterised in that at Differential Input In Ji, aforementioned second level differential input stage is common-source stage amplifier architecture, and it is brilliant by PMOS Body pipe MP1, PMOS transistor MP2, PMOS transistor MP3, nmos pass transistor MN9 and nmos pass transistor MN10 composition:
The source of PMOS transistor MP1 is connected jointly with the source of PMOS transistor MP2 To the drain terminal of PMOS transistor MP3, the source of PMOS transistor MP3 and PMOS The substrate of transistor MP3 is all connected to supply voltage VDD, PMOS transistor MP3 Grid end is connected to the bias vb1 that auto bias circuit produces, the grid end of PMOS transistor MP1 It is commonly connected to GND, PMOS transistor MP1 with the grid end of PMOS transistor MP2 Drain terminal be connected with the drain terminal of nmos pass transistor MN9, the leakage of PMOS transistor MP2 End is connected with the drain terminal of nmos pass transistor MN10, the source of nmos pass transistor MN9, The substrate of nmos pass transistor MN9, the source of nmos pass transistor MN10 and NMOS The substrate of transistor MN10 be all connected to GND, nmos pass transistor MN9 grid end and The grid end of nmos pass transistor MN10 is connected to the bias vb2 that auto bias circuit produces, The substrate of PMOS transistor MP1 and the substrate of PMOS transistor MP2 are second level difference Two inputs of input stage, are connected with two outfans of first order differential input stage respectively, The drain terminal of PMOS transistor MP1 and the drain terminal of PMOS transistor MP2 are second level difference Two outfans of input stage.
Aforesaid low-power consumption width scope operational transconductance amplifier, it is characterised in that aforesaid gains level By PMOS transistor MP4, PMOS transistor MP5, nmos pass transistor MN7 and Nmos pass transistor MN8 forms:
The source of PMOS transistor MP4, the substrate of PMOS transistor MP4, PMOS The source of transistor MP5 and the substrate of PMOS transistor MP5 are commonly connected to supply voltage VDD, the grid end of PMOS transistor MP4 is connected with the grid end of PMOS transistor MP5 And it is commonly connected to the drain terminal of PMOS transistor MP4, the drain terminal of PMOS transistor MP4 Being connected to the drain terminal of nmos pass transistor MN7, the drain terminal of PMOS transistor MP5 connects To the drain terminal of nmos pass transistor MN8, the substrate of nmos pass transistor MN7 and NMOS The substrate of transistor MN8 all connects GND, the grid of nmos pass transistor MN7 and NMOS The grid of transistor MN8 is commonly connected to supply voltage VDD, nmos pass transistor MN7 Source and source is gain stage two inputs of nmos pass transistor MN8 respectively with Two outfans of two grades of differential input stages are connected, and the drain terminal of nmos pass transistor MN8 is for increasing The outfan of benefit level.
Aforesaid low-power consumption width scope operational transconductance amplifier, it is characterised in that in output stage In, aforementioned out amplifier by PMOS transistor MP8, nmos pass transistor MN15 and Resistance R7 forms:
The source of PMOS transistor MP8 and substrate connect supply voltage VDD, PMOS crystal One end of the drain terminal connecting resistance R7 of pipe MP8, the other end of resistance R7 is output node VOUT, the outfan of the grid termination gain stage of PMOS transistor MP8, NMOS crystal The source of pipe MN15 and substrate meet GND, and the drain terminal of nmos pass transistor MN15 is output The grid end of node VOUT, nmos pass transistor MN15 is connected to bias Va, aforementioned bias Va is by compensating and current foldback circuit generation.
Aforesaid low-power consumption width scope operational transconductance amplifier, it is characterised in that in output stage In, aforementioned backoff and current foldback circuit are by compensating electric capacity C1, compensating electric capacity C2, NMOS Transistor MN11, nmos pass transistor MN12, nmos pass transistor MN13, NMOS Transistor MN14, nmos pass transistor MN15, PMOS transistor MP6, PMOS Transistor MP7 and resistance R5 and resistance R6 composition:
Compensate electric capacity C1 to be connected between gain stage output and output node VOUT, complete close Strangle and compensate；
PMOS transistor MP6, the source of PMOS transistor MP7 and substrate terminal all connect To supply voltage VDD, the grid end of PMOS transistor MP6 is connected to the outfan of gain stage, The drain terminal of PMOS transistor MP6 connects grid end and the resistance of nmos pass transistor MN12 One end of R5, the other end of resistance R5 connects the drain terminal of nmos pass transistor MN12, The source of nmos pass transistor MN12 connects drain terminal and the grid end of nmos pass transistor MN11 And the grid end of nmos pass transistor MN13, the substrate terminal of nmos pass transistor MN12, The source of nmos pass transistor MN11 and substrate terminal are all connected to GND, PMOS transistor The grid end of MP7 connects the bias voltage vb1 that auto bias circuit produces, PMOS transistor MP7 Drain terminal connect the grid end of nmos pass transistor MN14 and one end of resistance R6, resistance R6 The other end connect nmos pass transistor MN14 drain terminal, and for output stage load NMOS Transistor MN15 provides bias voltage va, and the source of nmos pass transistor MN14 is connected to The drain terminal of nmos pass transistor MN13, the substrate terminal of nmos pass transistor MN14, NMOS Source and the substrate terminal of transistor MN13 are all connected to GND.
Aforesaid low-power consumption width scope operational transconductance amplifier, it is characterised in that aforementioned self-bias Circuits provides bias voltage for amplifiers at different levels, and it is by PMOS transistor M1, PMOS Transistor M2, PMOS transistor M3, PMOS transistor M4, PMOS transistor M7, PMOS transistor M8, nmos pass transistor M5 and nmos pass transistor M6 group Become:
PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, PMOS The substrate of transistor M4, PMOS transistor M7 and PMOS transistor M8 is all connected to Supply voltage VDD, the substrate of nmos pass transistor M5 and nmos pass transistor M6 all connects Receive GND, the source of PMOS transistor M1, the source of PMOS transistor M4, The source of PMOS transistor M7 is connected to supply voltage VDD, PMOS transistor M1 Drain terminal be connected with the source of PMOS transistor M2, the grid end of PMOS transistor M1 with The grid end of PMOS transistor M4, the drain terminal of PMOS transistor M2, PMOS transistor The source of M3 is connected, and common generation biases vb1, the grid end of PMOS transistor M2 and PMOS The grid end of transistor M7, the grid end of PMOS transistor M8, PMOS transistor M8 Drain terminal, the drain terminal of M6 are connected, and common generation biases vb3, the grid of PMOS transistor M3 End is connected with drain terminal, the drain terminal of the drain terminal of PMOS transistor M4 and nmos pass transistor M5, The grid end of nmos pass transistor M5 is connected with the grid end of nmos pass transistor M6, jointly produces Raw bias vb2.
The invention have benefit that:
(1) there is lower power consumption
Second level differential input stage have employed the PMOS of bulk driven, owing to input signal loads Conducting channel has been formed under substrate terminal, the grid of single tube bulk driven PMOS transistor, Therefore between lining-source, have only to the least supply voltage just can realize the tune to leakage current System, reduces the restriction of threshold voltage, can effectively reduce the supply voltage needed for circuit, from And reduce the power consumption of integrated circuit.
(2) there is broader input/output bound
The output voltage range of amplifier is closely related with the harmonic distortion performance of system, i.e. SFDR Performance.When the output voltage swing of amplifier is by limited time, and this saturated meeting introduces pole in final parallel operation Big distortion, lost some status signals in other words.In order to make manipulator in certain amplifier Not lost condition signal under the conditions of output voltage swing, needs to use bi-directional scaling (scaling) skill Art.The amplitude of oscillation of amplifier is the highest, it is possible to use the least scale factor.As such, it is possible to reduce Feedback capacity, thus reduce the area of chip.Meanwhile, in amplifier transmission function, by feeding back The zero point that electric capacity causes can reduce its impact on the time of setting up at high frequency treatment.
First order differential input stage have employed the source follower structure of cascade, drives compensate for substrate The shortcoming that dynamic pipe input mutual conductance is low, increases common-mode input range simultaneously；The grid of PMOS is even Connect minimum level and ensure that enough common-mode input ranges；Output stage is that PMOS input pipe is total to Gate junction structure, improves system gain and output common mode scope.
(3) there is higher gain bandwidth
In SC circuit, the finite bandwidth of amplifier produces incomplete foundation, causes turning of electric charge Shift error.For common SC manipulator, amplifier must reach to refer within half clock cycle Fixed precision.In order to make amplifier use in feedback loop, it is necessary to the frequency response of design amplifier connects Nearly first order pole frequency characteristic.Therefore, in addition to a low frequency dominant pole, remaining pole and zero It is preferably disposed at upper frequency.
Miller compensates electric capacity C1 and is connected, by circuit with gain stage and the output stage of operational amplifier Dominant pole to low frequency direction elapse, by the output limit of circuit to high frequency direction elapse, to carry The gain bandwidth of high operational amplifier；In nmos pass transistor MN13 and current foldback circuit Nmos pass transistor MN12 be connected, constitute current-mirror structure, electric capacity C2 connects NMOS The grid of transistor MN15 and drain electrode, compensated the zero of electric capacity C1 introducing to eliminate by miller Point, improves the stability of system.
Accompanying drawing explanation
Fig. 1 is single order Deltasigma modulator structured flowchart；
Fig. 2 is switched-capacitor integrator structure chart；
Fig. 3 (a) is the design principle figure of low-power consumption width scope operational transconductance amplifier of the present invention；
Fig. 3 (b) is the circuit diagram of low-power consumption width scope operational transconductance amplifier of the present invention；
Fig. 4 is the circuit diagram of first order differential input stage；
Fig. 5 is the circuit diagram of second level differential input stage；
Fig. 6 is the circuit diagram of gain stage；
Fig. 7 is the circuit diagram of output stage；
Fig. 8 is the circuit diagram of PMOS bulk driven pipe in the present invention；
Fig. 9 is the circuit diagram of cascade source follower input pipe；
Figure 10 is the circuit diagram of auto bias circuit.
Detailed description of the invention
The operational transconductance amplifier of the present invention is the multistage amplifier having used bulk driven technology, Its running voltage being possible not only to effectively reduce circuit thus reduce power consumption, and can expand defeated Go out scope and gain bandwidth.
Below in conjunction with the drawings and specific embodiments, the present invention made concrete introduction.
With reference to Fig. 3 (a) and Fig. 3 (b), the low-power consumption width scope operational transconductance of the present invention amplifies Device includes: differential input stage, gain stage, output stage and auto bias circuit.Wherein, difference is defeated Entering level to be made up of first order differential input stage and second level differential input stage, output stage is put by output Big device and compensation and current foldback circuit composition, auto bias circuit can produce vb1, vb2, Vb3 tri-bias.
The electrical connection of whole operational transconductance amplifier circuit is: first order differential input stage Input accesses input signal, and the bias voltage vb3 of its load is produced by auto bias circuit, the The outfan of one-level differential input stage is connected to the input of second level differential input stage, the second level Bias voltage vb1 and vb2 needed for differential input stage is produced by auto bias circuit, and first is differential Point input stage and second level differential input stage have collectively constituted differential input stage, this differential input stage Both there is higher input impedance, bigger common-mode input range, reduced again supply voltage, Thus having reached to reduce the purpose of power consumption, the outfan of second level differential input stage is connected to gain The input of level, gain stage can improve the gain of integrated circuit, and the outfan of gain stage is connected to On out amplifier in output stage and compensation and current foldback circuit, compensate and overcurrent protection electricity Road can make whole operational transconductance amplifier reach the requirement of high gain-bandwidth, meanwhile, at electric current Current path is provided time too high, plays the effect of protection circuit.
The structure of differential input stage, gain stage, output stage and auto bias circuit is described in detail below.
1, differential input stage
Differential input stage is made up of first order differential input stage and second level differential input stage.
With reference to Fig. 3 b and Fig. 4, first order differential input stage is the source follower structure of cascade, Its by nmos pass transistor MN1, nmos pass transistor MN2, nmos pass transistor MN3, Nmos pass transistor MN4, nmos pass transistor MN5, nmos pass transistor MN6 and electricity Resistance R1, resistance R2, resistance R3, resistance R4 composition.
In first order differential input stage, the electrical connection between each components and parts is: NMOS The substrate of transistor MN1, the substrate of nmos pass transistor MN2, nmos pass transistor MN3 Substrate, the substrate of nmos pass transistor MN4, the substrate of nmos pass transistor MN5 and The substrate of nmos pass transistor MN6 is all connected to GND, the leakage of nmos pass transistor MN1 End is commonly connected to supply voltage VDD, NMOS with the drain terminal of nmos pass transistor MN3 The source of transistor MN1 is connected with the drain terminal of nmos pass transistor MN2, NMOS crystal The grid end of pipe MN1 is connected the one of resistance R1 jointly with the grid end of nmos pass transistor MN2 End, the other end of resistance R1 is inverting input vinn, the NMOS crystal of operational amplifier The source of pipe MN2 is connected with one end of resistance R3, and the other end of resistance R3 connects NMOS The drain terminal of transistor MN5, the source of nmos pass transistor MN3 and nmos pass transistor The drain terminal of MN4 is connected, the grid end of nmos pass transistor MN3 and nmos pass transistor MN4 Grid end jointly connect one end of resistance R2, the other end of resistance R2 is operational amplifier In-phase input end vinp, the source of nmos pass transistor MN4 is connected with one end of resistance R4, The other end of resistance R4 connects the drain terminal of nmos pass transistor MN6, nmos pass transistor The source of MN5 is commonly connected to GND, NMOS with the source of nmos pass transistor MN6 The grid end of transistor MN5 and the grid end of nmos pass transistor MN6 are commonly connected to automatic biasing The bias vb3 that circuit produces, wherein, the source of nmos pass transistor MN2 and NMOS are brilliant Source is first order differential input stage two outfans of body pipe MN4.
First order differential input stage have employed the source follower structure of cascade, nmos pass transistor MN1 and nmos pass transistor MN2 cascade, the grid end of nmos pass transistor MN1 and NMOS The grid end of transistor MN2 is inverting input, connects anti-phase input level；Nmos pass transistor MN3 and nmos pass transistor MN4 cascade, the grid end of nmos pass transistor MN3 and NMOS The grid end of transistor MN4 is in-phase input end, connects homophase incoming level；Nmos pass transistor The source of MN2 and the source of nmos pass transistor MN4 are as first order differential input stage Outfan.
Nmos pass transistor MN1 and nmos pass transistor MN2 cascade, nmos pass transistor MN3 and nmos pass transistor MN4 cascade, composition Differential Input, to pipe, can improve fortune The input mutual conductance put, strengthens load capacity, can also improve the input range of common mode electrical level simultaneously.
With reference to Fig. 3 b and Fig. 5, second level differential input stage is common-source stage amplifier architecture, its By PMOS transistor MP1, PMOS transistor MP2, PMOS transistor MP3, NMOS Transistor MN9 and nmos pass transistor MN10 composition.
In the differential input stage of the second level, the electrical connection between each components and parts is: PMOS The source of transistor MP1 and the source of PMOS transistor MP2 are commonly connected to PMOS The drain terminal of transistor MP3, the source of PMOS transistor MP3 and PMOS transistor MP3 Substrate be all connected to supply voltage VDD, the grid end of PMOS transistor MP3 be connected to from The bias vb1 that biasing circuit produces, the grid end of PMOS transistor MP1 and PMOS crystal The grid end of pipe MP2 is commonly connected to GND (to ensure to exist in MOSFET conducting channel), The drain terminal of PMOS transistor MP1 is connected with the drain terminal of nmos pass transistor MN9, PMOS The drain terminal of transistor MP2 is connected with the drain terminal of nmos pass transistor MN10, NMOS crystal The source of pipe MN9, the substrate of nmos pass transistor MN9, nmos pass transistor MN10 Source and the substrate of nmos pass transistor MN10 be all connected to GND, nmos pass transistor The grid end of MN9 and the grid end of nmos pass transistor MN10 are connected to what auto bias circuit produced Bias vb2, the substrate of PMOS transistor MP1 and the substrate of PMOS transistor MP2 are Two inputs of second level differential input stage, defeated with the two of first order differential input stage respectively Going out end to be connected, the drain terminal of PMOS transistor MP1 and the drain terminal of PMOS transistor MP2 are Two outfans of second level differential input stage.
PMOS transistor MP1 and PMOS transistor MP2 constitute Differential Input to pipe, and Connect into common-source stage structure.
In the present invention, the circuit diagram of PMOS bulk driven pipe is as shown in Figure 8.
See Fig. 8, when input signal VBS added by the Bulk of bottom changes, substrate terminal Depletion layer thickness between Bulk and conducting channel changes, thus changes channel inversion The thickness of layer, is equivalent to channel current and is controlled by substrate and source electrode institute plus signal.Therefore, Single tube bulk driven PMOS transistor can be equivalent to a knot with relatively high input impedance Type field-effect transistor.
Second level differential input stage have employed the PMOS of bulk driven, owing to input signal loads Conducting channel has been formed under substrate terminal, the grid of single tube bulk driven PMOS transistor, Therefore between lining-source, have only to the least supply voltage just can realize the modulation to leakage current (being similar to depletion device), reduces the restriction of threshold voltage.
With reference to Fig. 5, bulk driven PMOS Differential Input to pipe PMOS transistor MP1 and PMOS transistor MP2, as the second level differential input stage of operational amplifier, makes PMOS Transistor MP1 and PMOS transistor MP2 are mated completely, then second level differential input stage increases Benefit AV,bdFor:
A V , b d = g m b , P 1 ( g m , P 1 + g m b , P 1 + 1 / r o , P 1 )
Output resistance is:
R 0 , b d = 1 g m , P 1 / / 1 g m b , P 1 / / r o , P 1
Wherein, gm,P1、gmb,P1、ro,P1Be respectively PMOS transistor MP1 grid across Lead, substrate mutual conductance, output resistance.
The major defect of bulk driven PMOS is: input mutual conductance little, typically about grid drive across 1/4 to 1/5 led；Input capacitance is relatively big, result in the characteristic frequency f of MOSFETTReduce, Thus limit the maximum operating frequency of circuit；Due to bulk-driven MOS FET own gain Declining, equivalent input noise increases.
Fig. 9 is the circuit diagram of cascade source follower input pipe, and the source class that it illustrates cascade is followed Device is as the situation of first order differential input stage, and wherein, Vo1 is the output of this source class follower End, nmos pass transistor MN1 and nmos pass transistor MN2 cascade, first order difference is defeated Enter the gain A of levelVIt is represented by:
A V = r o , N 2 g m , N 2 ( g m , N 1 + g m b , N 1 + 1 / r o , N 1 ) + g m , N 1 ( g m , N 1 + g m b , N 1 + 1 / r o , N 1 ) ( g m , N 2 + g m b , N 2 + 1 / r o , N 2 )
The output resistance of first order differential input stage is represented by:
R 0 = 1 g m , N 1 / / 1 g m b , N 1 / / r o , N 1
Wherein, gm,N1、gmb,N1、ro,N1It is respectively the grid of nmos pass transistor MN1 Mutual conductance, substrate mutual conductance, output resistance, gm,N2、gmb,N2、ro,N2It is respectively NMOS The grid mutual conductance of transistor MN2, substrate mutual conductance, output resistance.
Compared with single-stage source class follower, after cascade, the gain of circuit is greatly improved, Output resistance keeps constant, thus compensate for the low increasing of bulk driven PMOS differential input stage Benefit shortcoming.
So, the differential input stage that the present invention relates to both had had higher input impedance, bigger Common-mode input range, reduce again supply voltage, thus reached to reduce the purpose of power consumption.
2, gain stage
Gain stage uses gate junction structure altogether, to improve the gain of amplifier, reduces input impedance.
With reference to Fig. 3 b and Fig. 6, gain stage is by PMOS transistor MP4, PMOS transistor MP5, nmos pass transistor MN7 and nmos pass transistor MN8 composition.
In gain stage, the electrical connection between each components and parts is: PMOS transistor MP4 Source, the substrate of PMOS transistor MP4, the source of PMOS transistor MP5 and The substrate of PMOS transistor MP5 is commonly connected to supply voltage VDD, PMOS transistor The grid end of MP4 is connected with the grid end of PMOS transistor MP5 and is commonly connected to PMOS The drain terminal of transistor MP4, the drain terminal of PMOS transistor MP4 is connected to NMOS crystal The drain terminal of pipe MN7, the drain terminal of PMOS transistor MP5 is connected to nmos pass transistor MN8 Drain terminal, the substrate of nmos pass transistor MN7 and the substrate of nmos pass transistor MN8 are all Connect the grid of GND, the grid of nmos pass transistor MN7 and nmos pass transistor MN8 Pole is commonly connected to supply voltage VDD, the source of nmos pass transistor MN7 and NMOS The source of transistor MN8 be gain stage two inputs respectively with second level differential input stage Two outfans be connected, the drain terminal of nmos pass transistor MN8 is the outfan of gain stage.
Because using PMOS transistor MP4 as the current source of nmos pass transistor MN7 Load, uses PMOS transistor MP5 negative as the current source of nmos pass transistor MN8 Carry, and realize the double-width grinding conversion to Single-end output with the form of current mirror, so the present invention The gain stage related to can be good at improving the gain of integrated circuit.
3, output stage
Output stage is made up of out amplifier and compensation and current foldback circuit.
With reference to Fig. 3 b and Fig. 7, out amplifier is brilliant by PMOS transistor MP8, NMOS Body pipe MN15 and resistance R7 composition.
In out amplifier, the electrical connection between each components and parts is: PMOS transistor The source of MP8 and substrate meet supply voltage VDD, and the drain terminal of PMOS transistor MP8 connects electricity One end of resistance R7, the other end of resistance R7 is output node VOUT, PMOS transistor The outfan of the grid termination gain stage of MP8, the source of nmos pass transistor MN15 and substrate Meeting GND, the drain terminal of nmos pass transistor MN15 is output node VOUT, and NMOS is brilliant The grid end of body pipe MN15 is connected to bias Va, and wherein, bias Va is by compensating and overcurrent protection Circuit produces (compensating and the drain voltage of nmos pass transistor MN14 in current foldback circuit).
With reference to Fig. 3 b and Fig. 7, compensate and current foldback circuit is by compensating electric capacity C1, compensating electricity Hold C2, nmos pass transistor MN11, nmos pass transistor MN12, nmos pass transistor MN13, nmos pass transistor MN14, nmos pass transistor MN15, PMOS transistor MP6, PMOS transistor MP7 and resistance R5 and resistance R6 composition.
In compensation and current foldback circuit, the electrical connection between each components and parts is:
(1) compensate electric capacity C1 to be connected between gain stage output and output node VOUT, complete Become miller compensation；
(2) compensate electric capacity C2, nmos pass transistor MN11, nmos pass transistor MN12, Nmos pass transistor MN13, nmos pass transistor MN14, nmos pass transistor MN15, PMOS transistor MP6 and PMOS transistor MP7 composition feedback control loop, wherein, compensate Electric capacity C2 is connected across between the drain terminal of nmos pass transistor MN15 and grid end, PMOS crystal Pipe MP6, the source of PMOS transistor MP7 and substrate terminal are all connected to supply voltage VDD, the grid end of PMOS transistor MP6 be connected to the outfan of gain stage (i.e. MP5 and The drain terminal of MN8), the drain terminal of PMOS transistor MP6 connects nmos pass transistor MN12 Grid end and one end of resistance R5, the other end of resistance R5 connects nmos pass transistor MN12 Drain terminal, the source of nmos pass transistor MN12 connects the leakage of nmos pass transistor MN11 The grid end of end and grid end and nmos pass transistor MN13 be (nmos pass transistor MN13's Grid end connects by the bias compensated in output stage and current foldback circuit produces, and forms current mirror), The substrate terminal of nmos pass transistor MN12, the source of nmos pass transistor MN11 and substrate End is all connected to GND, and the grid end of PMOS transistor MP7 connects what auto bias circuit produced Bias voltage vb1 (i.e. the grid end of NMOS tube M1 and M4), PMOS transistor MP7 Drain terminal connect the grid end of nmos pass transistor MN14 and one end of resistance R6, resistance R6 The other end connect nmos pass transistor MN14 drain terminal, and for output stage load NMOS Transistor MN15 provides bias voltage va, and the source of nmos pass transistor MN14 is connected to The drain terminal of nmos pass transistor MN13, the substrate terminal of nmos pass transistor MN14, NMOS Source and the substrate terminal of transistor MN13 are all connected to GND.
Visible, in above-mentioned compensation and current foldback circuit, compensation includes: miller compensation is with anti- Feedback compensates.Wherein, miller compensation realizes by compensating electric capacity C1；Feedback control loop is except permissible Realize feedback compensation, it is also possible to complete overcurrent protection function, resistance R5, PMOS transistor MP6, nmos pass transistor MN11, nmos pass transistor MN12 can be brilliant at PMOS The grid voltage of body pipe MP6 forms discharge path when exceeding certain value, thus plays protection circuit Function.
Miller compensation electric capacity C1 is connected to outfan and the operation amplifier of the gain stage of operational amplifier Between the output stage of device, constituting typical miller collocation structure, miller compensates and makes computing put The limit (dominant pole) of big device input stage and gain inter-stage moves to initial point, makes operational amplifier Output limit (secondary limit) move to the direction leaving initial point, increase the bandwidth of system.
Although miller compensates electric capacity C1 and adds the bandwidth of system, but draws at RHP simultaneously Having entered 1 zero point, this zero point slow down the decline of amplitude, thus makes the dominant pole of amplifier extrapolate, Greatly reduce the stability of system.
In order to eliminate the impact of zero point, use and compensate electric capacity C2, nmos pass transistor MN11-MN15, PMOS transistor MP6-MP8, resistance R5, R6, constitute feedback loop Road, eliminates and is compensated, by miller, the zero point that electric capacity C1 introduces, and improves the stability of system, its In, Vo is the outfan that operation amplifier is put.
After overcompensation, the gain of operational amplifier is represented by:
A V , O P = sC 1 + g m , P 8 + E ( g m , N 15 - sC 2 ) s ( C 1 + C 2 ) + g m , P 8 + 1 / r o , N 15 + 1 / r o , P 8
Wherein, s refers to the complex frequency on complex plane.
E = r o , N 13 g m , N 13 D ( 1 / r o , N 14 + g m , N 14 ) Ar o , N 12 g m , N 12 - B C A ( 1 + r o , N 12 g m , N 12 ) + C ( 1 / r o , N 11 + g m , N 11 )
A=1/ro,P6+1/ro,N11+gm,P6+(gm,N11+gmb,N11+1/ro,N11)(R5gm,P6+1/ro,P6) B=gm,P6[1+R5(gm,N11+gmb,N11+1/ro,N11)]
C=ro,N12(gm,P6+1/ro,P6)
D = 1 / r o , N 14 + 1 / R 6 + 1 R 6 + r o , P 7 [ ( g m , N 14 - 1 / R 6 ) r o , P 7 + ( g m , N 14 + 1 / r o , N 14 ) g m , N 13 ]
Wherein, gm,PiFor the grid mutual conductance of PMOS transistor MPi, ro,PiFor PMOS crystal The equivalent output resistance of pipe MPi, gm,NjFor the grid mutual conductance of nmos pass transistor MNj, ro,Nj For the equivalent output resistance of nmos pass transistor MNj, i and j is the sequence of respective transistor Number, gmb,N11For the substrate mutual conductance of nmos pass transistor MN11, when i.e. considering bulk effect Mutual conductance.
As long as making sC1-sC2E=0, can eliminate the zero point of RHP.Wherein, select to compensate It is little more than 10 times that the area ratio of electric capacity C2 compensates electric capacity C1, so can save chip area, Ensure that the limit by compensating electric capacity C2 introducing is little to amplifier performance impact simultaneously.
Output stage that is visible, that the present invention relates to, its simple in construction, PMOS transistor MP8 As input pipe, using common-source stage structure, input impedance is big, further increases operation amplifier The gain of device；Use nmos pass transistor MN15 as common-source stage active load, add Output common mode scope, thus increase the output voltage swing that amplifier is overall；Resistance R7 is connected to Between drain terminal and the drain terminal of nmos pass transistor MN15 of PMOS transistor MP8, adjustable Joint output electric current.
4, auto bias circuit
Auto bias circuit provides biasing for nmos pass transistor MN15.
With reference to Fig. 3 b and Figure 10, auto bias circuit provides bias voltage for amplifiers at different levels, its By PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, PMOS Transistor M4, PMOS transistor M7, PMOS transistor M8, nmos pass transistor M5 and nmos pass transistor M6 composition.
In auto bias circuit, the electrical connection between each components and parts is: PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, PMOS transistor M4, PMOS The substrate of transistor M7 and PMOS transistor M8 is all connected to supply voltage VDD, The substrate of nmos pass transistor M5 and nmos pass transistor M6 is all connected to GND, PMOS The source of transistor M1, the source of PMOS transistor M4, PMOS transistor M7 Source is connected to supply voltage VDD, the drain terminal of PMOS transistor M1 and PMOS crystal The source of pipe M2 is connected, the grid end of PMOS transistor M1 and PMOS transistor M4 Grid end, the drain terminal of PMOS transistor M2, the source of PMOS transistor M3 are connected, altogether With producing bias vb1, the grid end of PMOS transistor M2 and the grid of PMOS transistor M7 End, the grid end of PMOS transistor M8, the drain terminal of PMOS transistor M8, NMOS crystalline substance The drain terminal of body pipe M6 is connected, and common generation biases vb3, the grid end of PMOS transistor M3 It is connected with drain terminal, the drain terminal of the drain terminal of PMOS transistor M4 and nmos pass transistor M5, The grid end of nmos pass transistor M5 is connected with the grid end of nmos pass transistor M6, jointly produces Raw bias vb2.
The metal-oxide-semiconductor dividing potential drop that auto bias circuit connects mainly by diode, produces amplifier circuit Bias voltage required for middle load pipe, Vb1 is by PMOS transistor M1, PMOS crystal Pipe M2, PMOS transistor M3 dividing potential drop produce, wherein, and PMOS transistor M2 inclined It is set to Mb2, Mb2 by PMOS transistor M7, PMOS transistor M8, NMOS crystalline substance Body pipe M6 dividing potential drop produces, and nmos pass transistor M6 is biased to Vb3, and Vb3 is by PMOS Transistor M4, nmos pass transistor M5 produce.
In sum, the low-power consumption width scope operational transconductance amplifier of the present invention reduces circuit Running voltage, reduces power consumption, expands input and output voltage and gain bandwidth, the most not There is the decline causing the performances such as gain, noise, output impedance, there is good using effect.
It should be noted that above-described embodiment limits the present invention, all employings etc. the most in any form The technical scheme obtained with the mode of replacement or equivalent transformation, all falls within the protection model of the present invention In enclosing.

Claims (7)

1. a low-power consumption width scope operational transconductance amplifier, it is characterised in that including: poor Divide input stage, gain stage, output stage and auto bias circuit, wherein, described differential input stage Being made up of first order differential input stage and second level differential input stage, described output stage is put by output Big device and compensation and current foldback circuit composition, described auto bias circuit can produce vb1, vb2, Vb3 tri-bias,
The electrical connection of whole circuit is: the input of first order differential input stage accesses input Signal, the bias voltage vb3 of its load is produced by auto bias circuit, first order differential input stage Outfan be connected to the input of second level differential input stage, second level differential input stage needed for Bias voltage vb1 and vb2 produced by auto bias circuit, the output of second level differential input stage End is connected to the input of gain stage, and the output that the outfan of gain stage is connected in output stage is put On big device and compensation and current foldback circuit.
Low-power consumption width scope operational transconductance amplifier the most according to claim 1, it is special Levying and be, in differential input stage, described first order differential input stage is the source follower of cascade Structure, it is by nmos pass transistor MN1, nmos pass transistor MN2, NMOS crystal Pipe MN3, nmos pass transistor MN4, nmos pass transistor MN5, nmos pass transistor MN6 and resistance R1, resistance R2, resistance R3, resistance R4 form:
The substrate of nmos pass transistor MN1, the substrate of nmos pass transistor MN2, NMOS The substrate of transistor MN3, the substrate of nmos pass transistor MN4, nmos pass transistor MN5 Substrate and the substrate of nmos pass transistor MN6 be all connected to GND, nmos pass transistor The drain terminal of MN1 is commonly connected to supply voltage VDD with the drain terminal of nmos pass transistor MN3, The source of nmos pass transistor MN1 is connected with the drain terminal of nmos pass transistor MN2, NMOS The grid end of transistor MN1 is connected resistance R1 jointly with the grid end of nmos pass transistor MN2 One end, the other end of resistance R1 is the inverting input vinn, NMOS of operational amplifier The source of transistor MN2 is connected with one end of resistance R3, and the other end of resistance R3 connects The drain terminal of nmos pass transistor MN5, the source of nmos pass transistor MN3 is brilliant with NMOS The drain terminal of body pipe MN4 is connected, the grid end of nmos pass transistor MN3 and nmos pass transistor The grid end of MN4 connects one end of resistance R2 jointly, and the other end of resistance R2 is operation amplifier One end of the in-phase input end vinp of device, the source of nmos pass transistor MN4 and resistance R4 Being connected, the other end of resistance R4 connects the drain terminal of nmos pass transistor MN6, and NMOS is brilliant The source of body pipe MN5 and the source of nmos pass transistor MN6 are commonly connected to GND, The grid end of nmos pass transistor MN5 is commonly connected to the grid end of nmos pass transistor MN6 Auto bias circuit produce bias vb3, wherein, the source of nmos pass transistor MN2 and The source of nmos pass transistor MN4 is two outfans of first order differential input stage.
Low-power consumption width scope operational transconductance amplifier the most according to claim 2, it is special Levying and be, in differential input stage, described second level differential input stage is common-source stage amplifier knot Structure, it is by PMOS transistor MP1, PMOS transistor MP2, PMOS transistor MP3, nmos pass transistor MN9 and nmos pass transistor MN10 composition:
The source of PMOS transistor MP1 is connected jointly with the source of PMOS transistor MP2 To the drain terminal of PMOS transistor MP3, the source of PMOS transistor MP3 and PMOS The substrate of transistor MP3 is all connected to supply voltage VDD, PMOS transistor MP3 Grid end is connected to the bias vb1 that auto bias circuit produces, the grid end of PMOS transistor MP1 It is commonly connected to GND, PMOS transistor MP1 with the grid end of PMOS transistor MP2 Drain terminal be connected with the drain terminal of nmos pass transistor MN9, the leakage of PMOS transistor MP2 End is connected with the drain terminal of nmos pass transistor MN10, the source of nmos pass transistor MN9, The substrate of nmos pass transistor MN9, the source of nmos pass transistor MN10 and NMOS The substrate of transistor MN10 be all connected to GND, nmos pass transistor MN9 grid end and The grid end of nmos pass transistor MN10 is connected to the bias vb2 that auto bias circuit produces, The substrate of PMOS transistor MP1 and the substrate of PMOS transistor MP2 are second level difference Two inputs of input stage, are connected with two outfans of first order differential input stage respectively, The drain terminal of PMOS transistor MP1 and the drain terminal of PMOS transistor MP2 are second level difference Two outfans of input stage.
Low-power consumption width scope operational transconductance amplifier the most according to claim 3, it is special Levying and be, described gain stage is by PMOS transistor MP4, PMOS transistor MP5, NMOS Transistor MN7 and nmos pass transistor MN8 composition:
The source of PMOS transistor MP4, the substrate of PMOS transistor MP4, PMOS The source of transistor MP5 and the substrate of PMOS transistor MP5 are commonly connected to supply voltage VDD, the grid end of PMOS transistor MP4 is connected with the grid end of PMOS transistor MP5 And it is commonly connected to the drain terminal of PMOS transistor MP4, the drain terminal of PMOS transistor MP4 Being connected to the drain terminal of nmos pass transistor MN7, the drain terminal of PMOS transistor MP5 connects To the drain terminal of nmos pass transistor MN8, the substrate of nmos pass transistor MN7 and NMOS The substrate of transistor MN8 all connects GND, the grid of nmos pass transistor MN7 and NMOS The grid of transistor MN8 is commonly connected to supply voltage VDD, nmos pass transistor MN7 Source and source is gain stage two inputs of nmos pass transistor MN8 respectively with Two outfans of two grades of differential input stages are connected, and the drain terminal of nmos pass transistor MN8 is for increasing The outfan of benefit level.
Low-power consumption width scope operational transconductance amplifier the most according to claim 4, it is special Levying and be, in output stage, described out amplifier is by PMOS transistor MP8, NMOS Transistor MN15 and resistance R7 composition:
The source of PMOS transistor MP8 and substrate connect supply voltage VDD, PMOS crystal One end of the drain terminal connecting resistance R7 of pipe MP8, the other end of resistance R7 is output node VOUT, the outfan of the grid termination gain stage of PMOS transistor MP8, NMOS crystal The source of pipe MN15 and substrate meet GND, and the drain terminal of nmos pass transistor MN15 is output The grid end of node VOUT, nmos pass transistor MN15 is connected to bias Va, described bias Va is by compensating and current foldback circuit generation.
Low-power consumption width scope operational transconductance amplifier the most according to claim 5, it is special Levying and be, in output stage, described compensation and current foldback circuit are by compensating electric capacity C1, benefit Repay electric capacity C2, nmos pass transistor MN11, nmos pass transistor MN12, NMOS crystalline substance Body pipe MN13, nmos pass transistor MN14, nmos pass transistor MN15, PMOS crystalline substance Body pipe MP6, PMOS transistor MP7 and resistance R5 and resistance R6 composition:
Compensate electric capacity C1 to be connected between gain stage output and output node VOUT, complete close Strangle and compensate；
PMOS transistor MP6, the source of PMOS transistor MP7 and substrate terminal all connect To supply voltage VDD, the grid end of PMOS transistor MP6 is connected to the outfan of gain stage, The drain terminal of PMOS transistor MP6 connects grid end and the resistance of nmos pass transistor MN12 One end of R5, the other end of resistance R5 connects the drain terminal of nmos pass transistor MN12, The source of nmos pass transistor MN12 connects drain terminal and the grid end of nmos pass transistor MN11 And the grid end of nmos pass transistor MN13, the substrate terminal of nmos pass transistor MN12, The source of nmos pass transistor MN11 and substrate terminal are all connected to GND, PMOS transistor The grid end of MP7 connects the bias voltage vb1 that auto bias circuit produces, PMOS transistor MP7 Drain terminal connect the grid end of nmos pass transistor MN14 and one end of resistance R6, resistance R6 The other end connect nmos pass transistor MN14 drain terminal, and for output stage load NMOS Transistor MN15 provides bias voltage va, and the source of nmos pass transistor MN14 is connected to The drain terminal of nmos pass transistor MN13, the substrate terminal of nmos pass transistor MN14, NMOS Source and the substrate terminal of transistor MN13 are all connected to GND.
Low-power consumption width scope operational transconductance amplifier the most according to claim 6, it is special Levying and be, described auto bias circuit provides bias voltage for amplifiers at different levels, and it is by PMOS Transistor M1, PMOS transistor M2, PMOS transistor M3, PMOS transistor M4, PMOS transistor M7, PMOS transistor M8, nmos pass transistor M5 and Nmos pass transistor M6 forms:
PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, PMOS The substrate of transistor M4, PMOS transistor M7 and PMOS transistor M8 is all connected to Supply voltage VDD, the substrate of nmos pass transistor M5 and nmos pass transistor M6 all connects Receive GND, the source of PMOS transistor M1, the source of PMOS transistor M4, PMOS The source of transistor M7 is connected to supply voltage VDD, the drain terminal of PMOS transistor M1 It is connected with the source of PMOS transistor M2, the grid end of PMOS transistor M1 and PMOS The grid end of transistor M4, the drain terminal of PMOS transistor M2, PMOS transistor M3 Source is connected, and common generation biases vb1, and the grid end of PMOS transistor M2 is brilliant with PMOS The grid end of body pipe M7, the grid end of PMOS transistor M8, the leakage of PMOS transistor M8 End, the drain terminal of M6 are connected, and common generation biases vb3, the grid end of PMOS transistor M3 It is connected with drain terminal, the drain terminal of the drain terminal of PMOS transistor M4 and nmos pass transistor M5, The grid end of nmos pass transistor M5 is connected with the grid end of nmos pass transistor M6, jointly produces Raw bias vb2.
CN201610265136.4A 2016-04-26 2016-04-26 Low-power-consumption wide-range operational transconductance amplifier Pending CN105958948A (en)

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CN106374859A (en) * 2016-10-27 2017-02-01 广西师范大学 Low-pressure low-power consumption trans-conductance amplifier
CN108155875A (en) * 2016-12-02 2018-06-12 瑞昱半导体股份有限公司 Power amplifier
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CN106788294A (en) * 2016-12-15 2017-05-31 芯海科技（深圳）股份有限公司 A kind of adjustable amplifier of number of stages of amplification
CN107834981A (en) * 2017-11-13 2018-03-23 东南大学 A kind of loop discharge circuit of anti-PV changes
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CN112398447A (en) * 2019-08-13 2021-02-23 圣邦微电子（北京）股份有限公司 Output stage circuit for reducing THD (Total harmonic distortion) of low-voltage operational amplifier based on CMOS (complementary Metal oxide semiconductor) process
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CN112234948B (en) * 2020-10-26 2022-09-06 成都华微电子科技股份有限公司 High-speed high-linearity time-interleaved dynamic operational amplifier circuit

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Application publication date: 20160921