CN112953420B - Dynamic operational amplifier circuit with input tube in linear region - Google Patents
Dynamic operational amplifier circuit with input tube in linear region Download PDFInfo
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Abstract
A dynamic operational amplifier circuit with an input tube in a linear region belongs to the technical field of analog integrated circuits. The input range of the dynamic operational amplifier is enlarged by enabling the input tube to be in a linear region; meanwhile, a cascode tube is introduced to stabilize the drain-end voltage of the input tube, so that the input gate-source voltage and the drain-source current of the input tube in a linear region have a good linear relation, the transconductance of the input tube changes little along with input and output signals, and the gain precision of the dynamic operational amplifier is ensured; in addition, the cascade pipe is adopted, and kickback noise fed back from the output end to the input end is reduced. The invention respectively provides the dynamic operational amplifier structure when the NMOS tube is used as the input tube and the PMOS tube is used as the input tube, and the application range is wider.
Description
Technical Field
The invention belongs to the technical field of analog integrated circuits, and relates to a dynamic operational amplifier structure with large input-output swing amplitude and high linearity of an input tube in a linear region, which can be applied to a pipeline-successive approximation-type analog-to-digital converter (P-SAR ADC).
Background
Analog-to-digital converters are a constant topic in analog circuit design. In a high-speed and high-precision application scenario, a pipeline-successive approximation architecture is a highly desirable analog-to-digital converter (ADC). The front end of the structure is a high-precision successive approximation-register analog-to-digital converter (SAR ADC) which is used for carrying out first quantization on an analog signal; the middle part is provided with a dynamic operational amplifier which is used for amplifying the redundant analog signal obtained by the first quantization; and the rear end is provided with an SAR ADC (synthetic aperture radar) which is used for quantizing the amplified redundant analog signal again. The digital coding combination obtained by the two quantization steps obtains the digital signal corresponding to the analog signal of the input end. The gain precision of the dynamic operational amplifier directly affects the precision of the whole ADC, and the output swing amplitude of the dynamic operational amplifier can affect the quantization precision of the next-stage SAR ADC so as to indirectly affect the precision of the whole ADC.
Fig. 1 shows a conventional dynamic operational amplifier structure, and fig. 2 shows a corresponding timing diagram.
When the clock signal CLK is low, the dynamic operational amplifier is in a reset state, M5, M6, M7 are turned on, M1 is turned off to turn off M2, M3, M4, and the node V is connected to the power supply P 、V N 、V OCM Is reset to the supply voltage VDD, node V OCM The voltage is obtained into a SW signal through two inverters, the SW signal is in a high level, the SW signal controls the switches SW1 and SW2 to be closed (when the SW is in the high level, the SW1 and the SW2 are closed, and when the SW is in the low level, the SW1 and the SW2 are opened), and the load capacitor C L Upper output node V OP 、V ON Is charged to the power supply voltage VDD.
When the clock signal CLK is high level, the dynamic operational amplifier starts to work in the amplifying state, M5, M6 and M7 are disconnected, M1, M2, M3 and M4 are conducted, SW1 and SW2 continue the closing state of the reset stage, and the load capacitor C is connected with the load capacitor C L Upper output node V OP 、V ON The voltage drops from the supply voltage VDD at different rates (depending on the input differential magnitude) until the sampling capacitor C S Sampled output common mode level V OCM Falls to the inversion threshold voltage of the inverter, the SW signal changes to low level, the switches SW1 and SW2 are turned off, and the output node V is turned off OP 、V ON The voltage is kept unchanged, M2 is disconnected, then M3 and M4 are cut off, and the output node V OP 、V ON The maintained voltage difference is used as the output differential voltage of the amplifier. The output differential voltage is divided by the input differential voltage to obtain the gain of the amplifier.
The gain of such an integrating dynamic operational amplifier can be expressed as
Wherein V OP 、V ON Is the output node voltage, Δ V IN ＝V IP -V IN Is an input differential signal, g m Is the transconductance of input transistors M3 and M4, I D0 Is the common mode leakage current, i.e. the average of the currents flowing through M3 and M4, VDD is the supply voltage, V TH Is the inverter flip threshold voltage. Due to g m /I D0 、VDD-V TH The value of (c) is limited and thus the dynamic op amp gain of this architecture is small, typically only 4-5 times. The input swing of this architecture is large, since a large output swing is beneficial for the quantization of the next stage SAR ADC.
In the schematic diagram of the conventional dynamic operational amplifier circuit shown in fig. 1, since the input transistors M3 and M4 operate in the saturation region, the drain currents flowing through M3 and M4 are proportional to the square of the gate-source voltage, and only in the case of very small input differential signals, the drain current and the gate-source voltage of the input transistors can be approximately linear (i.e., transconductance g) m Constant). Along with the transfusionThe linearity of the drain current and the gate-source voltage of the input tube is increasingly poor (namely transconductance g) due to the increase of the input difference m Large variations) resulting in increasingly less gain accuracy of the overall amplifier. As shown in FIG. 2, due to the linearity difference between the drain current and the gate-source voltage of the input tube in this structure, the output node V OP 、V ON The voltage drops in an arc, resulting in poor amplification accuracy of the dynamic operational amplifier. In addition, the change of the voltage at the output end is fed back to the input end through the grid-drain parasitic capacitance of the input tube, and the introduced kickback noise also causes the linearity to be deteriorated. When the input swing of the dynamic operational amplifier with the traditional structure is 40mV, the effective digit is only 7 bits.
Disclosure of Invention
Aiming at the problem that the input tube in the traditional dynamic operational amplifier is in a saturation region, so that the linearity of the drain-end current and the gate-source voltage of the input tube is poorer and poorer along with the increase of the input difference, and the gain precision of the amplifier is low, the invention provides a dynamic operational amplifier structure, wherein the input tube is in a linear region, and a cascode tube is introduced to stabilize the drain-end voltage of the input tube, so that the drain-source voltage of the input tube in the linear region is constant, and the good linear relation between the input gate-source voltage and the drain-source current is realized, therefore, the transconductance of the input tube of the dynamic operational amplifier structure provided by the invention is small along with the change of input and output signals, and the gain precision is higher.
The input tube of the dynamic operational amplifier structure can be realized by an NMOS tube or a PMOS tube, and when the input tube of the dynamic operational amplifier structure is realized by the NMOS tube, the technical scheme of the invention is as follows:
a dynamic operational amplifier circuit with an input tube in a linear region comprises a first switch device, a second switch device, a third switch device, a fourth switch device, a fifth switch device, a sixth switch device, a seventh switch device, a first load capacitor, a second load capacitor, a first sampling capacitor, a second sampling capacitor, a switch control module, a first input tube and a second input tube, wherein the capacitance values of the first load capacitor and the second load capacitor are equal, the capacitance values of the first sampling capacitor and the second sampling capacitor are equal, the first input tube is a first NMOS tube, and the second input tube is a second NMOS tube;
the first connection end of the first switching device is used as a first differential output end of the dynamic operational amplifier circuit and is grounded after passing through the first load capacitor, and the second connection end of the first switching device is connected with the first connection end of the first sampling capacitor and is used as a first middle node;
the first connecting end of the second switching element is used as a second differential output end of the dynamic operational amplifier circuit and is grounded after passing through a second load capacitor, and the second connecting end of the second switching element is connected with the first connecting end of a second sampling capacitor and is used as a second intermediate node;
the second connecting end of the first sampling capacitor is connected with the second connecting end of the second sampling capacitor and the input end of the switch control module and is connected with the power supply voltage after passing through a third switch device;
a fourth switching device coupled between the first intermediate node and the supply voltage and a fifth switching device coupled between the second intermediate node and the supply voltage;
the first connecting end of the sixth switching device is connected with the first connecting end of the seventh switching device, and the second connecting end of the sixth switching device is grounded;
a second connecting end of the seventh switching device is connected with a source electrode of the first NMOS tube and a source electrode of the second NMOS tube, a grid electrode of the first NMOS tube is used as a first differential input end of the dynamic operational amplifier circuit, and a grid electrode of the second NMOS end is used as a second differential input end of the dynamic operational amplifier circuit;
the third switching device, the fourth switching device, the fifth switching device and the sixth switching device are controlled by a clock signal, and when the clock signal is in a first state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched on, and the sixth switching device is controlled to be switched off; when the clock signal is in a second state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched off, and the sixth switching device is controlled to be switched on;
the first switch device, the second switch device and the seventh switch device are controlled by an output signal of the switch control module, the switch control module is used for comparing a voltage value of an input end of the switch control module with a turnover threshold voltage, and when the voltage value of the input end of the switch control module is not lower than the turnover threshold voltage, the output signal of the switch control module controls the first switch device, the second switch device and the seventh switch device to be conducted; when the voltage value of the input end of the switch control module is lower than the overturning threshold voltage, the output signal of the switch control module controls the first switch device, the second switch device and the seventh switch device to be switched off;
the dynamic operational amplifier circuit further comprises a third NMOS tube and a fourth NMOS tube;
the grid electrode of the third NMOS tube is connected with bias voltage, the source electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube, and the drain electrode of the third NMOS tube is connected with the first intermediate node;
the grid electrode of the fourth NMOS tube is connected with the bias voltage, the source electrode of the fourth NMOS tube is connected with the drain electrode of the second NMOS tube, and the drain electrode of the fourth NMOS tube is connected with the second intermediate node;
the first NMOS tube and the second NMOS tube work in a linear region, and the third NMOS tube and the fourth NMOS tube work in a saturation region.
Specifically, the switch control module comprises a first inverter and a second inverter, wherein the input end of the first inverter is connected with the input end of the switch control module, and the output end of the first inverter is connected with the input end of the second inverter; and the output end of the second inverter outputs the output signal of the switch control module.
Specifically, the seventh switching device is a fifth NMOS transistor, a gate of the fifth NMOS transistor is connected to the output signal of the switching control module, a source of the fifth NMOS transistor is used as the first connection end of the seventh switching device, and a drain of the fifth NMOS transistor is used as the second connection end of the seventh switching device.
Specifically, the third switching device is a first PMOS transistor, the fourth switching device is a second PMOS transistor, the fifth switching device is a third PMOS transistor, and the sixth switching device is a sixth NMOS transistor;
the grid electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are all connected with the clock signal, the source electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are all connected with the power supply voltage, the drain electrode of the first PMOS tube is connected with the input end of the switch control module, the drain electrode of the second PMOS tube is connected with the first intermediate node, and the drain electrode of the third PMOS tube is connected with the second intermediate node;
the grid electrode of the sixth NMOS tube is connected with the clock signal, the drain electrode of the sixth NMOS tube is used as the first connecting end of the sixth switching device, and the source electrode of the sixth NMOS tube is used as the second connecting end of the sixth switching device.
When the input tube of the dynamic operational amplifier structure is realized by a PMOS tube, the technical scheme of the invention is as follows:
a dynamic operational amplifier circuit with an input tube in a linear region comprises a first switch device, a second switch device, a third switch device, a fourth switch device, a fifth switch device, a sixth switch device, a seventh switch device, a first load capacitor, a second load capacitor, a first sampling capacitor, a second sampling capacitor, a switch control module, a first input tube and a second input tube, wherein the capacitance values of the first load capacitor and the second load capacitor are equal, the capacitance values of the first sampling capacitor and the second sampling capacitor are equal, the first input tube is a fourth PMOS tube, and the second input tube is a fifth PMOS tube;
the first connection end of the first switching device is used as a first differential output end of the dynamic operational amplifier circuit and is grounded after passing through the first load capacitor, and the second connection end of the first switching device is connected with the first connection end of the first sampling capacitor and is used as a first middle node;
the first connecting end of the second switching element is used as a second differential output end of the dynamic operational amplifier circuit and is grounded after passing through a second load capacitor, and the second connecting end of the second switching element is connected with the first connecting end of a second sampling capacitor and is used as a second intermediate node;
the second connecting end of the first sampling capacitor is connected with the second connecting end of the second sampling capacitor and the input end of the switch control module and is grounded after passing through a third switch device;
a fourth switching device is connected between the first intermediate node and ground, and a fifth switching device is connected between the second intermediate node and ground;
the first connecting end of the sixth switching device is connected with the first connecting end of the seventh switching device, and the second connecting end of the sixth switching device is connected with power supply voltage;
a second connecting end of the seventh switching device is connected with a source electrode of a fourth PMOS tube and a source electrode of a fifth PMOS tube, a grid electrode of the fourth PMOS tube is used as a first differential input end of the dynamic operational amplifier circuit, and a grid electrode of a second PMOS end is used as a second differential input end of the dynamic operational amplifier circuit;
the third switching device, the fourth switching device, the fifth switching device and the sixth switching device are controlled by a clock signal, and when the clock signal is in a first state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched on, and the sixth switching device is controlled to be switched off; when the clock signal is in a second state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched off, and the sixth switching device is controlled to be switched on;
the first switch device, the second switch device and the seventh switch device are controlled by an output signal of the switch control module, the switch control module is used for comparing a voltage value of an input end of the switch control module with a turnover threshold voltage, and when the voltage value of the input end of the switch control module is not lower than the turnover threshold voltage, the output signal of the switch control module controls the first switch device, the second switch device and the seventh switch device to be conducted; when the voltage value of the input end of the switch control module is lower than the overturning threshold voltage, the output signal of the switch control module controls the first switch device, the second switch device and the seventh switch device to be switched off;
the dynamic operational amplifier circuit further comprises a sixth PMOS tube and a seventh PMOS tube;
the grid electrode of the sixth PMOS tube is connected with bias voltage, the source electrode of the sixth PMOS tube is connected with the drain electrode of the fourth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the first intermediate node;
the grid electrode of the seventh PMOS tube is connected with the bias voltage, the source electrode of the seventh PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the second intermediate node;
the fourth PMOS tube and the fifth PMOS tube work in a linear region, and the sixth PMOS tube and the seventh PMOS tube work in a saturation region.
Specifically, the switch control module comprises a first inverter and a second inverter, wherein the input end of the first inverter is connected with the input end of the switch control module, and the output end of the first inverter is connected with the input end of the second inverter; and the output end of the second inverter outputs the output signal of the switch control module.
Specifically, the seventh switching device is an eighth PMOS transistor, a gate of the eighth PMOS transistor is connected to the output signal of the switch control module, a source of the eighth PMOS transistor is used as the first connection end of the seventh switching device, and a drain of the eighth PMOS transistor is used as the second connection end of the seventh switching device.
Specifically, the third switching device is a seventh NMOS transistor, the fourth switching device is an eighth NMOS transistor, the fifth switching device is a ninth NMOS transistor, and the sixth switching device is a ninth PMOS transistor;
the grid electrodes of the seventh NMOS tube, the eighth NMOS tube and the ninth NMOS tube are all connected with the clock signal, the source electrodes of the seventh NMOS tube, the eighth NMOS tube and the ninth NMOS tube are all grounded, the drain electrode of the seventh NMOS tube is connected with the input end of the switch control module, the drain electrode of the eighth NMOS tube is connected with the first intermediate node, and the drain electrode of the ninth NMOS tube is connected with the second intermediate node;
the gate of the ninth PMOS transistor is connected to the clock signal, the drain of the ninth PMOS transistor is used as the first connection terminal of the sixth switching device, and the source of the ninth PMOS transistor is used as the second connection terminal of the sixth switching device.
The beneficial effects of the invention are as follows: the dynamic operational amplifier provided by the invention obtains stable input transconductance, small kickback noise and larger input and output swing amplitude through the cascode structure of the input tube in the linear region, and compared with the traditional dynamic operational amplifier, the dynamic operational amplifier provided by the invention has higher gain precision and larger input and output swing amplitude.
Drawings
The following description of various embodiments of the invention may be better understood with reference to the following drawings, which schematically illustrate major features of some embodiments of the invention. These figures and examples provide some embodiments of the invention in a non-limiting, non-exhaustive manner. For purposes of clarity, the same reference numbers will be used in different drawings to identify the same or similar elements or structures having the same function.
Fig. 1 is a circuit schematic of a conventional dynamic operational amplifier.
Fig. 2 is a timing diagram of a conventional dynamic operational amplifier.
Fig. 3 is a circuit diagram of a dynamic operational amplifier circuit with an input transistor in a linear region according to the present invention, when the input transistor is implemented by an NMOS transistor.
FIG. 4 is a timing diagram of a dynamic operational amplifier circuit with an input transistor in a linear region, when the input transistor is implemented by an NMOS transistor.
Fig. 5 is a result of FFT analysis of a conventional dynamic operational amplifier.
Fig. 6 is a FFT analysis result of a dynamic operational amplifier circuit with an input transistor in a linear region according to the present invention, when the input transistor is implemented by an NMOS transistor.
Fig. 7 is a circuit diagram of a dynamic operational amplifier circuit with an input transistor in a linear region according to the present invention, when the input transistor is implemented by a PMOS transistor.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
It should be noted that, in the present invention, the relational terms such as first and second, and the like are only used for distinguishing one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.
The current is not well controlled because the drain-source voltage of a transistor operating in the linear region varies and directly affects the current. The transistor operating in the saturation region is generally used as an input transistor because the drain voltage variation of the transistor has little influence on the current and the current is easily controlled by the gate voltage. However, the linearity of the input tube in the saturation region is considered to be better when the input signal is small, but as the input signal increases, the gain accuracy of the amplifier is reduced when the input tube in the dynamic operational amplifier is in the saturation region. Therefore, the invention breaks through the traditional method that the input tube usually adopts a transistor working in a saturation region, provides that the input tube of the dynamic operational amplifier is in a linear region, and simultaneously introduces a cascode transistor to stabilize the drain-end voltage of the input tube, so that the input gate-source voltage to the drain-source current of the input tube in the linear region has a good linear relation, and the input range of the invention is greatly enlarged compared with the input range of the traditional structure under the same amplification precision.
As shown in fig. 3, the dynamic operational amplifier circuit with an NMOS input tube in a linear region includes a first switch device SW1, a second switch device SW2, a third switch device, a fourth switch device, a fifth switch device, a sixth switch device, a seventh switch device, a first load capacitor, a second load capacitor, a first sampling capacitor, a second sampling capacitor, a switch control module, a first input tube and a second input tube, wherein capacitance values of the first load capacitor and the second load capacitor are equal and are both C L The capacitance values of the first sampling capacitor and the second sampling capacitor are equal and are both C S The first input tube is a first NMOS tube MN1, and the second input tube is a second NMOS tube MN 2; the grid electrode of the first NMOS transistor MN1 is used as a first differential input end of the dynamic operational amplifier circuit, and the grid electrode of the second NMOS terminal is used as a second differential input end of the dynamic operational amplifier circuit; the first connection end of the first switching device SW1 is used as the first differential output end of the dynamic operational amplifier circuit and is grounded after passing through the first load capacitor, and the second connection end of the first switching device SW1 is connected with the first connection end of the first sampling capacitor and is used as the first middle node V P (ii) a The first connection terminal of the second switching device SW2 being a dynamic operational amplifier circuitThe second differential output end is grounded after passing through the second load capacitor, and the second connecting end is connected with the first connecting end of the second sampling capacitor and is used as a second intermediate node V N (ii) a If the first differential input terminal of the dynamic operational amplifier circuit is a negative input terminal V IN The second differential input terminal of the dynamic operational amplifier circuit is a positive input terminal V IP The first differential output terminal of the dynamic operational amplifier circuit is a positive output terminal V OP The second differential output end of the dynamic operational amplifier circuit is a negative output end V ON . Of course, the input tube of the dynamic operational amplifier is symmetrical, and the positive and negative input ends and the positive and negative output ends can be interchanged.
When the input tube is an NMOS tube, the invention introduces a third NMOS tube MN3 and a fourth NMOS tube to form a cascode structure with a first NMOS tube MN1 and a second NMOS tube MN2, and the grid electrode of the third NMOS tube MN3 is connected with a bias voltage V B A source connected to the drain of the first NMOS transistor MN1, and a drain connected to the first intermediate node V P (ii) a The grid electrode of the fourth NMOS tube is connected with a bias voltage V B A source connected to the drain of the second NMOS transistor MN2, and a drain connected to a second intermediate node V N (ii) a The first NMOS transistor MN1 and the second NMOS transistor MN2 are input paired transistors and work in a linear region, the third NMOS transistor MN3 and the fourth NMOS transistor are cascode transistors and work in a saturation region, and the structure has high linearity in an integral circuit.
The second connecting end of the first sampling capacitor is connected with the second connecting end of the second sampling capacitor and the input end of the switch control module and is connected with the power supply voltage VDD through a third switch device; the fourth switching device is connected between the first intermediate node and the power supply voltage VDD, and the fifth switching device is connected between the second intermediate node and the power supply voltage VDD; the first connecting end of the sixth switching device is connected with the first connecting end of the seventh switching device, and the second connecting end of the sixth switching device is grounded; a second connection terminal of the seventh switching device is connected to the source electrode of the first NMOS transistor MN1 and the source electrode of the second NMOS transistor MN 2.
The third, fourth, fifth and sixth switching devices are controlled by a clock signal CLK, and when the clock signal CLK is in a first state, the third, fourth and fifth switching devices are controlledThe switching device is connected with the fifth switching device, and the sixth switching device is controlled to be disconnected; and when the clock signal CLK is in a second state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched off, and the sixth switching device is controlled to be switched on. The first switching device SW1, the second switching device SW2 and the seventh switching device are controlled by an output signal of a switch control module, and the switch control module is used for controlling a voltage value V at an input end of the switch control module OCM Comparing with the turning threshold voltage, and when the voltage value V of the input end of the switch control module OCM When the turning threshold voltage is not lower than the turning threshold voltage, the output signal of the switch control module controls the first switch device SW1, the second switch device SW2 and the seventh switch device to be conducted; when the voltage value V of the input end of the switch control module OCM Below the rollover threshold voltage, the output signal of the switch control module controls the first switching device SW1, the second switching device SW2, and the seventh switching device to open.
In some embodiments, the third to fifth switching devices are implemented by PMOS transistors, and the sixth and seventh switching devices are implemented by NMOS transistors, as shown in fig. 3, the seventh switching device is a fifth NMOS transistor MN5, a gate of the fifth NMOS transistor MN5 is connected to the output signal SW of the switch control module, a source thereof is used as the first connection terminal of the seventh switching device, and a drain thereof is used as the second connection terminal of the seventh switching device. The third switching device is a first PMOS transistor MP1, the fourth switching device is a second PMOS transistor MP2, the fifth switching device is a third PMOS transistor MP3, and the sixth switching device is a sixth NMOS transistor MN 6; the gates of the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3 are all connected to a clock signal CLK, the sources thereof are all connected to a power supply voltage VDD, the drain of the first PMOS transistor MP1 is connected to the input terminal of the switch control module, the drain of the second PMOS transistor MP2 is connected to the first intermediate node, and the drain of the third PMOS transistor MP3 is connected to the second intermediate node; the gate of the sixth NMOS transistor MN6 is connected to the clock signal CLK, the drain thereof serves as the first connection terminal of the sixth switching device, and the source thereof serves as the second connection terminal of the sixth switching device.
The switch control module is used for converting the voltage value V of the input end of the switch control module OCM The comparison with the flip threshold voltage can be performed by an inverterThe implementation can also be realized by a comparator, as shown in fig. 3, a structure of a switch control module realized by an inverter is given, in this embodiment, the switch control module includes a first inverter INV1 and a second inverter INV2, an input end of the first inverter INV1 is connected to the signal V input by the input end of the switch control module OCM The output end of the inverter is connected with the input end of the second inverter INV 2; an output end of the second inverter INV2 outputs the output signal SW of the switch control module.
The operation and the operation principle of the present embodiment will be described in detail below.
When the input tube is realized by adopting an NMOS tube in the embodiment, when the input tube MN1 and the input tube MN2 are in a linear region, the drain-end voltage of the input tube is stabilized by adding the cascode tube MN3 and the cascode tube MN4 in the design, and the charge coupled to the input from the output end is also reduced by adding the cascode tube, so that the kickback noise is greatly reduced. Therefore, the input end gate voltage and the output end drain current in the structure provided by the invention have good linear relation, the input tube transconductance changes little along with input and output signals, and the provided amplifier has higher gain precision.
When the clock signal CLK is at a low level, the dynamic operational amplifier is in a reset state, the third, fourth and fifth switching devices (i.e., the first, second and third PMOS transistors MP1, MP2 and MP3) are turned on, the sixth switching device (i.e., the sixth NMOS transistor MN6) is turned off, which causes the first, second, fourth and seventh NMOS transistors MN1, MN2, MN3, MN4 and MN5 to be turned off, and the first node V is connected to the first node V P And a second node V N And the input end potential V of the switch control module OCM Is reset to the power supply voltage VDD, and the input end potential V of the switch control module OCM The output signal of the switch control module, namely the switch control signal SW, is obtained after passing through the two inverters of the switch control module, at the moment, the switch control signal SW is in a high level, the switch control signal SW controls the first switch device SW1 and the second switch device SW2 to be closed (when the SW is in the high level, the SW1 and the SW2 are closed, and when the SW is in the low level, the SW1 and the SW2 are opened), and the two load capacitors C L Upper output node V OP 、V ON Is charged to the power supply voltage VDD.
When the clock signal CLK is at a high level, the dynamic operational amplifier starts to operate in an amplification state, the third, fourth and fifth switching devices (i.e., the first, second and third PMOS transistors MP1, MP2 and MP3) are turned off, the first, second and seventh switching devices MN1, MN2, MN3, MN4, MN6 and MN5 are turned on, the first and second switching devices SW1 and SW2 are initially maintained in a closed state, and an output node V between the two load capacitors CL is at a high level OP 、V ON The voltage drops from the supply voltage VDD at different rates (depending on the input differential magnitude) until the sampling capacitor C S Sampled output common mode level V OCM Down to the flip threshold voltage V of the inverter TH When the switch control signal SW changes to the low level, the first switching device SW1 and the second switching device SW2 are turned off, and the node V is outputted OP 、V ON The voltage remains unchanged, the seventh switching device (i.e., the fifth NMOS transistor MN5) is turned off, and then the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are turned off, and the output node V is connected to the output node V OP 、V ON The maintained voltage difference is used as the differential output of the amplifier. The output differential voltage is divided by the input differential signal to obtain the gain of the amplifier.
As shown in fig. 3, when the input transistor is an NMOS transistor, the first NMOS transistor MN1 and the second NMOS transistor MN2 of the input transistor in this embodiment operate in a linear region, so that the transconductance of the input transistor is not related to the magnitude of the input differential signal, and is proportional to the voltage value at the drain terminal of the input transistor, and thus the structure has a large input swing. Since the added cascode transistors (the third NMOS transistor MN3 and the fourth NMOS transistor MN4) have shielding effect on the voltage variation at the output end, the drain end voltage of the input transistor is basically stable and unchanged, and thus the input voltage to the output current has high linearity. In addition, the added cascode tubes (the third NMOS tube MN3 and the fourth NMOS tube MN4) have the function of shielding the voltage variation of the output end, so that the voltage variation fed back to the input end by the voltage variation of the output end is very small, and the input voltage of the amplifier is also improved to the output endLinearity of the current. When viewed in conjunction with the waveform diagram shown in fig. 4, the output node V is just due to the good linear relationship between the drain current of the input tube and the gate-source voltage in the structure of this embodiment OP 、V ON The voltage drops linearly.
In order to embody specific performance, a conventional structure circuit and a structure circuit of the embodiment shown in fig. 3 are simulated, fig. 5 is an output signal FFT analysis result of a conventional dynamic operational amplifier, fig. 6 is an output signal FFT analysis result of the dynamic operational amplifier in the embodiment, and it can be seen that under the condition that the input swing of the dynamic operational amplifier is 40mV as the input swing of the conventional structure, The Harmonic Distortion (THD) of the present invention is 53.29dB, the significant bit (Enob) is 8.56bit, while The Harmonic Distortion (THD) of the conventional structure is 43.78dB, and the significant bit is only 6.98 bit. The structure provided by the invention obviously reduces harmonic distortion, improves amplification precision, and can meet the requirements of a higher-performance pipeline-successive approximation type analog-to-digital converter on the performance of an amplifier.
In the embodiment shown in fig. 3, the input tube and the introduced cascode tube are both NMOS transistors, and may also all correspondingly use PMOS transistors, so that the high linearity of the implemented dynamic operational amplifier is still true, and the working principle and effect are the same. As shown in fig. 7, when the input tube and the introduced cascode tube are implemented by PMOS tubes, the dynamic operational amplifier circuit includes a first switch device SW1, a second switch device SW2, a third switch device, a fourth switch device, a fifth switch device, a sixth switch device, a seventh switch device, a first load capacitor, a second load capacitor, a first sampling capacitor, a second sampling capacitor, a switch control module, a first input tube, a second input tube, and introduced cascode tubes (a sixth PMOS tube MP6 and a seventh PMOS tube MP7), where capacitance values of the first load capacitor and the second load capacitor are equal, capacitance values of the first sampling capacitor and the second sampling capacitor are equal, the first input tube is the fourth PMOS tube MP4, and the second input tube is the fifth PMOS tube MP 5; the first connecting end of the first switching device SW1 is used as a first differential output end of the dynamic operational amplifier circuit and is grounded after passing through the first load capacitor, and the second connecting end of the first switching device SW1 is connected with the first connecting end of the first sampling capacitor and is used as a first middle node; the first connecting end of the second switching device SW2 is used as a second differential output end of the dynamic operational amplifier circuit and is grounded after passing through a second load capacitor, and the second connecting end of the second switching device SW2 is connected with the first connecting end of the second sampling capacitor and is used as a second intermediate node; the second connecting end of the first sampling capacitor is connected with the second connecting end of the second sampling capacitor and the input end of the switch control module and is grounded after passing through the third switching device; the fourth switching device is connected between the first intermediate node and the ground, and the fifth switching device is connected between the second intermediate node and the ground; the first connecting end of the sixth switching device is connected with the first connecting end of the seventh switching device, and the second connecting end of the sixth switching device is connected with a power supply voltage VDD; a second connection end of the seventh switch device is connected with a source electrode of the fourth PMOS transistor MP4 and a source electrode of the fifth PMOS transistor MP5, a gate electrode of the fourth PMOS transistor MP4 serves as a first differential input end of the dynamic operational amplifier circuit, and a gate electrode of the second PMOS terminal serves as a second differential input end of the dynamic operational amplifier circuit; the third switching device, the fourth switching device, the fifth switching device and the sixth switching device are controlled by a clock signal CLK, and when the clock signal CLK is in a first state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched on and the sixth switching device is controlled to be switched off; when the clock signal CLK is in a second state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched off, and the sixth switching device is controlled to be switched on; the first switch device SW1, the second switch device SW2 and the seventh switch device are controlled by an output signal of a switch control module, the switch control module is used for comparing a voltage value of an input end of the switch control module with a turnover threshold voltage, and when the voltage value of the input end of the switch control module is not lower than the turnover threshold voltage, the output signal of the switch control module controls the first switch device SW1, the second switch device SW2 and the seventh switch device to be conducted; when the voltage value of the input end of the switch control module is lower than the overturning threshold voltage, the output signal of the switch control module controls the first switch device SW1, the second switch device SW2 and the seventh switch device to be switched off; the gate of the sixth PMOS transistor MP6 is connected to the bias voltage, the source thereof is connected to the drain of the fourth PMOS transistor MP4, and the drain thereof is connected to the first intermediate node; the gate of the seventh PMOS transistor MP7 is connected to the bias voltage, the source thereof is connected to the drain of the fifth PMOS transistor MP5, and the drain thereof is connected to the second intermediate node; the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 operate in a linear region, and the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 operate in a saturation region.
In some embodiments, the third to fifth switching devices are implemented by NMOS transistors, and the sixth and seventh switching devices are implemented by PMOS transistors, as shown in fig. 7, the seventh switching device is an eighth PMOS transistor MP8, a gate of the eighth PMOS transistor MP8 is connected to the output signal of the switch control module, a source thereof is used as the first connection terminal of the seventh switching device, and a drain thereof is used as the second connection terminal of the seventh switching device. The third switching device is a seventh NMOS transistor MN7, the fourth switching device is an eighth NMOS transistor MN8, the fifth switching device is a ninth NMOS transistor MN9, and the sixth switching device is a ninth PMOS transistor MP 9; the gates of the seventh NMOS transistor MN7, the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are all connected to the clock signal CLK, the sources thereof are all grounded, the drain of the seventh NMOS transistor MN7 is connected to the input terminal of the switch control module, the drain of the eighth NMOS transistor MN8 is connected to the first intermediate node, and the drain of the ninth NMOS transistor MN9 is connected to the second intermediate node; the gate of the ninth PMOS transistor MP9 is connected to the clock signal CLK, the drain thereof is used as the first connection terminal of the sixth switching device, and the source thereof is used as the second connection terminal of the sixth switching device.
In the embodiment shown in FIG. 7, the signal V IP 、V IN The level of the positive input terminal (i.e. the second input terminal of the dynamic operational amplifier) and the level of the negative input terminal (i.e. the first input terminal of the dynamic operational amplifier) of the dynamic operational amplifier, respectively, and a node V OP 、V ON Positive output terminal (i.e. first output terminal) and negative output terminal (i.e. second output terminal) of the dynamic operational amplifier, nodes VDD and GND are power voltage and ground voltage, respectively, signal CLK is input-controlled clock signal, and signal V is output from the dynamic operational amplifier B For the bias voltage, the signal SW is a digital signal generated by the switch control module to control the operation states of the first switching device SW1, the second switching device SW2 and the seventh switching device (MP 8). The operation principle and the operation process of the dynamic operational amplifier circuit for realizing the input transistor by the PMOS transistor shown in FIG. 7 and the input transistor by the NMOS transistor shown in FIG. 3 are similarAnd will not be described herein.
According to the dynamic operational amplifier circuit with the input tube in the linear region, the input range of the dynamic operational amplifier is enlarged by enabling the input tube to be in the linear region; meanwhile, a cascode tube is introduced to stabilize the drain-terminal voltage of the input tube, so that a good linear relation from the gate-source voltage of the input tube to the drain-source current is realized, and the gain precision of the dynamic operational amplifier is ensured. While the embodiments have been described with respect to the selection of particular switch types and the selection of signal states, those skilled in the art, having benefit of this disclosure, will appreciate that many other variations and combinations can be made which do not depart from the spirit of the invention as disclosed herein, which still fall within the scope of the invention.
Claims (8)
1. A dynamic operational amplifier circuit with an input tube in a linear region comprises a first switch device, a second switch device, a third switch device, a fourth switch device, a fifth switch device, a sixth switch device, a seventh switch device, a first load capacitor, a second load capacitor, a first sampling capacitor, a second sampling capacitor, a switch control module, a first input tube and a second input tube, wherein the capacitance values of the first load capacitor and the second load capacitor are equal, the capacitance values of the first sampling capacitor and the second sampling capacitor are equal, the first input tube is a first NMOS tube, and the second input tube is a second NMOS tube;
the first connection end of the first switching device is used as a first differential output end of the dynamic operational amplifier circuit and is grounded after passing through the first load capacitor, and the second connection end of the first switching device is connected with the first connection end of the first sampling capacitor and is used as a first middle node;
the first connecting end of the second switching element is used as a second differential output end of the dynamic operational amplifier circuit and is grounded after passing through a second load capacitor, and the second connecting end of the second switching element is connected with the first connecting end of a second sampling capacitor and is used as a second intermediate node;
the second connecting end of the first sampling capacitor is connected with the second connecting end of the second sampling capacitor and the input end of the switch control module and is connected with the power supply voltage after passing through a third switch device;
a fourth switching device coupled between the first intermediate node and the supply voltage and a fifth switching device coupled between the second intermediate node and the supply voltage;
the first connecting end of the sixth switching device is connected with the first connecting end of the seventh switching device, and the second connecting end of the sixth switching device is grounded;
a second connecting end of the seventh switching device is connected with a source electrode of the first NMOS tube and a source electrode of the second NMOS tube, a grid electrode of the first NMOS tube is used as a first differential input end of the dynamic operational amplifier circuit, and a grid electrode of the second NMOS end is used as a second differential input end of the dynamic operational amplifier circuit;
the third switching device, the fourth switching device, the fifth switching device and the sixth switching device are controlled by a clock signal, and when the clock signal is in a first state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched on, and the sixth switching device is controlled to be switched off; when the clock signal is in a second state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched off, and the sixth switching device is controlled to be switched on;
the first switch device, the second switch device and the seventh switch device are controlled by an output signal of the switch control module, the switch control module is used for comparing a voltage value of an input end of the switch control module with a turnover threshold voltage, and when the voltage value of the input end of the switch control module is not lower than the turnover threshold voltage, the output signal of the switch control module controls the first switch device, the second switch device and the seventh switch device to be conducted; when the voltage value of the input end of the switch control module is lower than the overturning threshold voltage, the output signal of the switch control module controls the first switch device, the second switch device and the seventh switch device to be switched off;
the dynamic operational amplifier circuit is characterized by further comprising a third NMOS tube and a fourth NMOS tube;
the grid electrode of the third NMOS tube is connected with bias voltage, the source electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube, and the drain electrode of the third NMOS tube is connected with the first intermediate node;
the grid electrode of the fourth NMOS tube is connected with the bias voltage, the source electrode of the fourth NMOS tube is connected with the drain electrode of the second NMOS tube, and the drain electrode of the fourth NMOS tube is connected with the second intermediate node;
the first NMOS tube and the second NMOS tube work in a linear region, and the third NMOS tube and the fourth NMOS tube work in a saturation region.
2. The dynamic operational amplifier circuit with the input tube in the linear region as claimed in claim 1, wherein the switch control module comprises a first inverter and a second inverter, the input end of the first inverter is connected with the input end of the switch control module, and the output end of the first inverter is connected with the input end of the second inverter; and the output end of the second inverter outputs the output signal of the switch control module.
3. The dynamic operational amplifier circuit with the input tube in the linear region as claimed in claim 2, wherein the seventh switching device is a fifth NMOS tube, the gate of the fifth NMOS tube is connected to the output signal of the switch control module, the source thereof is used as the first connection terminal of the seventh switching device, and the drain thereof is used as the second connection terminal of the seventh switching device.
4. The dynamic operational amplifier circuit with the input tube in the linear region as claimed in any one of claims 1 to 3, wherein the third switching device is a first PMOS tube, the fourth switching device is a second PMOS tube, the fifth switching device is a third PMOS tube, and the sixth switching device is a sixth NMOS tube;
the grid electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are all connected with the clock signal, the source electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are all connected with the power supply voltage, the drain electrode of the first PMOS tube is connected with the input end of the switch control module, the drain electrode of the second PMOS tube is connected with the first intermediate node, and the drain electrode of the third PMOS tube is connected with the second intermediate node;
the grid electrode of the sixth NMOS tube is connected with the clock signal, the drain electrode of the sixth NMOS tube is used as the first connecting end of the sixth switching device, and the source electrode of the sixth NMOS tube is used as the second connecting end of the sixth switching device.
5. A dynamic operational amplifier circuit with an input tube in a linear region comprises a first switch device, a second switch device, a third switch device, a fourth switch device, a fifth switch device, a sixth switch device, a seventh switch device, a first load capacitor, a second load capacitor, a first sampling capacitor, a second sampling capacitor, a switch control module, a first input tube and a second input tube, wherein the capacitance values of the first load capacitor and the second load capacitor are equal, the capacitance values of the first sampling capacitor and the second sampling capacitor are equal, the first input tube is a fourth PMOS tube, and the second input tube is a fifth PMOS tube;
the first connection end of the first switching device is used as a first differential output end of the dynamic operational amplifier circuit and is grounded after passing through the first load capacitor, and the second connection end of the first switching device is connected with the first connection end of the first sampling capacitor and is used as a first middle node;
the first connecting end of the second switching element is used as a second differential output end of the dynamic operational amplifier circuit and is grounded after passing through a second load capacitor, and the second connecting end of the second switching element is connected with the first connecting end of a second sampling capacitor and is used as a second intermediate node;
the second connecting end of the first sampling capacitor is connected with the second connecting end of the second sampling capacitor and the input end of the switch control module and is grounded after passing through a third switch device;
a fourth switching device is connected between the first intermediate node and ground, and a fifth switching device is connected between the second intermediate node and ground;
the first connecting end of the sixth switching device is connected with the first connecting end of the seventh switching device, and the second connecting end of the sixth switching device is connected with power supply voltage;
a second connecting end of the seventh switching device is connected with a source electrode of a fourth PMOS tube and a source electrode of a fifth PMOS tube, a grid electrode of the fourth PMOS tube is used as a first differential input end of the dynamic operational amplifier circuit, and a grid electrode of a second PMOS end is used as a second differential input end of the dynamic operational amplifier circuit;
the third switching device, the fourth switching device, the fifth switching device and the sixth switching device are controlled by a clock signal, and when the clock signal is in a first state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched on, and the sixth switching device is controlled to be switched off; when the clock signal is in a second state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched off, and the sixth switching device is controlled to be switched on;
the first switch device, the second switch device and the seventh switch device are controlled by an output signal of the switch control module, the switch control module is used for comparing a voltage value of an input end of the switch control module with a turnover threshold voltage, and when the voltage value of the input end of the switch control module is not lower than the turnover threshold voltage, the output signal of the switch control module controls the first switch device, the second switch device and the seventh switch device to be conducted; when the voltage value of the input end of the switch control module is lower than the overturning threshold voltage, the output signal of the switch control module controls the first switch device, the second switch device and the seventh switch device to be switched off;
the dynamic operational amplifier circuit is characterized by further comprising a sixth PMOS tube and a seventh PMOS tube;
the grid electrode of the sixth PMOS tube is connected with bias voltage, the source electrode of the sixth PMOS tube is connected with the drain electrode of the fourth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the first intermediate node;
the grid electrode of the seventh PMOS tube is connected with the bias voltage, the source electrode of the seventh PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the second intermediate node;
the fourth PMOS tube and the fifth PMOS tube work in a linear region, and the sixth PMOS tube and the seventh PMOS tube work in a saturation region.
6. The dynamic operational amplifier circuit with the input tube in the linear region as claimed in claim 5, wherein the switch control module comprises a first inverter and a second inverter, the input end of the first inverter is connected with the input end of the switch control module, and the output end of the first inverter is connected with the input end of the second inverter; and the output end of the second inverter outputs the output signal of the switch control module.
7. The dynamic operational amplifier circuit with the input transistor in the linear region as claimed in claim 6, wherein the seventh switching device is an eighth PMOS transistor, the gate of the eighth PMOS transistor is connected to the output signal of the switch control module, the source thereof is the first connection terminal of the seventh switching device, and the drain thereof is the second connection terminal of the seventh switching device.
8. The dynamic operational amplifier circuit with the input tube in the linear region as claimed in any one of claims 5 to 7, wherein the third switching device is a seventh NMOS tube, the fourth switching device is an eighth NMOS tube, the fifth switching device is a ninth NMOS tube, and the sixth switching device is a ninth PMOS tube;
the grid electrodes of the seventh NMOS tube, the eighth NMOS tube and the ninth NMOS tube are all connected with the clock signal, the source electrodes of the seventh NMOS tube, the eighth NMOS tube and the ninth NMOS tube are all grounded, the drain electrode of the seventh NMOS tube is connected with the input end of the switch control module, the drain electrode of the eighth NMOS tube is connected with the first intermediate node, and the drain electrode of the ninth NMOS tube is connected with the second intermediate node;
the gate of the ninth PMOS transistor is connected to the clock signal, the drain of the ninth PMOS transistor is used as the first connection terminal of the sixth switching device, and the source of the ninth PMOS transistor is used as the second connection terminal of the sixth switching device.
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