CN210670009U

CN210670009U - High-speed pre-amplification latch comparator with low dynamic mismatch

Info

Publication number: CN210670009U
Application number: CN201922176927.1U
Authority: CN
Inventors: 黄晶; 朱从益; 赵莉; 只生武
Original assignee: Nanjing Derui Zhixin Electronic Technology Co ltd
Current assignee: Nanjing Derui Zhixin Electronic Technology Co ltd
Priority date: 2019-12-06
Filing date: 2019-12-06
Publication date: 2020-06-02
Anticipated expiration: 2029-12-06

Abstract

The utility model discloses a low high-speed pre-amplification of dynamic mismatch latches comparator, include: the preamplifier is used for amplifying the input differential signal; a latch for comparing the amplified differential signals; the preamplifier comprises a differential input pair and an active load, wherein the active load adopts an active inductance load comprising a load tube pair, a load capacitor pair and a load resistor pair and is used for compensating the gain and the phase of a high-frequency input signal; the latch includes a first amplification unit and a second amplification unit cross-coupled via a coupling capacitor; a reset tube is connected between the first amplification unit and the second amplification unit. The utility model provides a high-speed latch comparator that enlargies in advance when not increasing extra consumption, can reduce the dynamic mismatch because the sampling path difference arouses effectively. Furthermore, the introduction of cross-coupling capacitance in the latch may reduce the static offset of the comparator and increase the speed of the latch.

Description

High-speed pre-amplification latch comparator with low dynamic mismatch

Technical Field

The utility model relates to an integrated circuit, concretely relates to high-speed pre-amplification of low dynamic mismatch latches comparator.

Background

The comparator converts an input Analog signal into a Digital signal, and is widely used in an Analog-to-Digital Converter (ADC) and other circuits. Pre-amplified latching comparators are often used because of their ability of pre-preamplifier to amplify an input analog signal, isolate the effect of digital output on the input signal, and fast comparison latching of the latch. With the rapid development of digital communication, the requirements for speed, accuracy and power consumption of analog-to-digital converters in practical applications are continuously increased. Among many ADC architectures, a pipeline ADC architecture without a sample-and-hold circuit is widely adopted because it has the advantages of high speed and high precision, and because there is no sample-and-hold circuit, it can save much power consumption and area.

In a high-speed and high-precision pipeline ADC without a sample-and-hold circuit, a first-stage sub-circuit multiplication Digital-to-Analog Converter (MDAC) and a sub-ADC (sub-ADC) adopting a fully parallel (Flash) ADC respectively sample an input signal, and when a high-frequency signal is input, because the sample-and-hold circuit is not arranged in the front, the sampling bandwidths of two paths and the performance of the dynamic mismatch pair ADC are greatly influenced, wherein the dynamic mismatch is the phase deviation of the sampling signal generated by different sampling paths of latches in the MDAC and the Flash ADC comparator at the end moment of a clock sampling phase. Although the dual-switch capacitor sampling preamplification latching comparator can better meet the dynamic mismatch requirement, the charge redistribution after sampling occupies the establishment time of the MDAC, and the performance requirement is difficult to meet in a high-speed ADC. In addition, a preamplifier with a high enough bandwidth can solve the problem of dynamic mismatch in theory, but is difficult to implement in a higher speed ADC and consumes additional power.

SUMMERY OF THE UTILITY MODEL

Utility model purpose: the application provides a low-dynamic-mismatch high-speed pre-amplification latching comparator which is used for solving the problem of dynamic mismatch caused by different sampling paths in the conventional ADC.

The technical scheme is as follows: the utility model provides a low high-speed pre-amplification of dynamic mismatch latches comparator, include: the preamplifier is used for amplifying the input differential signal; and the latch is connected with the output of the preamplifier and used for comparing the amplified differential signals.

The preamplifier comprises a differential input pair and an active load, wherein the active load adopts an active inductance load comprising a load tube pair, a load capacitor pair and a load resistor pair and is used for compensating the gain and the phase of a high-frequency input signal; the latch includes a first amplification unit and a second amplification unit cross-coupled via a coupling capacitor; a reset tube is connected between the first amplification unit and the second amplification unit.

Further, the differential input pair comprises a first NMOS transistor (MN1) and a second NMOS transistor (MN2), gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) respectively receive the differential input signal, and sources are connected to the bias current.

Further, the preamplifier further comprises a bias current source, which comprises a third NMOS transistor (MN3), the grid electrode of which is connected with a bias voltage, the source electrode of which is grounded, and the drain electrode of which is connected with the source electrodes of the first NMOS transistor (MN1) and the second NMOS transistor (MN2), and the bias current source is used for providing bias current for the differential input pair.

Further, the load tube pair comprises a first PMOS tube (MP1) and a second PMOS tube (MP2), the sources of the first PMOS tube and the second PMOS tube are connected to the power supply (VDD) in common, and the drains of the first PMOS tube and the second PMOS tube are respectively connected to the drain of the first NMOS tube and the drain of the second NMOS tube;

the load capacitance pair comprises a first load capacitance (C1) and a second load capacitance (C2); two pole plates of a first load capacitor (C1) are respectively connected with the grid electrode and the source electrode of the first PMOS tube, and two pole plates of a second load capacitor (C2) are respectively connected with the grid electrode and the source electrode of the second PMOS tube;

the load resistance pair comprises a first load resistance (R1) and a second load resistance (R2); two ends of the first load resistor (R1) are respectively connected with the grid electrode and the drain electrode of the first PMOS tube, and two ends of the second load resistor (R2) are respectively connected with the grid electrode and the drain electrode of the second PMOS tube.

Furthermore, the latch further comprises a first input circuit and a second input circuit, which respectively comprise a fourth NMOS transistor (MN4) and a fifth NMOS transistor (MN5), sources of the first input circuit and the second input circuit are respectively connected with the differential output signal of the preamplifier, gates of the first input circuit and the fifth input circuit are both connected with a clock signal, and drain outputs of the first input circuit and the second input circuit are respectively used as inputs of the first amplifying unit and the second amplifying unit.

Further, the coupling capacitance includes a first coupling capacitance (C3) and a second coupling capacitance (C4); the first amplification unit comprises a third PMOS (MP3) and a sixth NMOS (MN6), and the second amplification unit comprises a fourth PMOS (MP4) and a seventh NMOS (MN 7);

a first coupling capacitor (C3) is coupled between the gates of the third PMOS transistor (MP3) and the sixth NMOS transistor (MN6), and the gate of the sixth NMOS transistor (MN6) is connected to the drains of the fourth PMOS transistor (MP4) and the seventh NMOS transistor (MN 7); a second coupling capacitor (C4) is coupled between the gates of the fourth PMOS transistor (MP4) and the seventh NMOS transistor (MN7), and the gate of the seventh NMOS transistor (MN7) is connected to the drains of the third PMOS transistor (MP3) and the sixth NMOS transistor (MN 6);

the source electrodes of the third PMOS tube (MP3) and the fourth PMOS tube (MP4) are connected with a power supply (VDD), and the source electrodes of the sixth NMOS tube (MN6) and the seventh NMOS tube (MN7) are grounded.

Furthermore, the drain of the fourth NMOS transistor (MN4) is connected to the gate of the third PMOS transistor (MP3), and the drain of the fifth NMOS transistor (MN5) is connected to the gate of the fourth PMOS transistor (MP 4).

Furthermore, the reset transistor adopts an eighth NMOS transistor (MN8), the source of which is connected to the drains of the third PMOS transistor (MP3) and the sixth NMOS transistor (MN6), the drain of which is connected to the drains of the fourth PMOS transistor (MP4) and the seventh NMOS transistor (MN7), and the gate of which is connected to the clock signal.

Has the advantages that: compared with the prior art, the utility model provides a high-speed preamplifier latch comparator introduces in leading preamplifier by the load pipe right, and load capacitance is right and load resistance is to the active inductance load of constitution, when not increasing extra consumption, can reduce effectively because the different dynamic mismatch that arouses of sampling path. Furthermore, the introduction of cross-coupling capacitance in the latch may reduce the static offset of the comparator and increase the speed of the latch. The comparator can be applied to a pipelined ADC with a high-speed high-precision non-sampling hold circuit, and can effectively improve the speed and the bandwidth of the ADC.

Drawings

FIG. 1 is a schematic diagram of a pre-amplification latch comparator according to the present invention;

fig. 2 is a waveform diagram of a transient simulation of a comparator before an active inductive load is introduced;

fig. 3 is a waveform diagram of a transient simulation of the comparator after the comparator of the present invention has been introduced into an active inductive load;

fig. 4 is a transient simulation waveform diagram of the comparator under different input signal amplitudes;

fig. 5 is a waveform diagram of the transient simulation of the comparator under different temperature conditions.

Detailed Description

The invention will be further described with reference to the following figures and examples:

the application provides a low-dynamic mismatch high-speed pre-amplification latch comparator, as shown in fig. 1, which comprises a pre-amplifier and a latch, wherein the pre-amplifier amplifies an input differential signal; and the latch is connected with the output of the preamplifier and compares the amplified differential signals.

The preamplifier includes a differential input pair 101 and an active load 102; the differential input pair comprises a first NMOS transistor (MN1) and a second NMOS transistor (MN2), the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) respectively receive differential input signals vip and vin, and the sources are connected with bias current. In this embodiment, the bias current source of the preamplifier includes a third NMOS transistor (MN3), the gate of which is connected to the bias voltage vb, the source of which is grounded GND, and the drain of which is connected to the sources of the first NMOS transistor (MN1) and the second NMOS transistor (MN2), so as to provide bias current for the differential input pair.

The active load 102 employs an active inductive load comprising a pair of load tubes, a pair of load capacitors, and a pair of load resistors. The load tube pair comprises a first PMOS tube (MP1) and a second PMOS tube (MP2), the sources of the first PMOS tube and the second PMOS tube are connected to a power supply (VDD) in common, and the drains of the first PMOS tube and the second PMOS tube are respectively connected to the drain of the first NMOS tube and the drain of the second NMOS tube. The load capacitance pair comprises a first load capacitance (C1) and a second load capacitance (C2); two polar plates of a first load capacitor (C1) are respectively connected with the grid electrode and the source electrode of the first PMOS tube, and two polar plates of a second load capacitor (C2) are respectively connected with the grid electrode and the source electrode of the second PMOS tube. The load resistance pair comprises a first load resistance (R1) and a second load resistance (R2); two ends of the first load resistor (R1) are respectively connected with the grid electrode and the drain electrode of the first PMOS tube, and two ends of the second load resistor (R2) are respectively connected with the grid electrode and the drain electrode of the second PMOS tube. In the present embodiment, the amplified differential signal is output from the drains of the differential input pair, i.e., the output nodes pon and pop of fig. 1.

The active inductive load is composed of the MP1, the MP2, the C1, the C2, the R1 and the R2, a zero point of a left half plane is introduced during small signal model analysis, and when the position of the zero point is adjusted to be close to the position of a main pole point of a circuit, gain and phase of a signal input higher than the frequency of the main pole point can be compensated, so that dynamic mismatch caused by different sampling paths in the ADC is effectively reduced. In addition, an active inductive load introduced into the preamplifier consists of a POMS (point of presence) tube and a resistor capacitor instead of an NMOS (N-channel metal oxide semiconductor) tube, so that the output dynamic range of the preamplifier can be improved as much as possible, and the distortion under the condition of inputting a large signal is reduced.

In the present embodiment, the latch includes a first input circuit, a second input circuit, and a first amplification unit 103 and a second amplification unit 104 that are cross-coupled via coupling capacitances (the coupling capacitances include a first coupling capacitance C3 and a second coupling capacitance C4). As shown in fig. 1, the first input circuit includes a fourth NMOS transistor (MN4), the second input circuit includes a fifth NMOS transistor (MN5), and the sources thereof are respectively connected to the differential output signal of the preamplifier, i.e., the source of MN4 is connected to the node pon, and the source of MN5 is connected to the node pop; the grid electrodes are connected with a clock signal latchb, and the output of the drain electrodes of the grid electrodes and the drain electrodes of the grid electrodes are respectively used as the input of the first amplifying unit and the second amplifying unit.

The first amplifying unit comprises a third PMOS (MP3) and a sixth NMOS (MN6), and the second amplifying unit comprises a fourth PMOS (MP4) and a seventh NMOS (MN 7). A first coupling capacitor C3 is coupled between the gates of the MP3 and the MN6, and the gate of the MN6 is connected to the drains of the MP4 and the MN 7; a second coupling capacitor C4 is coupled between the gates of MP4 and MN7, and the gate of MN7 is connected to the drains of MP3 and MN 6. The sources of MP3 and MP4 are connected to VDD, and the sources of MN6 and MN7 are connected to ground. The introduction of the cross coupling capacitors C3 and C4 can not only improve the gate-source voltage of the two pairs of cross coupling transistors, thereby improving the comparison speed of the latch, but also play a role in memory and greatly reducing the static disorder of the comparator.

As shown in fig. 1, in the present embodiment, the gates of MP3 and MP4 are used as the input nodes ponx and popx of the latch, the drain of the fourth NMOS transistor (MN4) is connected to the input node ponx of the latch, and the drain of the fifth NMOS transistor (MN5) is connected to the input node popx of the latch. The input points of the latches are set as the gates of the PMOS transistors MP3 and MP4 so as to match the static operating point with the active inductive load of the preamplifier.

A reset tube is connected between the first amplification unit 103 and the second amplification unit 104. As shown in fig. 1, in this embodiment, the reset transistor is an eighth NMOS transistor (MN8), the source of the reset transistor is connected to the drains of the third PMOS transistor (MP3) and the sixth NMOS transistor (MN6), the drain of the reset transistor is connected to the drains of the fourth PMOS transistor (MP4) and the seventh NMOS transistor (MN7), and the gate of the reset transistor is connected to the clock signal latchb. Here, the NMOS transistor MN8 may be a smaller NMOS transistor, and its equivalent resistance and the introduced pair of cross-coupled capacitors C3 and C4 form a positive feedback while ensuring the reset effect, and may also play a part of the phase advancing role.

In the circuit of fig. 1, the preamplifier introduces an active inductive load composed of PMOS transistors MP1 and MP2, capacitors C1 and C2, and resistors R1 and R2 based on a typical common source amplifier, and two paths of equivalent impedances can be represented by calculating:

wherein R is₁、R₂Resistance values of the resistors R1, R2, C₁、C₂The capacitance values, gm, of the capacitors C1, C2, respectively_p1、gm_p2The transconductances of the PMOS transistors MP1 and MP2, respectively.

Get R₁＝R₂＝R,C₁＝C₂＝C,gm_p1＝gm_p2Gm, then:

when the small signal model of the comparator is analyzed, a zero point of a left half plane can be introduced into the active inductive load, and when the zero point position is close to the main pole position of the circuit by adjusting the corresponding parameter values of the PMOS tubes MP1 and MP2, the capacitors C1 and C2 and the resistors R1 and R2, the gain and the phase can be compensated for the signal input with the frequency higher than the main pole.

Before the actual circuit simulation design, the maximum phase deviation of the comparator sampling which can meet the dynamic mismatch requirement is calculated through derivation. Suppose the input signal is V_in＝V_refsin(2πf_int) in which V_refIs a reference voltage, f_inFor signal frequency, there is a maximum deviation V of the sampled signal_errmaxComprises the following steps:

V_errmax＝2πf_maxV_refΔt

wherein f is_maxIn order to meet the maximum frequency required by the index, delta t is the time deviation corresponding to the sampling of the Flash ADC comparator and the sampling of the MDAC. Taking a first-stage 2.5-bit structure pipelined ADC without sample hold as an example, it needs to satisfy:

wherein, alpha is the proportion of the dynamic mismatch to the whole circuit mismatch, the whole mismatch comprises the static mismatch of the comparator in addition to the dynamic mismatch, the resistance network mismatch generating the reference voltage of the Flash ADC, clock jitter, layout mismatch and the like

Then there are:

when f is_maxAt 500MHz, an approximation of Δ t < 13.3ps is obtained. The same can be derived that the sampling phase deviation needs to satisfy:

the phase deviation requirement can be theoretically met for a preamplifier with a sufficiently high bandwidth, and the following requirements are met:

wherein f is_BWmaxMaximum bandwidth of preamplifier, when f_maxWhen 500MHz, the same applies

Then approximate to f_BWmaxApproximately 12GHz, which is difficult to implement in the design and also adds much extra power consumption. The utility model discloses in adopted the aforesaid method of introducing active inductance makes gain and phase place obtain effective compensation when the high frequency.

In an actual simulation experiment, after stability (stb) simulation optimization is performed on a small signal model of a comparator, transient simulation is performed on the comparator, in order to quantitatively analyze phase deviation, an ideal sinusoidal signal with a frequency of 500MHZ is used as an input, and differential signals of input nodes ponx and popx of a latch passing through switch NMOS tubes MN4 and MN5 are used as output observation signals. Fig. 2 and fig. 3 are transient waveform diagrams of phase deviation relationship between input and output signals before and after the preamplifier introduces an active inductive load, respectively, and it can be seen that the phase deviation relationship is obviously improved.

The utility model discloses an active inductance load that the comparator introduced chooses for use the PMOS pipe, can improve preamplifier's output dynamic range, be the transient state emulation oscillogram under the different input signal amplitude circumstances as shown in fig. 4, can see that phase deviation is also less under the large-signal circumstances. Fig. 5 shows simulated waveforms of transients at different temperatures, which include the phase deviation relationships between the input and output at-40 degrees, 65 degrees and 125 degrees. The phase deviation obtained by simulation under each condition can meet the requirement of the maximum phase deviation calculated in the prior art.

The sampling phase deviation optimization effect shows that the offset of a transmission characteristic curve is reduced, the equivalent threshold voltage error is reduced, the offset deviation is within a digital calibration range, and the transient output between stages of the whole ADC is established within a certain range and cannot overflow.

To sum up, the utility model discloses a sampling dynamic mismatch problem that exists in the pipelined ADC of high-speed high accuracy no sample hold circuit can be solved well to the comparator, reduces sampling dynamic mismatch error when not increasing extra consumption effectively, improves the speed and the bandwidth of whole ADC.

Claims

1. A high speed pre-amplified latching comparator with low dynamic mismatch, comprising:

the preamplifier is used for amplifying the input differential signal;

the latch is connected with the output of the preamplifier and used for comparing the amplified differential signals;

the preamplifier comprises a differential input pair and an active load, wherein the active load adopts an active inductance load comprising a load tube pair, a load capacitor pair and a load resistor pair and is used for compensating the gain and the phase of a high-frequency input signal;

the latch includes a first amplification unit and a second amplification unit cross-coupled via a coupling capacitance; and a reset tube is connected between the first amplification unit and the second amplification unit.

2. The high speed pre-amplified latch comparator according to claim 1, wherein the differential input pair comprises a first NMOS transistor (MN1) and a second NMOS transistor (MN2), the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) respectively receive the differential input signal, and the sources are connected with the bias current.

3. The high speed pre-amplified latch comparator according to claim 2, wherein the pre-amp further comprises a bias current source including a third NMOS transistor (MN3) having a gate connected to a bias voltage, a source connected to ground, and a drain connected to the sources of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) for providing a bias current to the differential input pair.

4. The high speed pre-amplified latch comparator according to claim 2, wherein the pair of load transistors comprises a first PMOS transistor (MP1) and a second PMOS transistor (MP2), the sources of which are commonly connected to a power supply (VDD), and the drains of which are respectively connected to the drain of the first NMOS transistor and the drain of the second NMOS transistor;

the load capacitance pair comprises a first load capacitance (C1) and a second load capacitance (C2); the bipolar plates of the first load capacitor (C1) are respectively connected with the grid electrode and the source electrode of the first PMOS tube, and the bipolar plates of the second load capacitor (C2) are respectively connected with the grid electrode and the source electrode of the second PMOS tube;

the pair of load resistors comprises a first load resistor (R1) and a second load resistor (R2); two ends of the first load resistor (R1) are respectively connected with the grid electrode and the drain electrode of the first PMOS tube, and two ends of the second load resistor (R2) are respectively connected with the grid electrode and the drain electrode of the second PMOS tube.

5. The high-speed pre-amplified latching comparator according to claim 1, wherein the latch further comprises a first input circuit and a second input circuit, each comprising a fourth NMOS transistor (MN4) and a fifth NMOS transistor (MN5), the sources of which are respectively connected to the differential output signal of the pre-amplifier, the gates of which are both connected to the clock signal, and the drain outputs of which are respectively used as the inputs of the first amplifying unit and the second amplifying unit.

6. The high-speed pre-amplified latching comparator according to claim 5, wherein the coupling capacitor comprises a first coupling capacitor (C3) and a second coupling capacitor (C4);

the first amplification unit comprises a third PMOS (MP3) and a sixth NMOS (MN6), and the second amplification unit comprises a fourth PMOS (MP4) and a seventh NMOS (MN 7);

a first coupling capacitor (C3) is coupled between the gates of the third PMOS transistor (MP3) and the sixth NMOS transistor (MN6), and the gate of the sixth NMOS transistor (MN6) is connected to the drains of the fourth PMOS transistor (MP4) and the seventh NMOS transistor (MN 7);

a second coupling capacitor (C4) is coupled between the gates of the fourth PMOS transistor (MP4) and the seventh NMOS transistor (MN7), and the gate of the seventh NMOS transistor (MN7) is connected to the drains of the third PMOS transistor (MP3) and the sixth NMOS transistor (MN 6);

7. The high speed pre-amplified latch comparator according to claim 6, wherein the drain of the fourth NMOS transistor (MN4) is connected to the gate of the third PMOS transistor (MP3), and the drain of the fifth NMOS transistor (MN5) is connected to the gate of the fourth PMOS transistor (MP 4).

8. The high speed pre-amplified latch comparator according to claim 6, wherein the reset transistor is an eighth NMOS transistor (MN8), the source thereof is connected to the drains of the third PMOS transistor (MP3) and the sixth NMOS transistor (MN6), the drain thereof is connected to the drains of the fourth PMOS transistor (MP4) and the seventh NMOS transistor (MN7), and the gate thereof is connected to the clock signal.