CN115333515A - Dynamic comparator with low kickback noise - Google Patents
Dynamic comparator with low kickback noise Download PDFInfo
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- CN115333515A CN115333515A CN202210769743.XA CN202210769743A CN115333515A CN 115333515 A CN115333515 A CN 115333515A CN 202210769743 A CN202210769743 A CN 202210769743A CN 115333515 A CN115333515 A CN 115333515A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
Abstract
The invention discloses a dynamic comparator with low kickback noise. The dynamic comparator comprises a first-stage tailless current switching tube double-latch amplifying circuit, a second-stage dynamic latch and a time delay trigger. The pre-amplifying circuit has no tail current source, the source electrode of the differential input tube is grounded, and common-mode kickback noise caused by the fact that the source electrode voltage is discharged to the ground from the power supply voltage when the traditional dynamic comparator is used for comparison is avoided. And the second-stage dynamic latch compares the output of the first-stage amplifying circuit to obtain a final comparison result. The delay trigger is responsible for starting the second-stage dynamic latch at the position where the first-stage pre-amplifying circuit outputs the highest value. Because the tail current switch tube is not arranged, the source electrode potential of the input tube is fixed at the ground potential, and the drain electrode potential is close to the ground potential, the invention can effectively weaken kickback noise of the dynamic comparator on the premise of not sacrificing noise and comparator speed, and is suitable for a high-precision successive approximation type analog-to-digital converter.
Description
Technical Field
The invention relates to the technical field of analog integrated circuits, in particular to a dynamic comparator with low kickback noise.
Background
The analog-to-digital converter is a bridge connecting the real world and the digital world, and has wide application in the field of signal acquisition and processing. In the field of signal acquisition, a high-precision analog-to-digital converter plays an important role. The high-precision analog-to-digital converter mainly includes an oversampling analog-to-digital converter and a successive approximation type analog-to-digital converter, and the successive approximation type analog-to-digital converter receives a great deal of attention due to its high degree of digitization and low power consumption. As the precision of successive approximation analog-to-digital converters is continuously improved, comparator noise becomes a major limiting factor limiting the analog-to-digital converters. Among them, the kickback noise of the dynamic comparator seriously affects the noise performance of the comparator.
FIG. 1 is a circuit diagram of a conventional Strong-Arm dynamic comparator. In the reset stage, the tail current switch tube is turned off, no current flows through the input tubes M1 and M2, so that the potential of the node P is high, and the potentials of the nodes X and Y are high level. When the rising edge of the clock signal comes, the tail current switch tube is turned on, the potential of the node P is discharged to the ground, the voltage change of the node is coupled to the input end of the comparator through the gate-source parasitic capacitance of the input tubes M1 and M2, and the voltage coupled to the gate of M1 is different from the voltage coupled to the gate of M2 due to the impedance difference between the input end of the comparator and the ground, i.e. a dynamic offset (Noise _ Analysis _ of _ regeneration _ Comparators _ for _ reconfiguration _ ADC _ circuits) is generated at the input end of the comparator.
Disclosure of Invention
In order to solve the problems of kickback noise and dynamic maladjustment of the traditional Strong-Arm comparator, the invention provides a dynamic comparator with low kickback noise.
The purpose of the invention is realized by at least one of the following technical solutions.
A low kickback noise dynamic comparator suitable for a high-precision successive approximation type analog-to-digital converter comprises a first-stage tailless current switching tube double-latch pre-amplifying circuit, a second-stage dynamic latch and a time delay trigger;
the first-stage tailless current switching tube double-latch pre-amplifying circuit comprises a first output node, a second output node, a third output node and a fourth output node;
the second-stage dynamic latch comprises a fifth output node, a sixth output node, a first input node, a second input node, a third input node and a fourth input node;
the delay flip-flop comprises an output node;
the first-stage tailless current switch tube double-latch pre-amplification circuit receives a first input differential signal and a second input differential signal; a first input node, a second input node, a third input node and a fourth input node of the second-stage dynamic latch are respectively connected with a first output node, a second output node, a third output node and a fourth output node; the delay trigger is respectively connected with the first output node, the second output node, the third output node, the fourth output node, the fifth output node and the sixth output node;
before a clock signal does not arrive, the dynamic comparator is in a reset stage, and a first output node, a second output node, a third output node and a fourth output node of the first-stage tailless current switching tube double-latch pre-amplification circuit are discharged to the ground potential, namely low level; the output node of the delay trigger is charged to a high level; the fifth output node and the sixth output node of the second stage dynamic latch are discharged to ground potential;
the dynamic comparator is in a comparison stage after a clock signal arrives, the first-stage tailless current switch tube double-latch pre-amplification circuit amplifies input first input differential signals and second input differential signals, and the delay trigger triggers the second-stage dynamic latch to compare and latch output voltages of the first-stage tailless current switch tube double-latch pre-amplification circuit and output the comparison results.
Further, the first-stage tailless current switching tube double-latch pre-amplifying circuit comprises a plurality of input tubes, a plurality of reset discharge tubes controlled by clock signals, a first latch, a second latch and a plurality of offset voltage injection transistors;
the first latch and the second latch take a differential input tube as a source negative feedback resistor and are formed by connecting phase inverters end to end;
in the first-stage tailless current switching tube double-latch pre-amplification circuit, in a reset stage, a first output node, a second output node, a third output node and a fourth output node are discharged to the ground potential; in the comparison stage, the reset discharge tubes are turned off, the offset voltage injection transistors are turned on, offset voltages with the same magnitude are injected into the first latch and the second latch, and when the voltages of the first output node, the second output node, the third output node and the fourth output node are raised to the threshold voltage of the NMOS tube, the first latch and the second latch are turned on and quickly amplify the offset voltages of the first output node, the second output node, the third output node and the fourth output node;
an input tube in the first-stage tailless current switching tube double-latch pre-amplifying circuit works in a linear resistance area and is used as a source negative feedback resistance of NMOS tubes in the first latch and the second latch to influence the voltage amplifying speed of the first latch and the second latch; the higher the gate voltage of the input tube is, the smaller the linear resistance is, and the faster the amplification speed of the first latch and the second latch is.
Further, the first-stage tailless current switch tube double-latch pre-amplifying circuit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube;
the first NMOS tube is a first input tube, the second NMOS tube is a second input tube, the third NMOS tube is a third input tube, and the fourth NMOS tube is a fourth input tube; the ninth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube, the thirteenth NMOS tube and the fourteenth NMOS tube are reset discharge tubes; a fifth NMOS tube, a sixth NMOS tube, a third PMOS tube and a fourth PMOS tube form a first latch; a seventh NMOS tube, an eighth NMOS tube, a fifth PMOS tube and a sixth PMOS tube form a second latch; the first PMOS tube and the second PMOS tube are both offset voltage injection transistors.
Furthermore, the grids of the first NMOS tube and the second NMOS tube are connected with a first input differential signal, the sources of the first NMOS tube and the second NMOS tube are grounded, the drain of the first NMOS tube is connected with the source of the fifth NMOS tube, and the drain of the second NMOS tube is connected with the source of the sixth NMOS tube; the grid electrodes of the third NMOS tube and the fourth NMOS tube are connected with a second input differential signal, the source electrodes of the third NMOS tube and the fourth NMOS tube are grounded, the drain electrode of the third NMOS tube is connected with the source electrode of the seventh NMOS tube, and the drain electrode of the fourth NMOS tube is connected with the source electrode of the eighth NMOS tube;
the grid electrode of the fifth NMOS tube is used as a second output node, and the drain electrode of the fifth NMOS tube is used as a first output node; the grid electrode of the sixth NMOS tube is connected with the first output node, and the drain electrode of the sixth NMOS tube is connected with the second output node;
the grid electrode of the seventh NMOS tube is used as a fourth output node, and the drain electrode of the seventh NMOS tube is used as a third output node; the grid electrode of the eighth NMOS tube is connected with the third output node, and the drain electrode of the eighth NMOS tube is connected with the fourth output node; the drain electrode of the ninth NMOS tube is connected with the first output node, and the grid electrode of the ninth NMOS tube is connected with the inverted signal of the clock signal; the drain electrode of the tenth NMOS tube is connected with the second output node, and the grid electrode of the tenth NMOS tube is connected with the inverted signal of the clock signal; the drain electrode of the eleventh NMOS tube is connected with the third output node, and the grid electrode of the eleventh NMOS tube is connected with the inverted signal of the clock signal; the drain electrode of the twelfth NMOS tube is connected with the fourth output node, and the grid electrode of the twelfth NMOS tube is connected with the inverted signal of the clock signal; the grid electrode of the thirteenth NMOS tube is connected with the inverted signal of the clock signal, the source electrode of the thirteenth NMOS tube is grounded, and the drain electrode of the thirteenth NMOS tube is connected with the drain electrode of the second PMOS tube; the grid electrode of the fourteenth NMOS tube is connected with the inverted signal of the clock signal, the source electrode of the fourteenth NMOS tube is grounded, and the drain electrode of the fourteenth NMOS tube is connected with the drain electrode of the first PMOS tube; the grid electrode of the first PMOS tube is connected with the inverted signal of the clock signal, the source electrode of the first PMOS tube is externally connected with power supply voltage, and the drain electrode of the first PMOS tube is connected with the source electrodes of the fourth PMOS tube and the sixth PMOS tube; the grid electrode of the second PMOS tube is connected with the inverted signal of the clock signal, the source electrode is externally connected with power supply voltage, and the drain electrode is connected with the source electrodes of the third PMOS tube and the fifth PMOS tube; the grid electrode of the third PMOS tube is connected with the second output node, the source electrode is connected with the drain electrode of the second PMOS tube, and the drain electrode is connected with the first output node; the grid electrode of the fourth PMOS tube is connected with the first output node, the source electrode of the fourth PMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the second output node; the grid electrode of the fifth PMOS tube is connected with the fourth output node, the source electrode of the fifth PMOS tube is connected with the drain electrode of the second PMOS tube, and the drain electrode of the fifth PMOS tube is connected with the third output node; the grid electrode of the sixth PMOS tube is connected with the third output node, the source electrode of the sixth PMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the fourth output node.
Furthermore, the time delay trigger comprises a charging tube controlled by a clock signal and four discharge tubes controlled by the output node of the first-stage tailless current switching tube double-latch pre-amplifying circuit;
the delay trigger comprises a fifteenth NMOS (N-channel metal oxide semiconductor) tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube and a seventh PMOS tube;
the fifteenth NMOS tube, the sixteenth NMOS tube, the seventeenth NMOS tube and the eighteenth NMOS tube are discharge tubes, and the seventh PMOS tube is a charging tube;
the grid electrode of the fifteenth NMOS tube is connected with the first output node of the first-stage tailless current switching tube double-latch pre-amplifying circuit, and the source electrode of the fifteenth NMOS tube is grounded; the grid electrode of a sixteenth NMOS tube is connected with a second output node of the double-latch pre-amplifying circuit of the first-stage tailless current switch tube, and the source electrode of the sixteenth NMOS tube is grounded; the grid electrode of the seventeenth NMOS tube is connected with the third output node of the first-stage tailless current switching tube double-latch pre-amplifying circuit, and the source electrode is grounded; the grid electrode of the eighteenth NMOS tube is connected with the fourth output node of the double-latch pre-amplifying circuit of the first-stage tailless current switch tube, and the source electrode of the eighteenth NMOS tube is grounded; the drain electrodes of the fifteenth NMOS tube, the sixteenth NMOS tube, the seventeenth NMOS tube and the eighteenth NMOS tube are all connected with the drain electrode of the seventh PMOS tube and serve as the output node of the delay trigger; the grid electrode of the seventh PMOS tube is connected with the clock signal, and the source electrode of the seventh PMOS tube is externally connected with the power supply voltage.
Furthermore, the delay trigger is charged through a seventh PMOS tube in a reset stage, and outputs a high level; in the comparison stage, when any output node of the first-stage tailless current switch tube double-latch pre-amplification circuit is charged to the threshold voltage of the NMOS tube, the NMOS tube connected with the output node in the delay trigger is conducted, the output node of the delay trigger is discharged, the ground potential is output after a period of time, the second-stage dynamic latch is triggered to compare the output voltage of the first-stage tailless current switch tube double-latch pre-amplification circuit, and the final comparison result is obtained.
Further, the second-stage dynamic latch comprises a nineteenth NMOS transistor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, a twenty-fourth NMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor and a fourteenth PMOS transistor;
the grid electrode of the eighth PMOS tube is a first input node of the second-stage dynamic latch and is connected with a first output node of the first-stage tailless current switching tube double-latch pre-amplifying circuit; the source electrode of the eighth PMOS tube is connected with the drain electrode of the fourteenth PMOS tube, and the drain electrode of the eighth PMOS tube is connected with the source electrode of the twelfth PMOS tube; the grid electrode of the ninth PMOS tube is a second input node of the second-stage dynamic latch and is connected with a fourth output node of the double-latch pre-amplifying circuit of the first-stage tailless current switching tube; the source electrode of the ninth PMOS tube is connected with the drain electrode of the fourteenth PMOS tube, and the drain electrode of the ninth PMOS tube is connected with the source electrode of the twelfth PMOS tube; the grid electrode of the tenth PMOS tube is a third input node of the second-stage dynamic latch and is connected with a second output node of the first-stage tailless current switching tube double-latch pre-amplifying circuit; the source electrode of the tenth PMOS tube is connected with the drain electrode of the fourteenth PMOS tube, and the drain electrode of the tenth PMOS tube is connected with the source electrode of the thirteenth PMOS tube; the grid electrode of the eleventh PMOS tube is a fourth input node of the second-stage dynamic latch and is connected with a third output node of the first-stage tailless current switching tube double-latch pre-amplifying circuit; the source electrode of the eleventh PMOS tube is connected with the drain electrode of the fourteenth PMOS tube, and the drain electrode of the eleventh PMOS tube is connected with the source electrode of the thirteenth PMOS tube; the grid electrode of the twelfth PMOS tube is connected with the fifth output node of the second-stage dynamic latch, and the drain electrode of the twelfth PMOS tube is connected with the sixth output node of the second-stage dynamic latch; the grid electrode of the thirteenth PMOS tube is connected with the sixth output node of the second-stage dynamic latch, and the drain electrode of the thirteenth PMOS tube is connected with the fifth output node of the second-stage dynamic latch; the grid electrode of the fourteenth PMOS tube is connected with the output node of the time delay trigger, the source electrode of the fourteenth PMOS tube is grounded, and the drain electrode of the fourteenth PMOS tube is connected with the source electrodes of the eighth PMOS tube, the ninth PMOS tube, the tenth PMOS tube and the eleventh PMOS tube; the grid electrode of the nineteenth NMOS tube is connected with the output node of the delay trigger, the source electrode of the delay trigger is grounded, and the drain electrode of the delay trigger is connected with the negative output node; the grid electrode of the twentieth NMOS tube is connected with the fifth output node of the second-stage dynamic latch, the source electrode of the twentieth NMOS tube is grounded, and the drain electrode of the twentieth NMOS tube is connected with the sixth output node of the second-stage dynamic latch; the grid electrode of the twenty-first NMOS tube is connected with the sixth output node of the second-stage dynamic latch, the source electrode of the twenty-first NMOS tube is grounded, and the drain electrode of the twenty-first NMOS tube is connected with the fifth output node of the second-stage dynamic latch; the grid electrode of the twenty-second NMOS tube is connected with the output node of the delay trigger, the source electrode of the delay trigger is grounded, and the drain electrode of the delay trigger is connected with the fifth output node of the second-stage dynamic latch; the grid electrode of the twenty-third NMOS tube is connected with the output node of the delay trigger, the source electrode of the delay trigger is grounded, and the drain electrode of the delay trigger is connected with the source electrode of the twelfth PMOS tube; the grid electrode of the twenty-fourth NMOS tube is connected with the output node of the delay trigger, the source electrode of the delay trigger is grounded, and the drain electrode of the delay trigger is connected with the source electrode of the thirteenth PMOS tube.
Furthermore, the fourteenth PMOS tube is used as a tail current switching tube of the second-stage dynamic latch to provide current for the second-stage dynamic latch.
Compared with the prior art, the invention has the advantages that:
compared with the traditional Strong-Arm comparator, the first-stage tailless current switching tube double-latch pre-amplifying circuit eliminates a tail current switching tube, eliminates dynamic misadjustment coupled to the input of the comparator caused by source discharge of an input tube and kickback noise caused by the current switching tube, and enables the comparator to have lower input reference noise power; furthermore, the actively injected offset voltage can reduce the input offset of the circuit and the sampling noise of the output node of the first-stage pre-amplifying circuit. The low kickback noise dynamic comparator provided by the invention is suitable for a high-precision successive approximation type analog-to-digital converter.
Drawings
FIG. 1 is a schematic diagram of a conventional Strong-Arm comparator in an embodiment of the present invention.
Fig. 2 is a schematic diagram of a dual latch preamplifier circuit of a first stage tailless current switch tube of a low kickback noise dynamic comparator according to an embodiment of the invention.
FIG. 3 is a schematic diagram of a second stage dynamic latch of a low kickback noise dynamic comparator according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a delay flip-flop of a low kickback noise dynamic comparator according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
Example 1:
a low kickback noise dynamic comparator suitable for a high-precision successive approximation type analog-to-digital converter comprises a first-stage tailless current switching tube double-latch pre-amplifying circuit, a second-stage dynamic latch and a time delay trigger;
the first-stage tailless current switching tube double-latch pre-amplifying circuit comprises a first output node, a second output node, a third output node and a fourth output node;
the second-stage dynamic latch comprises a fifth output node, a sixth output node, a first input node, a second input node, a third input node and a fourth input node;
the delay flip-flop comprises an output node;
the first-stage tailless current switching tube double-latch pre-amplifying circuit receives a first input differential signal and a second input differential signal; a first input node, a second input node, a third input node and a fourth input node of the second-stage dynamic latch are respectively connected with a first output node, a second output node, a third output node and a fourth output node; the delay trigger is respectively connected with a first output node, a second output node, a third output node, a fourth output node, a fifth output node and a sixth output node;
before a clock signal does not arrive, the dynamic comparator is in a reset stage, and a first output node, a second output node, a third output node and a fourth output node of the first-stage tailless current switching tube double-latch pre-amplifying circuit are discharged to a ground potential, namely a low level; the output node of the delay flip-flop is charged to a high level; the fifth output node and the sixth output node of the second stage dynamic latch are discharged to ground potential;
the dynamic comparator is in a comparison stage after a clock signal arrives, the first-stage tailless current switch tube double-latch pre-amplification circuit amplifies input first input differential signals and second input differential signals, and the delay trigger triggers the second-stage dynamic latch to compare and latch output voltages of the first-stage tailless current switch tube double-latch pre-amplification circuit and output the comparison results.
As shown in fig. 2, the first-stage tailless current switching tube double-latch pre-amplifying circuit includes a plurality of input tubes, a plurality of clock signal controlled reset discharge tubes, a first latch, a second latch, and a plurality of offset voltage injection transistors;
the first latch and the second latch take a differential input tube as a source negative feedback resistor and are formed by connecting phase inverters end to end;
in the first-stage tailless current switching tube double-latch pre-amplification circuit, in a reset stage, a first output node, a second output node, a third output node and a fourth output node are discharged to the ground potential; in the comparison stage, the reset discharge tubes are turned off, the offset voltage injection transistors are turned on, offset voltages with the same magnitude are injected into the first latch and the second latch, and when the voltages of the first output node, the second output node, the third output node and the fourth output node are increased to the threshold voltage of the NMOS tube, the first latch and the second latch are started and quickly amplify the offset voltages of the first output node, the second output node, the third output node and the fourth output node;
the input tube works in the linear resistance area and is used as source negative feedback resistance of NMOS tubes in the first latch and the second latch to influence the voltage amplification speed of the first latch and the second latch; the higher the gate voltage of the input tube is, the smaller the linear resistance is, and the faster the amplification speed of the first latch and the second latch is.
Further, the first-stage tailless current switch tube double-latch pre-amplifying circuit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube;
the first NMOS tube is a first input tube, the second NMOS tube is a second input tube, the third NMOS tube is a third input tube, and the fourth NMOS tube is a fourth input tube; the ninth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube, the thirteenth NMOS tube and the fourteenth NMOS tube are reset discharge tubes; a fifth NMOS transistor, a sixth NMOS transistor, a third PMOS transistor and a fourth PMOS transistor form a first latch; a seventh NMOS tube, an eighth NMOS tube, a fifth PMOS tube and a sixth PMOS tube form a second latch; the first PMOS tube and the second PMOS tube are both offset voltage injection transistors.
Furthermore, the grids of the first NMOS tube and the second NMOS tube are connected with a first input differential signal, the source electrodes of the first NMOS tube and the second NMOS tube are grounded, the drain electrode of the first NMOS tube is connected with the source electrode of the fifth NMOS tube, and the drain electrode of the second NMOS tube is connected with the source electrode of the sixth NMOS tube; the grid electrodes of the third NMOS tube and the fourth NMOS tube are connected with a second input differential signal, the source electrodes of the third NMOS tube and the fourth NMOS tube are grounded, the drain electrode of the third NMOS tube is connected with the source electrode of the seventh NMOS tube, and the drain electrode of the fourth NMOS tube is connected with the source electrode of the eighth NMOS tube;
the grid electrode of the fifth NMOS tube is used as a second output node, and the drain electrode of the fifth NMOS tube is used as a first output node; the grid electrode of the sixth NMOS tube is connected with the first output node, and the drain electrode of the sixth NMOS tube is connected with the second output node;
the grid electrode of the seventh NMOS tube is used as a fourth output node, and the drain electrode of the seventh NMOS tube is used as a third output node; the grid electrode of the eighth NMOS tube is connected with the third output node, and the drain electrode of the eighth NMOS tube is connected with the fourth output node; the drain electrode of the ninth NMOS tube is connected with the first output node, and the grid electrode of the ninth NMOS tube is connected with the inverted signal of the clock signal; the drain electrode of the tenth NMOS tube is connected with the second output node, and the grid electrode of the tenth NMOS tube is connected with the inverted signal of the clock signal; the drain electrode of the eleventh NMOS tube is connected with the third output node, and the grid electrode of the eleventh NMOS tube is connected with the inverted signal of the clock signal; the drain electrode of the twelfth NMOS tube is connected with the fourth output node, and the grid electrode of the twelfth NMOS tube is connected with the inverted signal of the clock signal; the grid electrode of the thirteenth NMOS tube is connected with the inverted signal of the clock signal, the source electrode of the thirteenth NMOS tube is grounded, and the drain electrode of the thirteenth NMOS tube is connected with the drain electrode of the second PMOS tube; the grid electrode of the fourteenth NMOS tube is connected with the inverted signal of the clock signal, the source electrode of the fourteenth NMOS tube is grounded, and the drain electrode of the fourteenth NMOS tube is connected with the drain electrode of the first PMOS tube; the grid electrode of the first PMOS tube is connected with the inverted signal of the clock signal, the source electrode of the first PMOS tube is externally connected with power supply voltage, and the drain electrode of the first PMOS tube is connected with the source electrodes of the fourth PMOS tube and the sixth PMOS tube; the grid electrode of the second PMOS tube is connected with the inverted signal of the clock signal, the source electrode of the second PMOS tube is externally connected with power supply voltage, and the drain electrode of the second PMOS tube is connected with the source electrodes of the third PMOS tube and the fifth PMOS tube; the grid electrode of the third PMOS tube is connected with the second output node, the source electrode is connected with the drain electrode of the second PMOS tube, and the drain electrode is connected with the first output node; the grid electrode of the fourth PMOS tube is connected with the first output node, the source electrode of the fourth PMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the second output node; the grid electrode of the fifth PMOS tube is connected with the fourth output node, the source electrode of the fifth PMOS tube is connected with the drain electrode of the second PMOS tube, and the drain electrode of the fifth PMOS tube is connected with the third output node; the grid electrode of the sixth PMOS tube is connected with the third output node, the source electrode of the sixth PMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the fourth output node.
As shown in fig. 3, the delay flip-flop includes a charging tube controlled by a clock signal and four discharge tubes controlled by the output node of the first-stage tailless current switching tube double-latch pre-amplifying circuit;
the delay trigger comprises a fifteenth NMOS (N-channel metal oxide semiconductor) tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube and a seventh PMOS (P-channel metal oxide semiconductor) tube;
the fifteenth NMOS tube, the sixteenth NMOS tube, the seventeenth NMOS tube and the eighteenth NMOS tube are discharge tubes, and the seventh PMOS tube is a charging tube;
the grid electrode of the fifteenth NMOS tube is connected with the first output node of the first-stage tailless current switching tube double-latch pre-amplifying circuit, and the source electrode of the fifteenth NMOS tube is grounded; the grid electrode of a sixteenth NMOS tube is connected with a second output node of the double-latch pre-amplifying circuit of the first-stage tailless current switch tube, and the source electrode of the sixteenth NMOS tube is grounded; the grid electrode of a seventeenth NMOS tube is connected with a third output node of the double-latch pre-amplifying circuit of the first-stage tailless current switch tube, and the source electrode of the seventeenth NMOS tube is grounded; the grid electrode of the eighteenth NMOS tube is connected with the fourth output node of the double-latch pre-amplifying circuit of the first-stage tailless current switch tube, and the source electrode of the eighteenth NMOS tube is grounded; the drain electrodes of the fifteenth NMOS tube, the sixteenth NMOS tube, the seventeenth NMOS tube and the eighteenth NMOS tube are all connected with the drain electrode of the seventh PMOS tube and serve as the output node of the delay trigger; the grid electrode of the seventh PMOS tube is connected with a clock signal, and the source electrode of the seventh PMOS tube is externally connected with power supply voltage.
Furthermore, the delay trigger is charged through a seventh PMOS tube in a reset stage, and outputs a high level; in the comparison stage, when any output node of the first-stage tailless current switch tube double-latch pre-amplification circuit is charged to the threshold voltage of the NMOS tube, the NMOS tube connected with the output node in the delay trigger is conducted, the output node of the delay trigger is discharged, the ground potential is output after a period of time, the second-stage dynamic latch is triggered to compare the output voltage of the first-stage tailless current switch tube double-latch pre-amplification circuit, and the final comparison result is obtained.
As shown in fig. 4, the second-stage dynamic latch includes a nineteenth NMOS transistor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, a twenty-fourth NMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, and a fourteenth PMOS transistor;
the grid electrode of the eighth PMOS tube is a first input node of the second-stage dynamic latch and is connected with a first output node of the first-stage tailless current switching tube double-latch pre-amplifying circuit; the source electrode of the eighth PMOS tube is connected with the drain electrode of the fourteenth PMOS tube, and the drain electrode of the eighth PMOS tube is connected with the source electrode of the twelfth PMOS tube; the grid electrode of the ninth PMOS tube is a second input node of the second-stage dynamic latch and is connected with a fourth output node of the first-stage tailless current switching tube double-latch pre-amplifying circuit; the source electrode of the ninth PMOS tube is connected with the drain electrode of the fourteenth PMOS tube, and the drain electrode of the ninth PMOS tube is connected with the source electrode of the twelfth PMOS tube; the grid electrode of the tenth PMOS tube is a third input node of the second-stage dynamic latch and is connected with a second output node of the double-latch pre-amplifying circuit of the first-stage tailless current switching tube; the source electrode of the tenth PMOS tube is connected with the drain electrode of the fourteenth PMOS tube, and the drain electrode of the tenth PMOS tube is connected with the source electrode of the thirteenth PMOS tube; the grid electrode of the eleventh PMOS tube is a fourth input node of the second-stage dynamic latch and is connected with a third output node of the first-stage tailless current switching tube double-latch pre-amplifying circuit; the source electrode of the eleventh PMOS tube is connected with the drain electrode of the fourteenth PMOS tube, and the drain electrode of the eleventh PMOS tube is connected with the source electrode of the thirteenth PMOS tube; the grid electrode of the twelfth PMOS tube is connected with the fifth output node of the second-stage dynamic latch, and the drain electrode of the twelfth PMOS tube is connected with the sixth output node of the second-stage dynamic latch; the grid electrode of the thirteenth PMOS tube is connected with the sixth output node of the second-stage dynamic latch, and the drain electrode of the thirteenth PMOS tube is connected with the fifth output node of the second-stage dynamic latch; the grid electrode of the fourteenth PMOS tube is connected with the output node of the time delay trigger, the source electrode of the fourteenth PMOS tube is grounded, and the drain electrode of the fourteenth PMOS tube is connected with the source electrodes of the eighth PMOS tube, the ninth PMOS tube, the tenth PMOS tube and the eleventh PMOS tube; the grid electrode of the nineteenth NMOS tube is connected with the output node of the delay trigger, the source electrode of the nineteenth NMOS tube is grounded, and the drain electrode of the nineteenth NMOS tube is connected with the negative output node; the grid electrode of the twentieth NMOS tube is connected with the fifth output node of the second-stage dynamic latch, the source electrode of the twentieth NMOS tube is grounded, and the drain electrode of the twentieth NMOS tube is connected with the sixth output node of the second-stage dynamic latch; the grid electrode of the twenty-first NMOS tube is connected with the sixth output node of the second-stage dynamic latch, the source electrode of the twenty-first NMOS tube is grounded, and the drain electrode of the twenty-first NMOS tube is connected with the fifth output node of the second-stage dynamic latch; the grid electrode of the twenty-second NMOS tube is connected with the output node of the delay trigger, the source electrode of the delay trigger is grounded, and the drain electrode of the delay trigger is connected with the fifth output node of the second-stage dynamic latch; the grid electrode of the twenty-third NMOS transistor is connected with the output node of the delay trigger, the source electrode of the twenty-third NMOS transistor is grounded, and the drain electrode of the twenty-third NMOS transistor is connected with the source electrode of the twelfth PMOS transistor; the grid electrode of the twenty-fourth NMOS tube is connected with the output node of the delay trigger, the source electrode of the delay trigger is grounded, and the drain electrode of the delay trigger is connected with the source electrode of the thirteenth PMOS tube.
Furthermore, the fourteenth PMOS tube is used as a tail current switching tube of the second-stage dynamic latch to provide current for the second-stage dynamic latch.
In this embodiment, the first input differential signal and the second input differential signal are compared, and the comparison result shows that the dynamic offset error caused by the source discharge of the input tube is eliminated.
Example 2:
in this embodiment, the comparison result shows that the source potential and the drain potential of the input tube are the ground potential, the input tube operates in the linear resistance region, and the gain is small, so that the gain for amplifying the input voltage by using the input tube is small, which results in a large input reference noise ratio.
Example 3:
in this embodiment, the first input differential signal and the second input differential signal of the present invention are compared, and the comparison result shows that the delay flip-flop provided by the present invention can make the second stage dynamic latch compare at the maximum value of the output voltage of the first stage pre-amplifying circuit, further increase the gain of the first stage pre-amplifying circuit, and reduce the input reference noise.
Compared with the traditional Strong-Arm dynamic comparator shown in fig. 1, the low kickback noise dynamic comparator applicable to the high-precision successive approximation type analog-to-digital converter provided by the invention has the following advantages:
firstly, the first-stage tailless current switch tube double-latch pre-amplifying circuit removes a tail current switch tube, and eliminates dynamic maladjustment errors caused by source discharge of an input tube; secondly, the source electrode potential and the drain electrode potential of the input tube are ground potentials, the input tube works in a linear resistance area, the gain is small, so that the gain for amplifying the input voltage by using the input tube is small, and the input reference noise ratio is larger. Thirdly, the delay trigger provided by the invention can enable the second-stage dynamic latch to be compared at the maximum value of the output voltage of the first-stage pre-amplifying circuit, further increase the gain of the first-stage pre-amplifying circuit and reduce the input reference noise. Therefore, the dynamic comparator provided by the invention is suitable for a high-precision successive approximation type analog-to-digital converter.
It will be apparent to those skilled in the art that various other changes and modifications may be made in the above-described embodiments and concepts and all such changes and modifications are intended to be within the scope of the appended claims.
Claims (10)
1. A dynamic comparator with low kickback noise is characterized in that: the circuit comprises a first-stage tailless current switching tube double-latch pre-amplifying circuit, a second-stage dynamic latch and a time delay trigger;
the first-stage tailless current switching tube double-latch pre-amplifying circuit comprises a first output node, a second output node, a third output node and a fourth output node;
the second-stage dynamic latch comprises a fifth output node, a sixth output node, a first input node, a second input node, a third input node and a fourth input node;
the delay flip-flop comprises an output node;
the first-stage tailless current switch tube double-latch pre-amplification circuit receives a first input differential signal and a second input differential signal; a first input node, a second input node, a third input node and a fourth input node of the second-stage dynamic latch are respectively connected with a first output node, a second output node, a third output node and a fourth output node; the delay flip-flop is respectively connected with the first output node, the second output node, the third output node, the fourth output node, the fifth output node and the sixth output node.
2. A low kickback noise dynamic comparator as claimed in claim 1, wherein: before a clock signal does not arrive, the dynamic comparator is in a reset stage, and a first output node, a second output node, a third output node and a fourth output node of the first-stage tailless current switching tube double-latch pre-amplification circuit are discharged to the ground potential, namely low level; the output node of the delay trigger is charged to a high level; the fifth output node and the sixth output node of the second stage dynamic latch are discharged to ground potential;
the dynamic comparator is in a comparison stage after a clock signal arrives, the first-stage tailless current switch tube double-latch pre-amplification circuit amplifies input first input differential signals and second input differential signals, and the delay trigger triggers the second-stage dynamic latch to compare and latch output voltages of the first-stage tailless current switch tube double-latch pre-amplification circuit and output the comparison results.
3. A low kickback noise dynamic comparator as claimed in claim 1, wherein: the first-stage tailless current switching tube double-latch pre-amplifying circuit comprises a plurality of input tubes, a plurality of reset discharge tubes controlled by clock signals, a first latch, a second latch and a plurality of offset voltage injection transistors;
the first latch and the second latch take a differential input tube as a source negative feedback resistor and are formed by connecting phase inverters end to end;
in the first-stage tailless current switching tube double-latch pre-amplification circuit, in a reset stage, a first output node, a second output node, a third output node and a fourth output node are discharged to the ground potential; in the comparison stage, the reset discharge tubes are turned off, the offset voltage injection transistors are turned on, offset voltages with the same magnitude are injected into the first latch and the second latch, and when the voltages of the first output node, the second output node, the third output node and the fourth output node rise to the threshold voltage of the NMOS tube, the first latch and the second latch are turned on and quickly amplify the offset voltages of the first output node, the second output node, the third output node and the fourth output node.
4. A low kickback noise dynamic comparator as claimed in claim 1, wherein: an input tube in the first-stage tailless current switching tube double-latch pre-amplifying circuit works in a linear resistance area and is used as a source negative feedback resistance of NMOS tubes in the first latch and the second latch to influence the voltage amplifying speed of the first latch and the second latch; the higher the gate voltage of the input tube is, the smaller the linear resistance is, and the faster the first latch and the second latch amplify.
5. A low kickback noise dynamic comparator as claimed in claim 3, wherein: the first-stage tailless current switch tube double-latch pre-amplifying circuit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube;
the first NMOS tube is a first input tube, the second NMOS tube is a second input tube, the third NMOS tube is a third input tube, and the fourth NMOS tube is a fourth input tube; the ninth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube, the thirteenth NMOS tube and the fourteenth NMOS tube are reset discharge tubes; a fifth NMOS tube, a sixth NMOS tube, a third PMOS tube and a fourth PMOS tube form a first latch; a seventh NMOS tube, an eighth NMOS tube, a fifth PMOS tube and a sixth PMOS tube form a second latch; the first PMOS tube and the second PMOS tube are both offset voltage injection transistors.
6. A low kickback noise dynamic comparator as claimed in claim 5, wherein: the grid electrodes of the first NMOS tube and the second NMOS tube are connected with a first input differential signal, the source electrodes of the first NMOS tube and the second NMOS tube are grounded, the drain electrode of the first NMOS tube is connected with the source electrode of the fifth NMOS tube, and the drain electrode of the second NMOS tube is connected with the source electrode of the sixth NMOS tube; the grid electrodes of the third NMOS tube and the fourth NMOS tube are connected with a second input differential signal, the source electrodes of the third NMOS tube and the fourth NMOS tube are grounded, the drain electrode of the third NMOS tube is connected with the source electrode of the seventh NMOS tube, and the drain electrode of the fourth NMOS tube is connected with the source electrode of the eighth NMOS tube;
the grid electrode of the fifth NMOS tube is used as a second output node, and the drain electrode of the fifth NMOS tube is used as a first output node; the grid electrode of the sixth NMOS tube is connected with the first output node, and the drain electrode of the sixth NMOS tube is connected with the second output node;
the grid electrode of the seventh NMOS tube is used as a fourth output node, and the drain electrode of the seventh NMOS tube is used as a third output node; the grid electrode of the eighth NMOS tube is connected with the third output node, and the drain electrode of the eighth NMOS tube is connected with the fourth output node; the drain electrode of the ninth NMOS tube is connected with the first output node, and the grid electrode of the ninth NMOS tube is connected with the inverted signal of the clock signal; the drain electrode of the tenth NMOS tube is connected with the second output node, and the grid electrode of the tenth NMOS tube is connected with the inverted signal of the clock signal; the drain electrode of the eleventh NMOS tube is connected with the third output node, and the grid electrode of the eleventh NMOS tube is connected with the inverted signal of the clock signal; the drain electrode of the twelfth NMOS tube is connected with the fourth output node, and the grid electrode of the twelfth NMOS tube is connected with the inverted signal of the clock signal; the grid electrode of the thirteenth NMOS tube is connected with the inverted signal of the clock signal, the source electrode of the thirteenth NMOS tube is grounded, and the drain electrode of the thirteenth NMOS tube is connected with the drain electrode of the second PMOS tube; the grid electrode of the fourteenth NMOS tube is connected with the inverted signal of the clock signal, the source electrode of the fourteenth NMOS tube is grounded, and the drain electrode of the fourteenth NMOS tube is connected with the drain electrode of the first PMOS tube; the grid electrode of the first PMOS tube is connected with the inverted signal of the clock signal, the source electrode of the first PMOS tube is externally connected with power supply voltage, and the drain electrode of the first PMOS tube is connected with the source electrodes of the fourth PMOS tube and the sixth PMOS tube; the grid electrode of the second PMOS tube is connected with the inverted signal of the clock signal, the source electrode is externally connected with power supply voltage, and the drain electrode is connected with the source electrodes of the third PMOS tube and the fifth PMOS tube; the grid electrode of the third PMOS tube is connected with the second output node, the source electrode is connected with the drain electrode of the second PMOS tube, and the drain electrode is connected with the first output node; the grid electrode of the fourth PMOS tube is connected with the first output node, the source electrode of the fourth PMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the second output node; the grid electrode of the fifth PMOS tube is connected with the fourth output node, the source electrode of the fifth PMOS tube is connected with the drain electrode of the second PMOS tube, and the drain electrode of the fifth PMOS tube is connected with the third output node; the grid electrode of the sixth PMOS tube is connected with the third output node, the source electrode of the sixth PMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the fourth output node.
7. A low kickback noise dynamic comparator as claimed in claim 1, wherein: the delay trigger comprises a charging tube controlled by a clock signal and four discharge tubes controlled by the output nodes of the first-stage tailless current switching tube double-latch pre-amplifying circuit;
the delay trigger comprises a fifteenth NMOS (N-channel metal oxide semiconductor) tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube and a seventh PMOS tube;
the fifteenth NMOS tube, the sixteenth NMOS tube, the seventeenth NMOS tube and the eighteenth NMOS tube are discharge tubes, and the seventh PMOS tube is a charging tube;
the grid electrode of the fifteenth NMOS tube is connected with the first output node of the first-stage tailless current switching tube double-latch pre-amplifying circuit, and the source electrode of the fifteenth NMOS tube is grounded; the grid electrode of the sixteenth NMOS tube is connected with the second output node of the first-stage tailless current switching tube double-latch pre-amplifying circuit, and the source electrode of the sixteenth NMOS tube is grounded; the grid electrode of the seventeenth NMOS tube is connected with the third output node of the first-stage tailless current switching tube double-latch pre-amplifying circuit, and the source electrode is grounded; the grid electrode of the eighteenth NMOS tube is connected with the fourth output node of the double-latch pre-amplifying circuit of the first-stage tailless current switch tube, and the source electrode of the eighteenth NMOS tube is grounded; the drain electrodes of the fifteenth NMOS tube, the sixteenth NMOS tube, the seventeenth NMOS tube and the eighteenth NMOS tube are all connected with the drain electrode of the seventh PMOS tube and serve as the output node of the delay trigger; the grid electrode of the seventh PMOS tube is connected with a clock signal, and the source electrode of the seventh PMOS tube is externally connected with power supply voltage.
8. A low kickback noise dynamic comparator as claimed in claim 7, wherein: the delay trigger is charged through a seventh PMOS tube in the reset stage, and outputs a high level; in the comparison stage, when any output node of the first stage tailless current switch tube double-latch pre-amplifying circuit is charged to the threshold voltage of the NMOS tube, the NMOS tube connected with the output node in the delay trigger is conducted, the output node of the delay trigger is discharged, the ground potential is output after a period of time, and the second stage dynamic latch is triggered to compare the output voltage of the first stage tailless current switch tube double-latch pre-amplifying circuit to obtain a final comparison result.
9. A low kickback noise dynamic comparator as claimed in any one of claims 1 to 8, wherein: the second-stage dynamic latch comprises a nineteenth NMOS transistor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, a twenty-fourth NMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor and a fourteenth PMOS transistor;
the grid electrode of the eighth PMOS tube is a first input node of the second-stage dynamic latch and is connected with a first output node of the first-stage tailless current switching tube double-latch pre-amplifying circuit; the source electrode of the eighth PMOS tube is connected with the drain electrode of the fourteenth PMOS tube, and the drain electrode of the eighth PMOS tube is connected with the source electrode of the twelfth PMOS tube; the grid electrode of the ninth PMOS tube is a second input node of the second-stage dynamic latch and is connected with a fourth output node of the first-stage tailless current switching tube double-latch pre-amplifying circuit; the source electrode of the ninth PMOS tube is connected with the drain electrode of the fourteenth PMOS tube, and the drain electrode of the ninth PMOS tube is connected with the source electrode of the twelfth PMOS tube; the grid electrode of the tenth PMOS tube is a third input node of the second-stage dynamic latch and is connected with a second output node of the first-stage tailless current switching tube double-latch pre-amplifying circuit; the source electrode of the tenth PMOS tube is connected with the drain electrode of the fourteenth PMOS tube, and the drain electrode of the tenth PMOS tube is connected with the source electrode of the thirteenth PMOS tube; the grid electrode of the eleventh PMOS tube is a fourth input node of the second-stage dynamic latch and is connected with a third output node of the double-latch pre-amplifying circuit of the first-stage tailless current switching tube; the source electrode of the eleventh PMOS tube is connected with the drain electrode of the fourteenth PMOS tube, and the drain electrode of the eleventh PMOS tube is connected with the source electrode of the thirteenth PMOS tube; the grid electrode of the twelfth PMOS tube is connected with the fifth output node of the second-stage dynamic latch, and the drain electrode of the twelfth PMOS tube is connected with the sixth output node of the second-stage dynamic latch; the grid electrode of the thirteenth PMOS tube is connected with the sixth output node of the second-stage dynamic latch, and the drain electrode of the thirteenth PMOS tube is connected with the fifth output node of the second-stage dynamic latch; the grid electrode of the fourteenth PMOS tube is connected with the output node of the delay trigger, the source electrode of the fourteenth PMOS tube is grounded, and the drain electrode of the fourteenth PMOS tube is connected with the source electrodes of the eighth PMOS tube, the ninth PMOS tube, the tenth PMOS tube and the eleventh PMOS tube; the grid electrode of the nineteenth NMOS tube is connected with the output node of the delay trigger, the source electrode of the nineteenth NMOS tube is grounded, and the drain electrode of the nineteenth NMOS tube is connected with the negative output node; the grid electrode of the twentieth NMOS tube is connected with the fifth output node of the second-stage dynamic latch, the source electrode of the twentieth NMOS tube is grounded, and the drain electrode of the twentieth NMOS tube is connected with the sixth output node of the second-stage dynamic latch; the grid electrode of the twenty-first NMOS tube is connected with the sixth output node of the second-stage dynamic latch, the source electrode of the twenty-first NMOS tube is grounded, and the drain electrode of the twenty-first NMOS tube is connected with the fifth output node of the second-stage dynamic latch; the grid electrode of the twenty-second NMOS tube is connected with the output node of the delay trigger, the source electrode of the twenty-second NMOS tube is grounded, and the drain electrode of the twenty-second NMOS tube is connected with the fifth output node of the second-stage dynamic latch; the grid electrode of the twenty-third NMOS tube is connected with the output node of the delay trigger, the source electrode of the delay trigger is grounded, and the drain electrode of the delay trigger is connected with the source electrode of the twelfth PMOS tube; the grid electrode of the twenty-fourth NMOS tube is connected with the output node of the delay trigger, the source electrode of the delay trigger is grounded, and the drain electrode of the delay trigger is connected with the source electrode of the thirteenth PMOS tube.
10. A low kickback noise dynamic comparator as claimed in claim 9, wherein: and the fourteenth PMOS tube is used as a tail current switching tube of the second-stage dynamic latch and provides current for the second-stage dynamic latch.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116192144A (en) * | 2023-02-13 | 2023-05-30 | 集益威半导体(上海)有限公司 | Asynchronous successive approximation analog-to-digital converter |
| CN117060899A (en) * | 2023-10-10 | 2023-11-14 | 江苏润石科技有限公司 | Dynamic comparator circuit and successive approximation analog-to-digital converter |
| CN117394858A (en) * | 2023-12-08 | 2024-01-12 | 成都通量科技有限公司 | Comparator, analog-to-digital converter and device for reducing kickback noise |
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2022
- 2022-07-01 CN CN202210769743.XA patent/CN115333515A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116192144A (en) * | 2023-02-13 | 2023-05-30 | 集益威半导体(上海)有限公司 | Asynchronous successive approximation analog-to-digital converter |
| CN116192144B (en) * | 2023-02-13 | 2024-04-02 | 集益威半导体(上海)有限公司 | Asynchronous successive approximation analog-to-digital converter |
| CN117060899A (en) * | 2023-10-10 | 2023-11-14 | 江苏润石科技有限公司 | Dynamic comparator circuit and successive approximation analog-to-digital converter |
| CN117060899B (en) * | 2023-10-10 | 2024-01-30 | 江苏润石科技有限公司 | Dynamic comparator circuit and successive approximation analog-to-digital converter |
| CN117394858A (en) * | 2023-12-08 | 2024-01-12 | 成都通量科技有限公司 | Comparator, analog-to-digital converter and device for reducing kickback noise |
| CN117394858B (en) * | 2023-12-08 | 2024-03-19 | 成都通量科技有限公司 | Comparator, analog-to-digital converter and device for reducing kickback noise |
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