CN111600607B

CN111600607B - Broadband low-power consumption comparator circuit

Info

Publication number: CN111600607B
Application number: CN202010403259.6A
Authority: CN
Inventors: 李福乐; 丁洋; 王晓
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2020-05-13
Filing date: 2020-05-13
Publication date: 2022-04-15
Anticipated expiration: 2040-05-13
Also published as: CN111600607A

Abstract

The invention provides a broadband low-power-consumption comparator circuit, and belongs to the field of integrated circuit design. The circuit includes an input transconductance circuit, two intermediate isolation switches, and an output latch circuit with a reset switch. The output latch comprises two cross-coupled inverters, a reset switch connected with output ends of the two inverters, a current-limiting resistor connected with negative power supply ends of the two inverters to the ground, and a triggering acceleration branch circuit connected with the negative power supply ends of the two inverters to the control clock LAT, wherein the branch circuit is formed by connecting a resistor and a capacitor in series. The comparator circuit provided by the invention is suitable for directly comparing broadband input signals, and comprises a current-limiting resistor which is introduced into an output latch and is used for connecting a power supply to a ground path, and a trigger accelerating branch circuit which is connected from a trigger clock to a negative power supply end of a bistable circuit; the comparator circuit has the characteristics of broadband, low power consumption and high speed under the characteristic of keeping single clock trigger.

Description

Broadband low-power consumption comparator circuit

Technical Field

The invention belongs to the field of integrated circuit design, and particularly relates to a broadband low-power-consumption comparator circuit suitable for directly comparing broadband input signals.

Background

The Pipeline analog-to-digital converter (Pipeline ADC) has high speed and high precision, and is widely used in the fields of communication, radar, medical treatment, instruments and meters, automotive electronics, and the like. With the continuous development of electronic systems, the system puts higher requirements on input bandwidth, speed and power consumption of the ADC. For Pipeline ADCs, the input Sample and Hold Amplifier (SHA) is removed, and the input signal is directly sampled and converted by the first stage circuit, i.e., so-called SHA-Less design is implemented, which can reduce power consumption, optimize noise and improve linearity, and thus SHA-Less design is being increasingly applied. However, the SHA-Less design has an aperture error problem, which is not favorable for the broadband input design.

To address this problem, one possible solution is to use a wide tracking bandwidth, comparator that determines the trigger time. One conventional comparator design is shown in fig. 1, in which fig. 1 (a) is a circuit 100, and fig. 1 (b) is an operation timing under clock control. The circuit 100 shown in fig. 1 (a) includes an input transconductance circuit 110, two

intermediate isolation switches

101 and 102, and an output latch circuit 120. The input transconductance circuit 110 includes two NMOS differential pair transistors 111 and 112 and an NMOS bias transistor 113, under the control of a bias voltage Vb, the NMOS bias transistor 113 provides a bias current for the NMOS differential pair transistors 111 and 112, and the NMOS differential pair transistors 111 and 112 respectively convert a difference between input voltages Vip and Vin into an output current difference. The output latch circuit 120 includes a first inverter formed by a PMOS transistor 121 and an NMOS transistor 123, and a second inverter formed by a PMOS transistor 122 and an NMOS transistor 124, which are cross-coupled and form a bistable circuit with reset together with an NMOS transistor 125 (as a reset switch). The comparator circuit has only one control clock LAT, the timing of which is shown in fig. 1 (b), when the control clock LAT is high, the

intermediate isolation switches

101 and 102 and the NMOS transistor 125 as the reset switch are both turned on, the comparator is in the tracking state, at this time, the input transconductance circuit 110 converts the differential input voltage into a differential output current, which is sent to the output latch circuit 120 through the

intermediate isolation switches

101 and 102, the output latch circuit 120 is in the reset state, the differential current forms an output differential voltage on the latch reset impedance and quickly tracks the change of the differential input voltage, and at the same time, since the NMOS transistor 125 as the reset switch is turned on, a conduction path is formed in the output latch circuit 120 from the power supply VDD to ground, increasing the current from the power supply VDD to ground; at the falling edge of the control clock LAT, the

intermediate isolation switches

101 and 102 are turned off to lock the signal value at that time, and at the same time, the NMOS transistor 125 as a reset switch is also turned off, and the output latch circuit 120 ends the reset and starts regenerative amplification of the voltage difference between the output terminals Vop and Von to a logic level. As described above, this comparator design has the following problems: in the tracking phase (when the control clock LAT is high), the sum of the gate-source voltage VGSp of the PMOS transistor 121/122 and the gate-source voltage VGSn of the NMOS transistor 123/124 is the power supply VDD, and thus, a variation in the power supply VDD is directly applied to the overdrive voltage of the MOS transistor, which causes a large power consumption of the output latch circuit portion, a poor power supply rejection ratio, and is too sensitive to variables such as a process, a supply voltage, and a temperature (PVT).

To solve this problem, the output latch circuit portion may be modified, as shown in fig. 2, which shows a second conventional design, where fig. 2 (a) is a circuit 200 and fig. 2 (b) is an operation timing under clock control. The circuit 200 shown in fig. 2 (a) includes an input transconductance circuit 210, two

intermediate isolation switches

201 and 202, and an output latch circuit 220. The input transconductance circuit 210 includes two NMOS differential pair transistors 211 and 212, and an NMOS bias transistor 213, under the control of a bias voltage Vb, the NMOS bias transistor 213 provides a bias current for the NMOS differential pair transistors 211 and 212, and the NMOS differential pair transistors 211 and 212 convert the difference between the input voltages Vip and Vin into an output current difference. The output latch circuit 220 includes a first inverter formed by a PMOS transistor 221 and an NMOS transistor 223, a second inverter formed by a PMOS transistor 222 and an NMOS transistor 224, which are cross-coupled and form a bistable circuit with reset together with an NMOS transistor 225. The output latch circuit 220 further includes an NMOS switch 226 from the aforementioned bi-stable negative supply ns to ground. The comparator circuit has two control clocks, namely, control clocks LAT and CK2, the timing of which is shown in fig. 2 (b), when the control clock LAT is high, the

intermediate isolation switches

201 and 202 and the NMOS transistor 225 as the reset switch are both turned on, the comparator is in the tracking state, at this time, the input transconductance circuit 210 converts the differential input voltage into a differential output current, which is sent to the output latch circuit 220 through the

intermediate isolation switches

201 and 202, the output latch circuit 220 is in the reset state, the differential current forms an output differential voltage on the latch reset impedance, and quickly tracks the change of the differential input voltage, at this time, although the NMOS transistor 225 as the reset switch is turned on, the NMOS transistor 226 controlled by the control clock CK2 is in the off state, and no current path from the power supply VDD to the ground is formed inside the output latch circuit 220; at the falling edge of the control clock LAT, the

intermediate isolation switches

201 and 202 are turned off to lock the signal value at that time, the NMOS transistor 225 as a reset switch is also turned off, the output latch circuit 220 ends the reset, and the control clock CK2 turns on the path from the power supply VDD to the ground from low to high to start regenerative amplification of the voltage difference between the output terminals Vop and Von to a logic level. As described above, compared to the first conventional design, the second conventional design adds an NMOS transistor 226 between the negative supply terminal of the output latch and ground, and adds the control clock CK2 to implement the function of a switch to turn off the current of the output latch part in the tracking phase, so as to solve the problems of the first conventional design, such as large power consumption of the output latch part, poor power supply rejection ratio, and excessive sensitivity to temperature (PVT) and other variables. However, this comparator design also has the following problems: the timing control is not single-clock control, so that the timing control is more complicated, the control clock LAT is usually a voltage-bootstrapped clock, the control clock CK2 is a non-voltage-bootstrapped clock, the timing between the two clocks is difficult to accurately control, the trigger time is difficult to accurately determine if the rising edge of the control clock CK2 leads the control clock LAT, and the comparison speed is slower if the rising edge of the control clock CK2 lags the control clock LAT.

Disclosure of Invention

The invention aims to overcome the defects of the prior art, provides a broadband low-power-consumption comparator circuit, and is a broadband low-power-consumption comparator circuit suitable for an SHA-Less Pipeline ADC.

In order to achieve the purpose, the invention adopts the following technical scheme:

the invention provides a broadband low-power-consumption comparator circuit, which comprises an input transconductance circuit, two intermediate isolating switches and an output latch circuit, wherein the input transconductance circuit is connected with the output latch circuit;

the input transconductance circuit comprises two NMOS differential pair transistors and an NMOS bias transistor, the source electrodes of the two NMOS differential pair transistors are connected to the drain electrode of the NMOS bias transistor together, the grid electrodes of the two NMOS differential pair transistors are respectively connected to input voltages Vip and Vin, the drain electrodes of the two NMOS differential pair transistors are respectively connected to the output latch circuit through the corresponding intermediate isolating switches, and the source electrode and the grid electrode of the NMOS bias transistor are respectively grounded and biased by a bias voltage Vb;

the output latch circuit comprises a first inverter formed by a first PMOS transistor and a first NMOS transistor, and a second inverter formed by a second PMOS transistor and a second NMOS transistor, wherein the first inverter and the second inverter are cross-coupled and form a bistable circuit with reset together with a third NMOS transistor; the drain electrode and the source electrode of the third NMOS transistor are respectively connected with the output ends Vop and Von of the bistable circuit; output ends Vop and Von of the bistable circuit are respectively connected to drains of two NMOS differential pair transistors in the input transconductance circuit through corresponding intermediate isolating switches; the gates of the two intermediate isolating switches and the gate of the third NMOS transistor are both connected to a control clock LAT;

the output latch circuit is characterized by further comprising a current-limiting resistor from the negative power supply end ns of the bistable circuit to the ground, and a triggering acceleration branch formed by serially connecting a capacitor and a resistor and used for connecting the control clock LAT and the negative power supply end ns of the bistable circuit, wherein the triggering acceleration branch provides a pull-down current for the negative power supply end ns of the bistable circuit at the falling edge moment of the control clock LAT, the resistance value of the resistor controls the maximum pull-down current value, the capacitance value of the capacitor controls the total discharge amount of the pull-down current, and the product of the resistance value of the resistor and the capacitance value of the capacitor determines the decay time of the pull-down current.

The invention has the following characteristics and beneficial effects:

the comparator circuit provided by the invention is suitable for directly comparing broadband input signals, and comprises a current-limiting resistor which is introduced into an output latch and is used for connecting a power supply to a ground path, and a trigger accelerating branch circuit which is connected from a trigger clock to a negative power supply end of a bistable circuit. The whole comparator is only provided with one control clock LAT, when the LAT is high, the middle isolating switch and the latch reset switch are both conducted, the comparator is in a tracking state, at the moment, the input transconductance circuit converts differential input voltage into differential output current, the differential output current is sent to the output latch through the middle isolating switch, the output latch is in a reset state, the differential current forms output differential voltage on the latch reset impedance, and the change of the differential input voltage is quickly tracked; at the falling edge of the control clock LAT, the isolating switch is closed, the signal value at the moment is locked, meanwhile, the latch finishes resetting, and the voltage difference of the differential end starts to be regenerated and amplified until the logic level; when the control clock LAT is low, the latch latches the comparison result and outputs it. Compared with the existing design, the method has the characteristics of broadband, low power consumption, high speed and low PVT sensitivity under the characteristic of keeping single clock trigger.

Drawings

Fig. 1 (a) and (b) show a circuit diagram of a conventional comparator and an operation timing chart under clock control, respectively.

Fig. 2 (a) and (b) are a circuit diagram of another conventional comparator and an operation timing chart under clock control, respectively.

Fig. 3 is a schematic diagram of a wideband low power consumption comparator circuit according to the present invention.

Fig. 4 is a timing diagram of the operation of the comparator circuit shown in fig. 3 under clock control.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the detailed description and specific examples, while indicating the scope of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.

For better understanding of the present invention, an application example of a wideband low power consumption comparator circuit proposed by the present invention is described in detail below.

The main design idea of the broadband low-power-consumption comparator circuit provided by the embodiment of the invention is to keep single clock triggering, reduce the power consumption of an input tracking phase, reduce the PVT sensitivity of the input tracking phase and keep higher comparison speed. Corresponding circuit design as shown in fig. 3, the comparator circuit 300 of the present embodiment includes an input transconductance circuit 310, two

intermediate isolation switches

301 and 302, and an output latch circuit 320. The input transconductance circuit 310 comprises two NMOS

differential pair transistors

311 and 312 and an NMOS bias transistor 313, the sources of the NMOS

differential pair transistors

311 and 312 are connected to the drain of the NMOS bias transistor 313 together, the gates of the NMOS

differential pair transistors

311 and 312 are connected to the input voltages Vip and Vin, the drains of the NMOS

differential pair transistors

311 and 312 are connected to the output latch circuit 320 through the

intermediate isolation switches

301 and 302, and the source of the NMOS bias transistor 313 is grounded; under the control of the bias voltage Vb, the NMOS bias tube 313 provides bias currents for the NMOS

differential pair tubes

311 and 312, and the NMOS

differential pair tubes

311 and 312 convert the difference between the input voltages Vip and Vin into an output current difference. The output latch circuit 320 includes a first inverter formed by a PMOS transistor 321 and an NMOS transistor 323, and a second inverter formed by a PMOS transistor 322 and an NMOS transistor 324, which are cross-coupled to form a bistable circuit with reset together with an NMOS transistor 325. The drain and source of the NMOS transistor 325 are connected to the output terminals Vop and Von of the bistable circuit, respectively, and function as a reset switch; in addition, the output terminals Vop and Von of the bistable circuit are connected to the drains of the NMOS

differential pair transistors

312 and 311 in the input transconductance circuit 310 through the

intermediate isolation switches

302 and 301, respectively. The gates of the

intermediate isolation switches

301 and 302 and the NMOS transistor 325 are both connected to the control clock LAT. The output latch circuit 320 further includes a current limiting resistor 326 (which may be an active resistor 326a or a passive resistor 326b) from the negative power supply terminal ns of the bistable circuit to ground, and a trigger acceleration branch formed by a capacitor 327 and a resistor 328 connected in series and used for connecting the control clock LAT and the negative power supply terminal ns of the bistable circuit. The triggering acceleration branch provides a pull-down current for the negative power supply end ns of the bistable circuit at the beginning of the falling edge moment of the control clock LAT, so that the judgment speed of the output latch circuit 320 is accelerated; the resistance value of the resistor 328 controls the maximum pull-down current value, the capacitance value of the capacitor 327 controls the total discharge amount of the pull-down current, the product of the resistance value of the resistor 328 and the capacitance value of the capacitor 327 determines the decay time of the pull-down current, and the specific design values of the capacitor 327 and the resistor 328 need to be adjusted according to the parameters of each transistor in the bistable circuit and the loads of the output terminals Vop and Von of the bistable circuit, so that a better trigger acceleration effect is realized by using a smaller control clock LAT additional load (namely the capacitance value of the capacitor 327).

The comparator circuit proposed by the present invention has only one control clock LAT, the timing of which is shown in fig. 4, when the control clock LAT is high, the

intermediate isolation switches

301 and 302 and the NMOS transistor 325 as the reset switch are both turned on, the comparator is in the tracking state, at this time, the input transconductance circuit 310 converts the differential input voltage into a differential output current, which is sent to the output latch circuit 320 through the

intermediate isolation switches

301 and 302, the output latch circuit 320 is in the reset state, the differential current forms an output differential voltage on the latch reset impedance and quickly tracks the change of the differential input voltage, at the same time, since the NMOS transistor 325 as the reset switch is turned on, a conduction path is formed in the output latch circuit 320 from the power supply VDD to ground, increasing the current from the power supply VDD to ground, but at this time, the resistance 326 from the negative power supply terminal ns of the bistable circuit to ground can reduce the current value, the power supply rejection ratio is improved, and the sensitivity of the power supply rejection ratio to variables such as process, power supply voltage and temperature (PVT) is reduced; on the falling edge of the control clock LAT, the

intermediate isolator switches

301 and 302 are closed, locking the signal value at that moment, at the same time, the NMOS transistor 325, which is used as a reset switch, is also turned off, the output latch circuit 320 is reset, and the voltage difference between the output terminals Vop and Von of the output latch circuit 320 is regenerated and amplified to a logic level, which is worth pointing out, at the falling edge of the control clock LAT, due to the action of the resistor 326, the voltage of the negative supply terminal ns of the bistable circuit is higher than ground, that is, the bistable circuit composed of MOS transistors 321-324 is low in power supply, resulting in slow output regeneration and amplification, a trigger acceleration branch consisting of a capacitor 327 and a resistor 328 which are connected in series is added from the control clock LAT to the negative power supply end ns of the bistable circuit, so that the negative power supply end ns of the bistable circuit is pulled down and maintained for a short time just at the falling edge of the control clock LAT, and the instantaneous output regeneration amplification speed cannot be slowed down due to the introduction of the resistor 326; when the control clock LAT is low, the output latch circuit 320 latches and outputs the comparison result.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A wideband low power comparator circuit comprising an input transconductance circuit (310), two intermediate isolation switches (301 and 302), and an output latch circuit (320);

the input transconductance circuit (310) comprises two NMOS differential pair transistors (311 and 312) and an NMOS bias transistor (313), the sources of the two NMOS differential pair transistors (311 and 312) are connected to the drain of the NMOS bias transistor (313) together, the gates of the two NMOS differential pair transistors (311 and 312) are connected to input voltages Vip and Vin respectively, the drains of the two NMOS differential pair transistors (311 and 312) are connected to the output latch circuit (320) through the corresponding intermediate isolation switches (301 and 302), the drains of the two NMOS differential pair transistors (311 and 312) are connected to the drains of the corresponding intermediate isolation switches (301 and 302), and the source and the gate of the NMOS bias transistor (313) are connected to ground and a bias voltage Vb respectively;

the output latch circuit (320) comprises a first inverter formed by a first PMOS transistor (321) and a first NMOS transistor (323), a second inverter formed by a second PMOS transistor (322) and a second NMOS transistor (324), the first inverter and the second inverter are cross-coupled, and a bistable circuit with reset is formed by the first inverter and the second inverter together with a third NMOS transistor (325); the drains of the first PMOS transistor (321) and the first NMOS transistor (323) are connected, the gates of the first PMOS transistor (321) and the first NMOS transistor (323) are connected to the drain of the third NMOS transistor (325), the sources of the first PMOS transistor (321) and the second PMOS transistor (322) are connected, the sources of the first NMOS transistor (323) and the second NMOS transistor (324) are connected to serve as a negative power supply terminal ns of the bistable circuit, the gates of the first NMOS transistor (323) and the second NMOS transistor (324) are connected to the source of the third NMOS transistor (325), and the drain and the source of the third NMOS transistor (325) are connected to the output terminals Vop and Von of the bistable circuit respectively; the output ends Vop and Von of the bistable circuit are respectively connected to the drains of two NMOS differential pair transistors (312 and 311) in the input transconductance circuit (310) through corresponding intermediate isolating switches (302 and 301); the gates of the two intermediate isolating switches (301 and 302) and the third NMOS transistor (325) are connected to a control clock LAT;

the output latch circuit (320) is characterized by further comprising a current-limiting resistor (326) from the negative power supply end ns of the bistable circuit to ground, and a trigger acceleration branch formed by serially connecting a capacitor (327) and a resistor (328) and used for connecting the control clock LAT and the negative power supply end ns of the bistable circuit, wherein the trigger acceleration branch provides a pull-down current for the negative power supply end ns of the bistable circuit at the falling edge moment of the control clock LAT, the resistance value of the resistor (328) controls the maximum pull-down current value, the capacitance value of the capacitor (327) controls the total discharge amount of the pull-down current, and the product of the resistance value of the resistor (328) and the capacitance value of the capacitor (327) determines the decay time of the pull-down current.

2. A wideband low power comparator circuit according to claim 1, characterized in that the current limiting resistor (326) is an active resistor (326a) or a passive resistor (326 b).