CN106374929B - Quick response dynamic latch comparator - Google Patents
Quick response dynamic latch comparator Download PDFInfo
- Publication number
- CN106374929B CN106374929B CN201611096658.2A CN201611096658A CN106374929B CN 106374929 B CN106374929 B CN 106374929B CN 201611096658 A CN201611096658 A CN 201611096658A CN 106374929 B CN106374929 B CN 106374929B
- Authority
- CN
- China
- Prior art keywords
- unit
- mos transistor
- latch
- comparator
- cross
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention discloses a fast response dynamic latch comparator which comprises a tail switch unit, a pre-amplification input unit, a pre-amplification reset unit, a latch input unit, a cross-coupling latch structure unit, an isolating switch unit, a latch reset unit and a positive feedback unit. The isolation switch unit is cut off in the reset stage, the grid potential of the PMOS tube in the cross-coupling latch structure is made to be the ground GND under the action of the latch input NMOS pair tube, and the grid potential of the NMOS tube in the cross-coupling latch structure is made to be the VDD under the action of the latch reset PMOS pair tube, so that positive feedback is quickly established when the cross-coupling latch structure enters the comparison stage, and the speed of the comparator is further improved. The invention can overcome the defect that the time delay of the traditional double-tail dynamic latch comparator is sharply increased along with the reduction of the differential input voltage on the premise of not increasing the power consumption, reduces the sensitivity of the time delay of the comparator to the differential input voltage and improves the performance of the comparator.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a fast response dynamic latch comparator.
Background
With the rapid development of digital processing technology and semiconductor technology, a large number of analog signals are required to be converted into digital signals for processing, an analog-to-digital converter (ADC) plays an increasingly important role as a bridge for connecting the analog signals and the digital signals, and the rapid development of information transmission also puts higher requirements on the ADC.
The comparator is used as a core module of the ADC, and indexes such as precision, time delay, power consumption and offset of the comparator have important influence on the performance of the whole ADC, even influence on the performance of the whole system. Although the speed of the traditional pre-amplification single-stage dynamic latch comparator is higher compared with that of a static comparator, the power consumption is larger due to the generation of dynamic power consumption; and typically there are multiple MOS transistors stacked from power supply to ground, thus requiring higher supply voltage. The traditional double-tail dynamic latch comparator has no waste of static power consumption, but the delay of the comparator is sharply increased along with the reduction of differential voltage, so that the highest frequency of the comparator which can work is greatly limited, and the speed of the comparator is reduced; and the use of multi-phase clocks adds complexity to the circuit. With the development of semiconductor technology, the delay performance of the traditional dynamic latch comparator under a smaller differential voltage cannot meet the requirement.
Disclosure of Invention
The invention aims to solve the problem that the delay performance of the traditional dynamic latch comparator under a smaller differential voltage cannot meet the requirement, and provides a quick-response dynamic latch comparator.
In order to solve the problems, the invention is realized by the following technical scheme:
a fast response dynamic latch comparator includes a comparator body. The comparator body comprises a tail switch unit, a pre-amplification input unit, a pre-amplification reset unit, a latch input unit, a cross-coupling latch structure unit, a latch reset unit and a positive feedback unit. The difference is that the comparator body further comprises an isolating switch unit, and the isolating switch unit is arranged on the cross-coupling latch structure unit. The isolating switch unit cuts off and cuts off the positive feedback in the reset stage. In the comparison stage, under the action of the latch input NMOS pair transistor, the grid potential of the PMOS transistor in the cross-coupling latch structure is set to be the ground GND, and under the action of the latch reset PMOS pair transistor, the grid potential of the NMOS transistor in the cross-coupling latch structure is set to be the VDD, so that the cross-coupling latch structure can quickly establish positive feedback when entering the comparison stage, and the speed of the comparator body is further improved.
In the above scheme, the tail switch unit inputs the clock signal clk and is connected to the pre-amplification input unit. The tail switch unit is used for providing a discharge channel for the pre-amplification input unit in the comparison stage so as to generate current. The pre-amplification input unit forms an input end of the comparator body, inputs a positive input signal ip and a negative input signal in, and is connected with the pre-amplification reset unit, the tail switch unit and the latch input unit. The pre-amplification input unit is used for amplifying the input voltage signal and then outputting the amplified voltage signal to the latch stage. The pre-amplification reset unit inputs a clock signal clk and is connected with the pre-amplification input unit and the latch input unit. The pre-amplification reset unit is used for pulling up the outputs fp and fn of the pre-amplification reset unit to the power supply VDD in the reset stage. The input end of the latch input unit is connected with the output end of the pre-amplification input unit and is connected with the cross-coupling latch structure unit and the positive feedback unit. The latch input unit is used for converting an input voltage signal into a current signal and pulling down the input of the cross-coupling latch structure unit to the ground GND in the reset stage. The cross-coupling latch structure unit is connected with the latch input unit, the isolating switch unit and the latch reset unit, forms an output end of the comparator body, and outputs a positive output signal outp and a negative output signal outn. The cross-coupled latch structure unit is used for accelerating the discharge speed in the comparison stage and latching data in the latch stage. The isolating switch unit inputs a clock signal clk and is connected with the cross-coupling latch structure unit, the latch reset unit, the latch input unit and the positive feedback unit. The isolating switch unit is used for disconnecting the positive feedback in the reset stage and establishing the positive feedback in the comparison stage. The latch reset unit inputs a clock signal clk and is connected with the cross-coupled latch structure unit and the isolating switch unit. The latch reset unit is used for pulling the output of the comparator body to a power supply VDD in the reset stage. The positive feedback unit is connected with the latch input unit and the cross-coupling latch structure unit. The positive feedback unit is used for being conducted in the comparison stage, and a discharging branch is added to the cross-coupling latch structure unit in the comparison stage.
In the above scheme, the tail switch unit comprises a MOS transistor M 1 . MOS transistor M 1 Is connected to ground GND. MOS transistor M 1 Is connected to a clock signal clk. MOS transistor M 1 Drain of and pre-amplifying input unit MOS transistor M 2 、M 3 Are connected.
In the above scheme, the pre-amplification input unit includes a MOS transistor M 2 ～M 3 . MOS transistor M 2 And MOS transistor M 3 Source and tail switch unit MOS tube M 1 Is connected to the drain of (c). MOS transistor M 2 The gate of which forms the positive input of the comparator body and is connected to a positive input signal ip. MOS transistor M 3 The gate of (a) forms the inverse input terminal of the comparator body, which is connected to the inverse input signal in. MOS transistor M 2 Drain electrode of and MOS tube M 4 After the drain electrodes of (1) are connected, formThe inverse output terminal fn of the input unit is pre-amplified. MOS transistor M 3 Drain electrode of and MOS tube M 5 After the drain electrodes of the pre-amplifying input unit are connected, a positive output end fp of the pre-amplifying input unit is formed.
In the above scheme, the pre-amplification reset unit comprises an MOS transistor M 4 ～M 5 . MOS transistor M 4 And MOS transistor M 5 Is connected to a power supply VDD. MOS transistor M 4 And MOS tube M 5 The gate of which is coupled to a clock signal clk. MOS transistor M 4 Is connected to the inverse output terminal fn of the pre-amplifying input unit. MOS transistor M 5 Is connected to the positive output fp of the pre-amplification input unit.
In the above scheme, the latch input unit includes a positive latch input unit and a negative latch input unit. The positive latch input unit comprises a MOS transistor M 6 . MOS transistor M 6 Is connected to ground GND. MOS transistor M 6 Is connected to the inverse output terminal fn of the pre-amplifying input unit. MOS transistor M 6 The drain electrode of the MOS transistor M is coupled with the cross coupling latch structure unit 8 After the drains of the cross-coupled latch structure units are connected, a positive input terminal v1 of the cross-coupled latch structure unit is formed. The anti-latch input unit comprises a MOS transistor M 7 . MOS transistor M 7 Is connected to ground GND. MOS transistor M 7 Is connected to the positive output fp of the pre-amplifying input unit. MOS transistor M 7 Drain of the cross-coupled latch structure unit and MOS transistor M 9 After the drain electrodes of the cross-coupled latch structure unit are connected, an inverse input end v2 of the cross-coupled latch structure unit is formed.
In the above scheme, the cross-coupled latch structure unit includes an MOS transistor M 8 ～M 11 . MOS transistor M 8 And MOS transistor M 9 Is connected to ground GND. MOS transistor M 10 And MOS transistor M 11 Is connected to a power supply VDD. MOS transistor M 8 Grid and MOS tube M 11 After the drain electrodes of the comparator are connected, a comparator body inverted output terminal outn is formed. MOS transistor M 9 Grid and MOS tube M 10 After connecting, the positive output terminal outp of the comparator body is formed. MOS transistor M 10 Grid and MOS tube M 9 Is connected to the inverted input terminal v2 of the cross-coupled latch structure unit. MOS transistor M 11 Grid and MOS tubeM 8 Is connected to the cross-coupled latch structure cell positive input terminal v1.
In the above scheme, the isolation switch unit includes a positive isolation switch unit and a negative isolation switch unit. The positive isolating switch unit comprises a MOS transistor M 12 . MOS transistor M 12 Is connected to the positive input v1 of the cross-coupled latch structure cell. MOS transistor M 12 Is connected to a clock signal clk. MOS transistor M 12 Is connected to the positive output terminal outp of the comparator body. The anti-isolation switch unit comprises a MOS (metal oxide semiconductor) tube M 13 . MOS transistor M 13 Is connected to the inverted input terminal v2 of the cross-coupled latch structure unit. MOS transistor M 13 Is connected to a clock signal clk. MOS transistor M 13 Is connected to the inverted output terminal outn of the comparator body.
In the above scheme, the latch reset unit includes a positive latch reset unit and a negative latch reset unit. The positive latch reset unit comprises a MOS transistor M 14 . MOS transistor M 14 Is connected to a power supply VDD. MOS transistor M 14 Is connected to a clock signal clk. MOS transistor M 14 Is connected to the positive output terminal outp of the comparator body. The reverse latch reset unit comprises a MOS transistor M 15 . MOS transistor M 15 Is connected to a power supply VDD. MOS transistor M 15 Is connected to a clock signal clk. MOS transistor M 15 Is connected to the inverted output terminal outn of the comparator body.
In the above scheme, the positive feedback unit includes a positive feedback unit and a negative feedback unit. The positive feedback unit comprises an MOS tube M 16 . MOS transistor M 16 Is connected to ground GND. MOS transistor M 16 Is connected to the comparator body anti-output terminal outn. MOS transistor M 16 Is connected to the positive input terminal v1 of the cross-coupled latch structure cell. The positive and negative feedback unit comprises an MOS transistor M 17 . MOS transistor M 17 Is connected to ground GND. MOS transistor M 17 Is connected to the positive output terminal outp of the comparator body. MOS transistor M 17 Is connected to the inverted input terminal v2 of the cross-coupled latch building unit.
Compared with the prior art, the invention has the following characteristics:
1. a pair of isolating switches is added between two positive feedbacks of a comparator latch stage, so that the grid potential of a PMOS tube in a cross coupling latch structure unit is set as ground GND by a latch input NMOS tube in a reset stage, and the grid potential of the NMOS tube in the cross coupling latch structure unit is set as power VDD by the latch reset PMOS tube in the reset stage, therefore, when the comparison stage begins, two groups of positive feedbacks in the cross coupling latch structure unit can be quickly established; the dependence on the input current in the cross-coupled latching structure unit is small, so that the speed of the dynamic comparator is improved, and small delay can be obtained under small differential input voltage;
2. when the dynamic latch comparator works in a comparison stage, a discharge path is added to the circuit, so that the separation of the voltage of the regeneration node is accelerated, the speed of the dynamic latch comparator is further improved, and the dynamic latch comparator is equivalent to a positive feedback unit path;
3. the reset and comparison functions can be realized only by single-phase clock control;
4. on the premise of not increasing power consumption, the defect that the time delay of the traditional double-tail dynamic latch comparator is increased sharply along with the reduction of the differential input voltage is overcome, the sensitivity of the time delay of the comparator to the differential input voltage is reduced, and the performance of the comparator is improved.
Drawings
Fig. 1 is a schematic diagram of a fast response dynamic latch comparator.
Fig. 2 is a comparison of simulation results of the delay with the change of differential voltage of the two-tailed dynamic latch comparator of the present invention.
FIG. 3 shows the simulation result of the rising delay of the present invention.
FIG. 4 shows the simulation result of the descending delay of the present invention.
FIG. 5 shows the result of the functional verification according to the present invention.
Detailed Description
The technical scheme of the invention is described in detail in the following with reference to the accompanying drawings and embodiments:
a fast response dynamic latch comparator, as shown in FIG. 1, includes a tail switch unit, a pre-amplification input unit, a pre-amplification reset unit, a latch input unit, a cross-coupling latch structure unit, an isolation switch unit, a latch reset unit and a positive feedback unit.
A tail switch unit: the pre-amplification input unit is supplied with current during the comparison phase. In the preferred embodiment of the present invention, the tail switch unit comprises a MOS transistor M 1 (ii) a MOS transistor M 1 Is connected to ground GND; MOS transistor M 1 Is connected to a clock signal clk; MOS transistor M 1 Drain electrode of and MOS tube M 2 、M 3 Are connected.
A pre-amplification input unit: the input differential voltage signal is amplified and then output to the latch stage, gain is provided for the latch input signal, the input signal is amplified, and input and output are isolated, so that kickback noise is reduced, and the speed and the precision of the comparator are improved. In the preferred embodiment of the present invention, the pre-amplification input unit comprises a MOS transistor M 2 ～M 3 (ii) a MOS transistor M 2 、M 3 Source electrode and MOS tube M 1 Is connected with the drain electrode of the transistor; MOS transistor M 2 The gate of which is connected to the positive input signal ip of the comparator body; MOS transistor M 3 The grid of the grid is connected with a reverse input signal in of the comparator; MOS transistor M 2 Drain electrode of and MOS tube M 4 After the drain electrodes of the pre-amplification input unit are connected, a pre-amplification input unit reverse output end fn is formed; MOS transistor M 3 Drain electrode of and MOS tube M 5 The drains of the pre-amplifying input unit are connected to form a positive output end fp of the pre-amplifying input unit.
A pre-amplification reset unit: in the reset stage, the input end of the latch input unit, namely the pre-amplification output end, is pulled up to a power supply VDD, and the pre-amplification output end is reset; cut off in the comparison phase. In a preferred embodiment of the present invention, the pre-amplifying reset unit comprises a MOS transistor M 4 ～M 5 (ii) a MOS transistor M 4 、M 5 Is connected with a power supply VDD; MOS transistor M 4 、M 5 The gate of which is connected to a clock signal clk; MOS transistor M 4 The drain electrode of the pre-amplifying input unit is connected with the reverse output end fn of the pre-amplifying input unit; MOS transistor M 5 Drain electrode and preThe positive output end fp of the amplifying input unit is connected.
A latch input unit: the input voltage signal is converted into a current signal, the current signal is isolated and output, and kickback noise is reduced, namely the input of the cross-coupling latch structure unit is pulled down to the ground GND in the reset stage. In the preferred embodiment of the present invention, the latch input unit comprises a MOS transistor M 6 ～M 7 (ii) a MOS transistor M 6 、M 7 The source of (2) is connected with the ground GND; MOS transistor M 6 The grid of the pre-amplifying input unit is connected with the inverse output end fn of the pre-amplifying input unit; MOS transistor M 7 The grid electrode of the pre-amplifying input unit is connected with the positive output end fp of the pre-amplifying input unit; MOS transistor M 6 Drain electrode of and MOS tube M 8 The drains are connected to form a positive input end v1 of the cross-coupled latch structure unit; MOS transistor M 7 Drain electrode of (3) and MOS tube M 9 The drains of the latch units are connected to form a cross-coupled latch structure unit inverse input terminal v2.
A cross-coupled latch structure unit: the comparison function is completed and two positive feedbacks are used to accelerate the comparison speed, i.e. the discharge speed is accelerated in the comparison stage and the data is latched in the latch stage. In the preferred embodiment of the present invention, the cross-coupled latch structure unit includes a MOS transistor M 8 ～M 11 (ii) a MOS transistor M 8 、M 9 The source of (2) is connected with the ground GND; MOS transistor M 10 、M 11 The source of the transistor is connected with a power supply VDD; MOS transistor M 8 Grid of (3) and MOS tube M 11 After the drain electrodes of the comparator are connected, an output end outn of the comparator body is formed; MOS transistor M 9 Grid and MOS tube M 10 After the drain electrodes of the comparator are connected, a positive output end outp of the comparator body is formed; MOS transistor M 10 Grid and MOS tube M 9 The drain electrode of the cross coupling latch structure unit is connected with the inverse input end v2 of the cross coupling latch structure unit; MOS transistor M 11 Grid and MOS tube M 8 Is connected to the cross-coupled latch structure cell positive input terminal v1.
An isolation switch unit: in the reset stage, the positive feedback is cut off, and the PMOS transistor M in the cross-coupling latch structure unit is enabled to be under the action of the latch input NMOS transistor pair 10 、M 11 The grid of the cross-coupling latch structure unit is pulled down to the ground GND, and the NMOS tube M in the cross-coupling latch structure unit is driven by the latch reset PMOS pair tube 8 、M 9 The grid electrode of the cross coupling latch structure unit is pulled up to a power supply VDD, so that positive feedback can be quickly established when the cross coupling latch structure unit enters a comparison stage, and the speed of the comparator is further improved; and in the comparison stage, conducting to enable the two branches of the cross-coupling latch structure unit to have current flowing through, establishing positive feedback, enabling the cross-coupling latch structure unit to normally work, comparing input signals and then outputting the compared signals. In a preferred embodiment of the present invention, the isolation switch unit includes a MOS transistor M 12 ～M 13 (ii) a MOS transistor M 12 The source electrode of the cross-coupled latch structure unit is connected with the positive input end v1 of the cross-coupled latch structure unit; MOS transistor M 13 The source electrode of the cross coupling latch structure unit is connected with the inverse input end v2 of the cross coupling latch structure unit; MOS transistor M 12 、M 13 Is connected to a clock signal clk; MOS transistor M 12 The drain of which is connected with the positive output end outp of the comparator body; MOS transistor M 13 The drain of the comparator is connected with the inverse output end outn of the comparator body;
a latch reset unit: in the reset stage, the output end of the comparator is pulled to VDD; cut off in the comparison phase. In a preferred embodiment of the present invention, the latch reset unit includes a MOS transistor M 14 ～M 15 (ii) a MOS transistor M 14 、M 15 Is connected with a power supply VDD; MOS transistor M 14 、M 15 Is connected to a clock signal clk; MOS transistor M 14 The drain of the comparator is connected with the positive output end outp of the comparator body; MOS transistor M 15 Is connected to the comparator body anti-output terminal outn.
A positive feedback unit: and in the comparison stage, the connection is carried out, a discharge branch is added, and the speed of the comparator is improved. In the preferred embodiment of the present invention, the positive feedback unit comprises a MOS transistor M 16 ～M 17 (ii) a MOS transistor M 16 、M 17 The source of (2) is connected to ground GND; MOS transistor M 16 The grid of the comparator is connected with the negative output end outn of the comparator body; MOS transistor M 17 The grid of the comparator is connected with the positive output end outp of the comparator body; MOS transistor M 16 The drain electrode of the cross-coupled latch structure unit is connected with the positive input end v1 of the cross-coupled latch structure unit; MOS transistor M 17 Is connected with the inverse input terminal v2 of the cross-coupled latch structure unit.
The working process of the invention can be divided into three stages.
A reset stage: when clk is low, MOS transistor M 1 、M 12 、M 13 Cut-off, MOS transistor M 4 、M 5 、M 14 、M 15 Conducting, pulling fn, fp, outp and outn high, and using MOS transistor M 6 、M 7 Turning on, the v1 and v2 potentials are pulled down to the ground GND.
And a comparison stage: when clk rises from low level to high level, MOS transistor M 4 、M 5 、M 14 、M 15 Cutoff, M 1 Is conducted to MOS tube M 2 Branch circuit and MOS tube M 3 The branch circuit provides a discharge channel to generate discharge current, and the MOS transistor M 14 、M 15 Cutoff, M 12 、M 13 Is conducted to MOS tube M 8 、M 12 、M 10 Branch and MOS tube M 9 、M 13 、M 11 The branch circuit provides current to conduct the branch circuit, and the difference of the positive input signal ip and the negative input signal in voltage of the comparator body enables the voltages of the pre-amplification input positive output end fp and the pre-amplification input negative output end fp to be reduced at different speeds. MOS transistor M 6 Branch circuit and MOS tube M 7 The branches discharge at different speeds under the control of fn and fp, resulting in MOS transistor M 8 、M 12 、M 10 Branch and MOS tube M 9 、M 13 、M 11 The current mismatch of the branch circuits, the voltage of outp and outn is reduced at different speeds, and an MOS tube M in the cross-coupled latch unit 8 、M 9 And MOS transistor M 10 、M 11 Under the action of two sets of positive feedback, one end is discharged quickly, the potential is continuously reduced, one end is charged quickly, the potential is raised again, and the MOS transistor M 16 、M 17 A discharge channel is added to one side of the output end outn and outp under the control of the voltage of the output end outn and outp, so that the MOS transistor M is intensified 8 、M 12 、M 10 Branch and MOS tube M 9 、M 13 、M 11 And due to the current mismatch of the branch circuits, the separation speed of the potentials of outp and outn is increased, the speed of the comparator is increased, and the final end of the comparator body for outputting outp and outn is high level while the other end is low level.
A latching stage: clk remains high and the comparison ends, all voltages remaining unchanged.
Since the MOS transistor M 4 、M 5 Before the comparison stage, the pre-amplification output nodes fn and fp are pulled to a power supply VDD, and an MOS tube M 6 、M 7 Pulling down the input ends v1 and v2 of the cross-coupled latch structure unit to the ground GND under the action of fn and fp, and using an MOS tube M 14 、M 15 The output nodes outp and outn of the comparator are pulled up to the power supply VDD, so that all the nodes in the circuit are reset to a determined voltage value, the memory function of the comparator is eliminated, the comparison result of the comparator is not influenced by the previous comparison result, and the precision of the comparator is improved; in addition, before the comparison stage, the input ends v1 and v2 of the cross-coupling latch structure unit are pulled down to GND, and the output nodes outp and outn of the comparator are pulled up to VDD, so that when the cross-coupling latch structure unit enters the comparison stage, positive feedback can be quickly established, the dependence on the magnitude of the input current of the cross-coupling latch structure unit is reduced, and the speed of the comparator is improved; pre-amplifying circuit and latch input MOS tube M 6 、M 7 The use of the comparator enables multi-stage isolation between the input signal and the output signal, thereby reducing the influence of kickback noise and improving the precision of the comparator; the pre-amplification input circuit provides certain gain for the input signal, and increases the voltage difference value input by the latch stage, thereby improving the precision of the comparator; tail switch MOS tube M 1 The pseudo current source is used for providing current for the pre-amplification input unit in a comparison stage, and replaces a static current source in a traditional pre-amplification circuit, so that the power consumption of the comparator is reduced; MOS tube M of positive feedback unit 16 、M 17 In the comparison stage, a stage of positive feedback is added to the cross-coupled latch structure unit, and a discharge channel is added, so that the speed of the comparator is improved.
The invention and the traditional double-tail dynamic latch comparator are designed and simulated by adopting an SMIC 0.18um CMOS process, the power supply voltage is 1.8V, and the sampling clock is 1GHz. Compared with the simulation result of the traditional double-tail dynamic latch comparator, which changes along with the change of differential voltage, the simulation result of the invention is shown in figure 2. Simulation results show that when the input differential voltage is small, the time delay of the traditional double-tail dynamic latching comparator is increased sharply, the time delay of the invention is stable and is always maintained within 200ps, and the time delay performance is greatly improved. The invention is simulated under the condition that the input swing amplitude is 900mV triangle wave signals. The simulation result of the rising delay of the invention is shown in fig. 3, the simulation result of the falling delay of the invention is shown in fig. 4, and the function verification result of the invention is shown in fig. 5. Simulation results show that the delay of the invention under the condition of inputting a large signal is only 90.797ps. Therefore, the invention can overcome the defect that the time delay of the traditional double-tail dynamic latch comparator is increased rapidly along with the reduction of the differential input voltage on the premise of not increasing the power consumption, reduces the sensitivity of the time delay of the comparator to the differential input voltage and improves the performance of the comparator.
Claims (8)
1. A fast response dynamic latch comparator includes a comparator body; the comparator body comprises a tail switch unit, a pre-amplification input unit, a pre-amplification reset unit, a latch input unit, a cross-coupling latch structure unit, a latch reset unit, a positive feedback unit and an isolating switch unit; the method is characterized in that:
the tail switch unit inputs a clock signal clk and is connected with the pre-amplification input unit; the tail switch unit is used for providing a discharge channel for the pre-amplification input unit in the comparison stage so as to generate current;
the pre-amplification input unit forms an input end of the comparator body, inputs a positive input signal ip and a negative input signal in, and is connected with the pre-amplification reset unit, the tail switch unit and the latch input unit; the pre-amplification input unit is used for amplifying an input voltage signal and then outputting the amplified voltage signal to the latch stage;
the preamplification reset unit inputs a clock signal clk and is connected with the preamplification input unit and the latch input unit; the pre-amplification resetting unit is used for pulling up the outputs fp and fn of the pre-amplification resetting unit to a power supply VDD in a resetting stage;
the input end of the latch input unit is connected with the output end of the pre-amplification input unit and is connected with the cross-coupling latch structure unit and the positive feedback unit; the latch input unit is used for converting an input voltage signal into a current signal and pulling down the input of the cross-coupling latch structure unit to the ground GND in a reset stage;
the cross-coupling latch structure unit is connected with the latch input unit, the isolating switch unit and the latch reset unit, forms an output end of the comparator body, and outputs a positive output signal outp and a negative output signal outn; the cross coupling latching structure unit is used for accelerating the discharging speed in the comparison stage and latching data in the latching stage; the cross-coupling latch structure unit comprises an MOS tube M 8 ～M 11 (ii) a MOS transistor M 8 And MOS transistor M 9 The source of (2) is connected with the ground GND; MOS transistor M 10 And MOS transistor M 11 The source of the transistor is connected with a power supply VDD; MOS transistor M 8 Grid and MOS tube M 11 After the drain electrodes of the comparator are connected, an output end outn of the comparator body is formed; MOS transistor M 9 Grid and MOS tube M 10 After the drain electrodes of the comparator are connected, a positive output end outp of the comparator body is formed; MOS transistor M 10 Grid and MOS tube M 9 The drain electrode of the cross coupling latch structure unit is connected with an inverse input end v2 of the cross coupling latch structure unit; MOS transistor M 11 Grid and MOS tube M 8 The drain electrode of the cross-coupling latch structure unit is connected with the positive input end v1 of the cross-coupling latch structure unit;
the isolation switch unit is arranged on the cross-coupling latch structure unit; the isolating switch unit inputs a clock signal clk and is connected with the cross-coupling latching structure unit, the latching reset unit, the latching input unit and the positive feedback unit; the isolating switch unit is used for disconnecting the positive feedback in the reset stage and establishing the positive feedback in the comparison stage; in the resetting stage, the positive feedback is cut off and disconnected; in the comparison stage, under the action of latching input NMOS (N-channel metal oxide semiconductor) geminate transistors, the grid potential of a PMOS (P-channel metal oxide semiconductor) transistor in the cross-coupling latching structure is set as ground GND (ground), and under the action of latching reset PMOS geminate transistors, the grid potential of the NMOS transistor in the cross-coupling latching structure is set as VDD (voltage-to-noise), so that the cross-coupling latching structure can quickly establish positive feedback when entering the comparison stage, and the speed of the comparator body is further improved;
the latch reset unit inputs a clock signal clk and is connected with the cross-coupling latch structure unit and the isolating switch unit; the latch reset unit is used for pulling the output of the comparator body to a power supply VDD in a reset stage;
the positive feedback unit is connected with the latch input unit and the cross-coupling latch structure unit; the positive feedback unit is used for conducting in the comparison stage and enabling the cross-coupling latch structure unit to be additionally provided with a discharge branch in the comparison stage.
2. A fast response dynamic latch comparator as recited in claim 1, wherein: the tail switch unit comprises an MOS tube M 1 (ii) a MOS transistor M 1 Is connected to ground GND; MOS transistor M 1 Is connected to a clock signal clk; MOS transistor M 1 Drain of and pre-amplifying input unit MOS transistor M 2 、M 3 Are connected.
3. A fast response dynamic latching comparator as claimed in claim 1, wherein: the pre-amplification input unit comprises an MOS (metal oxide semiconductor) tube M 2 ～M 3 (ii) a MOS transistor M 2 And MOS transistor M 3 Source and tail switch unit MOS tube M 1 Is connected with the drain electrode of the transistor; MOS transistor M 2 The gate of which forms the positive input end of the comparator body and is connected with a positive input signal ip; MOS transistor M 3 The grid electrode of the comparator forms an inverse input end of the comparator body and is connected with an inverse input signal in; MOS transistor M 2 Drain electrode of and MOS tube M 4 After the drain electrodes of the pre-amplification input unit are connected, an inverse output end fn of the pre-amplification input unit is formed; MOS transistor M 3 Drain electrode of and MOS tube M 5 After the drain electrodes of the pre-amplifying input unit are connected, a positive output end fp of the pre-amplifying input unit is formed.
4. A fast response dynamic latching comparator as claimed in claim 1, wherein: the pre-amplification reset unit comprises an MOS (metal oxide semiconductor) tube M 4 ～M 5 (ii) a MOS transistor M 4 And MOS tube M 5 Is connected with a power supply VDD; MOS transistor M 4 And MOS transistor M 5 The gate of which is connected to a clock signal clk; MOS transistor M 4 The drain of the pre-amplifying input unit is connected with an inverted output end fn of the pre-amplifying input unit; MOS transistor M 5 Is connected to the positive output fp of the pre-amplification input unit.
5. A fast response dynamic latching comparator as claimed in claim 1, wherein: the latch input unit comprises a positive latch input unit and a negative latch input unit;
the positive latch input unit comprises a MOS transistor M 6 (ii) a MOS transistor M 6 The source of (2) is connected with the ground GND; MOS transistor M 6 The grid of the pre-amplifying input unit is connected with an inverted output end fn of the pre-amplifying input unit; MOS transistor M 6 The drain electrode of the MOS transistor M is coupled with the cross coupling latch structure unit 8 After the drain electrodes of the cross-coupled latch structure unit are connected, a positive input end v1 of the cross-coupled latch structure unit is formed;
the anti-latch input unit comprises a MOS transistor M 7 (ii) a MOS transistor M 7 The source of (2) is connected with the ground GND; MOS transistor M 7 The grid electrode of the pre-amplifying input unit is connected with the positive output end fp of the pre-amplifying input unit; MOS transistor M 7 The drain electrode of the MOS transistor M is coupled with the cross coupling latch structure unit 9 After the drain electrodes of the cross-coupled latch structure unit are connected, an inverse input end v2 of the cross-coupled latch structure unit is formed.
6. A fast response dynamic latching comparator as claimed in claim 1, wherein: the isolating switch unit comprises a positive isolating switch unit and a negative isolating switch unit;
the positive isolating switch unit comprises a MOS transistor M 12 (ii) a MOS transistor M 12 The source of the cross-coupled latch structure unit is connected with the positive input end v1 of the cross-coupled latch structure unit; MOS transistor M 12 Is connected to a clock signal clk; MOS transistor M 12 Is connected with the positive output end outp of the comparator body;
the anti-isolation switch unit comprises an MOS tube M 13 (ii) a MOS transistor M 13 The source electrode of the cross coupling latch structure unit is connected with an inverse input end v2 of the cross coupling latch structure unit; MOS transistor M 13 Is connected to a clock signal clk; MOS transistor M 13 Is connected to the inverted output terminal outn of the comparator body.
7. A fast response dynamic latching comparator as claimed in claim 1, wherein: the latching reset unit comprises a positive latching reset unit and a negative latching reset unit;
the positive latch reset unit comprises a MOS transistor M 14 (ii) a MOS transistor M 14 Is connected with a power supply VDD; MOS transistor M 14 Is connected to a clock signal clk; MOS transistor M 14 Is connected with the positive output end outp of the comparator body;
the reverse latch reset unit comprises a MOS transistor M 15 (ii) a MOS transistor M 15 Is connected with a power supply VDD; MOS transistor M 15 Is connected to a clock signal clk; MOS transistor M 15 Is connected to the inverse output terminal outn of the comparator body.
8. A fast response dynamic latching comparator as claimed in claim 1, wherein: the positive feedback unit comprises a positive feedback unit and a negative feedback unit;
the positive feedback unit comprises an MOS tube M 16 (ii) a MOS transistor M 16 The source of (2) is connected to ground GND; MOS transistor M 16 The grid of the comparator is connected with the negative output end outn of the comparator body; MOS transistor M 16 The drain of the cross-coupled latch structure unit is connected with the positive input end v1 of the cross-coupled latch structure unit;
the positive and negative feedback unit comprises an MOS transistor M 17 (ii) a MOS transistor M 17 The source of (2) is connected with the ground GND; MOS transistor M 17 The grid of the comparator is connected with the positive output end outp of the comparator body; MOS transistor M 17 Is connected to the inverted input terminal v2 of the cross-coupled latch structure unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611096658.2A CN106374929B (en) | 2016-12-02 | 2016-12-02 | Quick response dynamic latch comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611096658.2A CN106374929B (en) | 2016-12-02 | 2016-12-02 | Quick response dynamic latch comparator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106374929A CN106374929A (en) | 2017-02-01 |
| CN106374929B true CN106374929B (en) | 2023-04-11 |
Family
ID=57891177
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611096658.2A Active CN106374929B (en) | 2016-12-02 | 2016-12-02 | Quick response dynamic latch comparator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106374929B (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107944099B (en) * | 2017-11-10 | 2021-12-07 | 东南大学 | High-speed high-precision comparator circuit design |
| CN108494406B (en) * | 2018-03-23 | 2022-03-18 | 上海唯捷创芯电子技术有限公司 | High-speed dynamic latch type comparator, chip and communication terminal |
| CN108540130A (en) * | 2018-04-10 | 2018-09-14 | 中国科学院微电子研究所 | Dynamic comparator |
| CN108964639A (en) * | 2018-06-06 | 2018-12-07 | 电子科技大学 | A kind of two-way hysteresis comparator |
| CN109613328B (en) * | 2019-01-14 | 2020-11-27 | 电子科技大学 | Cross-coupling rapid overcurrent detection circuit |
| CN114070274A (en) * | 2020-08-10 | 2022-02-18 | 长鑫存储技术有限公司 | Comparator with a comparator circuit |
| EP4195508A4 (en) | 2020-08-10 | 2024-02-07 | Changxin Memory Technologies, Inc. | Comparator |
| CN112653433B (en) * | 2020-12-14 | 2023-05-09 | 重庆百瑞互联电子技术有限公司 | Hybrid double-tail dynamic latching comparator |
| US11626869B2 (en) | 2021-07-12 | 2023-04-11 | Changxin Memory Technologies, Inc. | Comparator and decision feedback equalization circuit |
| CN113556104B (en) * | 2021-07-12 | 2022-08-09 | 长鑫存储技术有限公司 | Comparator and decision feedback equalization circuit |
| CN113472327B (en) * | 2021-08-17 | 2023-06-20 | 安徽大学 | High-speed low-power-consumption double-tail current dynamic comparator circuit |
| CN114389585A (en) * | 2022-01-13 | 2022-04-22 | 电子科技大学 | High-speed low-offset latch comparator |
| TWI835095B (en) * | 2022-03-21 | 2024-03-11 | 瑞昱半導體股份有限公司 | Low kickback noise comparator |
| CN116488622B (en) * | 2023-04-03 | 2024-02-02 | 广东工业大学 | Low-power consumption dynamic comparator |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101562441A (en) * | 2008-10-08 | 2009-10-21 | 西安电子科技大学 | Ultrahigh-speed comparator with low offset |
| CN104242879A (en) * | 2013-06-20 | 2014-12-24 | 西安电子科技大学 | High-speed low-imbalance dynamic comparator for high-speed analog-digital converter |
| CN105375910A (en) * | 2015-10-23 | 2016-03-02 | 广州金升阳科技有限公司 | Zero crossing comparison method and zero crossing comparator |
| CN106026996A (en) * | 2016-06-01 | 2016-10-12 | 桂林电子科技大学 | Positive feedback isolating dynamic latch comparator |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6597303B2 (en) * | 2001-08-16 | 2003-07-22 | Hrl Laboratories, Llc | Comparator with very fast regeneration time constant |
| US6831579B2 (en) * | 2002-06-06 | 2004-12-14 | Analog Devices, Inc. | BiCMOS latches with NPN control devices for current limiting of NPN regeneration devices |
-
2016
- 2016-12-02 CN CN201611096658.2A patent/CN106374929B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101562441A (en) * | 2008-10-08 | 2009-10-21 | 西安电子科技大学 | Ultrahigh-speed comparator with low offset |
| CN104242879A (en) * | 2013-06-20 | 2014-12-24 | 西安电子科技大学 | High-speed low-imbalance dynamic comparator for high-speed analog-digital converter |
| CN105375910A (en) * | 2015-10-23 | 2016-03-02 | 广州金升阳科技有限公司 | Zero crossing comparison method and zero crossing comparator |
| CN106026996A (en) * | 2016-06-01 | 2016-10-12 | 桂林电子科技大学 | Positive feedback isolating dynamic latch comparator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106374929A (en) | 2017-02-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106374929B (en) | Quick response dynamic latch comparator | |
| CN111200402B (en) | High-linearity dynamic residual error amplifier circuit capable of improving gain | |
| CN111446966B (en) | Single-phase clock high-speed low-power consumption dynamic comparator applied to SAR ADC | |
| US20060255859A1 (en) | Method and apparatus for improved clock preamplifier with low jitter | |
| CN107565966B (en) | Comparator applied to high-speed assembly line ADC | |
| CN115333515A (en) | Dynamic comparator with low kickback noise | |
| CN112187226A (en) | Low-voltage low-power-consumption dynamic comparator | |
| CN101841315A (en) | High speed comparator | |
| US9197198B2 (en) | Latch comparator circuits and methods | |
| Rabbi et al. | Design of a low-power ultra high speed dynamic latched comparator in 90-nm CMOS technology | |
| CN114389585A (en) | High-speed low-offset latch comparator | |
| CN112910447A (en) | Low-power-consumption comparator circuit with rail-to-rail input swing amplitude | |
| CN111313871B (en) | Dynamic pre-amplification circuit and dynamic comparator | |
| CN112910452A (en) | Low-offset low-power-consumption high-speed dynamic comparator and application thereof | |
| Shubhanand et al. | Design and simulation of a high speed CMOS comparator | |
| Chiwande et al. | Performance analysis of low voltage, low power dynamic double tail comparator for data convertor application | |
| CN215682235U (en) | Circuit and comparator | |
| CN113067557B (en) | High-speed full-differential comparator circuit with voltage conversion | |
| Al-Qadasi et al. | A high speed dynamic strongarm latch comparator | |
| Zhuang et al. | A back-gate-input clocked comparator with improved speed and reduced noise in 22-nm SOI CMOS | |
| CN115412077A (en) | High-speed low-power consumption prepositive latch comparator | |
| CN111130512B (en) | Quick comparison circuit and electronic equipment | |
| Lahariya et al. | Design of low power and high speed dynamic latch comparator using 180 nm technology | |
| Srivastava et al. | Analysis and Design of Low Voltage Low Power Inverter Based Double Tail Comparator | |
| Manikandan et al. | A comparative study of high performance dynamic comparators using strained silicon technology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |