CN111756375B - High-linearity low-voltage input buffer circuit - Google Patents
High-linearity low-voltage input buffer circuit Download PDFInfo
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- CN111756375B CN111756375B CN202010589767.8A CN202010589767A CN111756375B CN 111756375 B CN111756375 B CN 111756375B CN 202010589767 A CN202010589767 A CN 202010589767A CN 111756375 B CN111756375 B CN 111756375B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
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Abstract
The invention relates to a high linearity low voltage input buffer circuit, comprising: NMOS transistor M N1 、M N3 And M N2 、M N6 A main buffer respectively forming positive and negative input ends; PMOS transistor M P1 、M P3 And M P2 、M P4 Respectively forming auxiliary buffers; NMOS transistor M N3 、M N4 And M N5 、M N6 Respectively form a replica current amplifier and a replica capacitor C c The invention adopts the auxiliary buffer to simulate the load effect of the main buffer to generate the copy current of the load current, then the copy current is mirrored to the load transistor of the main buffer through the current amplifier, and the load capacitor is charged and discharged through the load transistor, thereby keeping the current of the input transistor constant and eliminating the nonlinearity caused by the load current.
Description
Technical Field
The invention belongs to the field of integrated circuit design, and particularly relates to a high-linearity low-voltage input buffer circuit which is mainly applied to isolation of package parasitic parameters and sample-hold network kickback noise when designing a high-speed high-precision analog-to-digital converter, and can also be applied to other signal processing systems with high-linearity buffering requirements.
Background
With the development of semiconductor technology, the resolution and sampling rate of the ADC are rapidly developed, and the influence of package parasitic parameters and sample-hold network kickback noise on the input signal of the ADC is more and more serious. One common approach is to integrate an input buffer inside the ADC, isolate the input signal from the sample and hold circuit, and reduce the load of the input signal. However, the input buffer is at the front end of the system input, and its performance will determine the upper performance limit that the system can achieve as a whole, and in a high-speed high-precision signal processing system, an analog signal buffer with low voltage, low power consumption and high performance is increasingly important.
Patent US8339161B2 of US ADI (Analog Devices) discloses a solution for generating a replica current compensation load current by means of a replica impedance, the circuit structure of which is shown in fig. 1. The structure is connected with a duplication impedance which is identical with the load impedance at the input end to generate duplication current, and the duplication current is injected into the load through the stacked cascode tube by adding the stacked cascode tube to the buffer, so that the current of the input tube is kept constant, and the linearity is improved. The circuit structure can effectively solve the problem of nonlinear transconductance of the input transistor caused by load current, but requires additional stacked transistors to limit the reduction of the power supply voltage.
US9628099B2, US TI (Texas Instruments), discloses a load current compensated analog input buffer structure with circuit configuration see fig. 2 and 3. The structure is formed by a capacitor C 1 And negative side input voltage V inn Generating a load C L Current of opposite phase passes through current mirror Q 3 Mirror inflow buffer load Q 2 So as to flow through the input pipe Q 1 Is substantially constant, eliminating nonlinear effects caused by load current. The TI patent uses current mirror amplification to compensate for the load current mirror, eliminating the problem of the ADI patent requiring additional stacked transistors, but if the circuit configuration shown in fig. 2 is used, replicating capacitor C 1 Directly accessing the input will increase the input load, and if the circuit structure shown in fig. 3 is adopted, the auxiliary buffer will effectively reduce the input load, but an additional load current mirror branch I is needed bias And the system power consumption is increased.
In addition, the replica impedance and the output impedance of the ADI company patent are completely the same, so that the input signal load cannot be reduced, and the area is wasted; the TI patent uses a current mirror to amplify the replica capacitor C 1 Reduced to load capacitance C L N times (N-bit current mirror magnification), but still requires a larger replica capacitor size.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: solves the problems that in the prior art, an additional stack tube is required to be introduced into a main buffer to limit the reduction of the power supply voltage, and eliminates the problem that the input load cannot be effectively reduced in the prior art or a main buffer load bias circuit I is required to be additionally introduced Bias Meanwhile, the size of the compensation capacitor is further reduced, and the power consumption and the area are effectively reduced.
To solve the above technical problems, the present invention provides a high linearity low voltage input buffer circuit, a positive input terminal V IP And a negative input terminal V IN Using differential inputs, characterised by M P1 、M P3 Constitute the positive input terminal V IP Main buffer of M P2 、M P6 Form the negative input terminal V IN Main buffer of M N1 、M N3 And M N2 、M N4 Respectively form auxiliary buffers M P3 、M P4 And M P5 、M P6 Respectively forming a replication current amplifier; wherein M is N1 、M N2 、M N3 、M N4 Is NMOS transistor, M P1 、M P2 、M P3 、M P4 、M P5 、M P6 The low voltage input buffer circuit also comprises a replica capacitor C as a PMOS transistor c ；
M N1 Gate of (2) is connected to positive input terminal V IP ，M N1 Is connected with a power supply V DD ，M N1 Source electrode of (C) and M N3 Is connected with the drain electrode of M N3 The source electrode of the transistor is grounded; m is M N3 Gate and M of (2) N4 Is connected with the grid electrode of M N4 Is connected to the drain thereof and to M P3 A drain electrode of (2); m is M N4 The source electrode of the transistor is grounded; m is M P3 Gate of (2) is connected to positive input terminal V IP ，M P3 Source connection M of (2) P1 Drain electrode of M P1 Is connected with the bias voltage V B ，M P1 Is connected with a power supply V DD ；
M N2 Is connected with the negative input terminal V IN ，M N2 Is connected with a power supply V DD ，M N2 Is a source of (a)Pole and M N6 Is connected with the drain electrode of M N6 The source electrode of the transistor is grounded; m is M N6 Gate and M of (2) N5 Is connected with the grid electrode of M N5 Is connected to the drain thereof and to M P4 A drain electrode of (2); m is M N5 The source electrode of the transistor is grounded; m is M P4 Is connected with the negative input terminal V IN ，M P4 Source connection M of (2) P2 Drain electrode of M P2 Is connected with the bias voltage V B ，M P2 Is connected with a power supply V DD ；
Wherein M is N1 Source electrode of (C) and M N3 The connection point of the drain electrode of (2) is a positive output end V OUP ，M N2 Source electrode of (C) and M N6 The connection point of the drain electrode of (C) is a negative output terminal V OUN ；M P3 Source electrode of (C) and M P1 Is connected to the replica capacitor C c Is one end of M P4 Source electrode of (C) and M P2 Is connected to the replica capacitor C c And the other end of (2).
In the above scheme, the positive output terminal V of the low-voltage input buffer circuit OUP And a negative output terminal V OUN Respectively connected with the respective load capacitors C L 。
In the above scheme, M N3 、M N4 And M N5 、M N6 The amplification factor of the separately configured replica current amplifier is N.
In the above scheme, the replica capacitor C c Is of the size of the load capacitance C L 1/(2N) times.
In addition, the dual replacement of the PMOS and the NMOS in the scheme can also solve the technical problems, under the scheme, M P1 、M P3 Constitute the positive input terminal V IP Main buffer of M P2 、M P6 Form the negative input terminal V IN Main buffer of M N1 、M N3 And M N2 、M N4 Respectively form auxiliary buffers M P3 、M P4 And M P5 、M P6 Respectively forming a replication current amplifier; wherein M is N1 、M N2 、M N3 、M N4 Is NMOS transistor, M P1 、M P2 、M P3 、M P4 、M P5 、M P6 The low voltage input buffer circuit also comprises a replica capacitor C as a PMOS transistor c ；
M P1 Gate of (2) is connected to positive input terminal V IP ，M P1 Is grounded at the drain electrode of M P1 Source electrode of (C) and M P3 Is connected with the drain electrode of M P3 Is connected with a power supply V DD ；M P3 Gate and M of (2) P4 Is connected with the grid electrode of M P4 Is connected to the drain thereof and to M N3 A drain electrode of (2); m is M P4 Is connected with a power supply V DD ；M N3 Gate of (2) is connected to positive input terminal V IP ，M N3 Source connection M of (2) N1 Drain electrode of M N1 Is connected with the bias voltage V B ，M N1 The source electrode of the transistor is grounded;
M P2 is connected with the negative input terminal V IN ，M P2 Is grounded at the drain electrode of M P2 Source electrode of (C) and M P6 Is connected with the drain electrode of M P6 Is connected with a power supply V DD ；M P6 Gate and M of (2) P5 Is connected with the grid electrode of M P5 Is connected to the drain thereof and to M N4 A drain electrode of (2); m is M P5 Is connected with a power supply V DD ；M N4 Is connected with the negative input terminal V IN ，M N4 Source connection M of (2) N2 Drain electrode of M N2 Is connected with the bias voltage V B ，M N2 The source electrode of the transistor is grounded;
wherein M is P1 Source electrode of (C) and M P3 The connection point of the drain electrode of (2) is a positive output end V OUP ，M P2 Source electrode of (C) and M P6 The connection point of the drain electrode of (C) is a negative output terminal V OUN ；M N3 Source electrode of (C) and M N1 Is connected to the replica capacitor C c Is one end of M N4 Source electrode of (C) and M N2 Is connected to the replica capacitor C c And the other end of (2).
Compared with the prior art, the invention has the beneficial effects that:
(1) Simulating the load effect of main buffer by using auxiliary buffer, using auxiliary buffer and two auxiliary buffersReplica capacitor C connected with output node of the device c Generating a replica current i C The replica current is then mirrored to the load transistor of the main buffer via a current amplifier for compensating the load capacitance C L The charging and discharging current (load current) of the main buffer input tube is constant, the overall linearity is improved, and the problem that extra stacked transistors are required to be introduced into the main buffer in the prior art is solved;
(2) The auxiliary buffer is adopted to effectively reduce the input load, and the main buffer load current mirror bias generation branch I is not required to be additionally introduced bias Compared with the prior art, the input load is reduced, and the overall power consumption of the system is reduced;
(3) The two ends of the load capacitor (replication capacitor) of the auxiliary buffer are respectively connected with the positive output end and the negative output end of the auxiliary buffer, so that the size of the replication capacitor can be further reduced by half, and the area and the power consumption of a chip are reduced.
Drawings
FIG. 1 is a prior art input buffer structure employing replica impedance to generate a replica current to compensate for load current;
FIG. 2 is a prior art input buffer structure 1 employing load current compensation;
FIG. 3 is a prior art input buffer structure 2 employing load current compensation;
fig. 4 is a circuit configuration of a high linearity low voltage input buffer according to an embodiment of the present invention.
Fig. 5 is a circuit configuration of a high linearity low voltage input buffer according to another embodiment of the present invention.
Detailed Description
The following describes specific embodiments of the present invention in detail with reference to the drawings.
In one embodiment, the structure of the high-linearity low-voltage input buffer circuit provided by the invention is shown in fig. 4, and the positive input terminal V IP And a negative input terminal V IN Using differential inputs, where M P1 、M P3 Constitute the positive input terminal V IP Main buffer of M P2 、M P6 Form the negative input terminal V IN Main buffer of M N1 、M N3 And M N2 、M N4 Respectively form auxiliary buffers M P3 、M P4 And M P5 、M P6 Respectively forming a replication current amplifier; wherein M is N1 、M N2 、M N3 、M N4 Is NMOS transistor, M P1 、M P2 、M P3 、M P4 、M P5 、M P6 The low voltage input buffer circuit also comprises a replica capacitor C as a PMOS transistor c The method comprises the steps of carrying out a first treatment on the surface of the Wherein the connection relation of each element is as follows:
M N1 gate of (2) is connected to positive input terminal V IP ，M N1 Is connected with a power supply V DD ，M N1 Source electrode of (C) and M N3 Is connected with the drain electrode of M N3 The source electrode of the transistor is grounded; m is M N3 Gate and M of (2) N4 Is connected with the grid electrode of M N4 Is connected to the drain thereof and to M P3 A drain electrode of (2); m is M N4 The source electrode of the transistor is grounded; m is M P3 Gate of (2) is connected to positive input terminal V IP ，M P3 Source connection M of (2) P1 Drain electrode of M P1 Is connected with the bias voltage V B ，M P1 Is connected with a power supply V DD ；
M N2 Is connected with the negative input terminal V IN ，M N2 Is connected with a power supply V DD ，M N2 Source electrode of (C) and M N6 Is connected with the drain electrode of M N6 The source electrode of the transistor is grounded; m is M N6 Gate and M of (2) N5 Is connected with the grid electrode of M N5 Is connected to the drain thereof and to M P4 A drain electrode of (2); m is M N5 The source electrode of the transistor is grounded; m is M P4 Is connected with the negative input terminal V IN ，M P4 Source connection M of (2) P2 Drain electrode of M P2 Is connected with the bias voltage V B ，M P2 Is connected with a power supply V DD ；
Wherein M is N1 Source electrode of (C) and M N3 The connection point of the drain electrode of (2) is a positive output end V OUP ，M N2 Source electrode of (C) and M N6 The connection point of the drain electrode of (C) is a negative output terminal V OUN ；M P3 Source electrode of (C) and M P1 Is connected to the replica capacitor C c Is one end of M P4 Source electrode of (C) and M P2 Is connected to the replica capacitor C c And the other end of (2).
The invention adopts fully differential input signals, positive input end V IP And a negative input terminal V IN The input signals of the (C) are respectively applied to the respective load capacitors C through the main buffer L Generates a load current i P 、i N ：
i P ＝V IP C L s
i N ＝V IN C L s
Positive input terminal V IP And a negative input terminal V IN The input signal of (2) acts on the replica capacitor C through the auxiliary buffer C Two ends, generate the copy current i C ：
i C ＝(V IP -V IN )C C s
Replication current i C Flow through transistor M N4 And M N5 Through M N3 、M N4 And M N5 、M N6 The mirror amplifier is constructed to replicate the current i C Amplified N times and acts on the load capacitance C L When the capacitor C is duplicated C And load capacitance C L The following relationships are satisfied:
flow through main buffer load tube M N3 And M N6 Will be equal to the load current i P 、i N The amplitude values are the same and the phases are opposite, so that the current flowing through the input tube of the main buffer is not influenced by load current, and the linearity is improved.
Another implementation manner of the present invention is to perform dual replacement on PMOS and NMOS in the first embodiment, where the structure of the high linearity low voltage input buffer circuit provided by this embodiment is shown in fig. 5, where M P1 、M P3 Constitute the positive input terminal V IP Main buffer of M P2 、M P6 Form the negative input terminal V IN Main buffer of M N1 、M N3 And M N2 、M N4 Respectively form auxiliary buffers M P3 、M P4 And M P5 、M P6 Respectively forming a replication current amplifier; m is M N1 、M N2 、M N3 、M N4 Is NMOS transistor, M P1 、M P2 、M P3 、M P4 、M P5 、M P6 The low voltage input buffer circuit also comprises a replica capacitor C as a PMOS transistor c The method comprises the steps of carrying out a first treatment on the surface of the Wherein the connection relation of each element is as follows:
M P1 gate of (2) is connected to positive input terminal V IP ，M P1 Is grounded at the drain electrode of M P1 Source electrode of (C) and M P3 Is connected with the drain electrode of M P3 Is connected with a power supply V DD ；M P3 Gate and M of (2) P4 Is connected with the grid electrode of M P4 Is connected to the drain thereof and to M N3 A drain electrode of (2); m is M P4 Is connected with a power supply V DD ；M N3 Gate of (2) is connected to positive input terminal V IP ，M N3 Source connection M of (2) N1 Drain electrode of M N1 Is connected with the bias voltage V B ，M N1 The source electrode of the transistor is grounded;
M P2 is connected with the negative input terminal V IN ，M P2 Is grounded at the drain electrode of M P2 Source electrode of (C) and M P6 Is connected with the drain electrode of M P6 Is connected with a power supply V DD ；M P6 Gate and M of (2) P5 Is connected with the grid electrode of M P5 Is connected to the drain thereof and to M N4 A drain electrode of (2); m is M P5 Is connected with a power supply V DD ；M N4 Is connected with the negative input terminal V IN ，M N4 Source connection M of (2) N2 Drain electrode of M N2 Is connected with the bias voltage V B ，M N2 The source electrode of the transistor is grounded;
wherein M is P1 Source electrode of (C) and M P3 The connection point of the drain electrode of (2) is a positive output end V OUP ，M P2 Source electrode of (C) and M P6 Is connected to the drain of (C)Is a negative output terminal V OUN ；M N3 Source electrode of (C) and M N1 Is connected to the replica capacitor C c Is one end of M N4 Source electrode of (C) and M N2 Is connected to the replica capacitor C c And the other end of (2).
The working principle is the same as that of the first embodiment, and the positive input end V IP And a negative input terminal V IN The input signals of the (C) are respectively applied to the respective load capacitors C through the main buffer L Generates a load current i P 、i N And positive input terminal V IP And a negative input terminal V IN The input signal of (2) acts on the replica capacitor C through the auxiliary buffer C Two ends, generate the copy current i C Copy current i C Flow through transistor M P4 And M P5 Through M P3 、M P4 And M P5 、M P6 The mirror amplifier is constructed to replicate the current i C Amplified N times and acts on the load capacitance C L When the capacitor C is duplicated C And load capacitance C L The following relationships are satisfied:
flow through main buffer load tube M P3 And M P6 Will be equal to the load current i P 、i N The amplitude values are the same and the phases are opposite, so that the current flowing through the input tube of the main buffer is not influenced by load current, and the linearity is improved.
The present invention can also be realized by other embodiments, for example, the auxiliary buffer input pipe M in the first embodiment P3 \M P4 Can be replaced by NMOS tube, and the capacitor C is duplicated by trimming C The same object can be achieved. At this time, the auxiliary buffer is converted into an amplifier, and the capacitor C is duplicated C The object of the invention can also be achieved by scaling down the amplification factor of the amplifier according to the same proportion.
The above embodiments are only preferred embodiments of the present invention, and are not intended to limit the present invention, but any modifications, equivalents, improvements, etc. within the principle of the idea of the present invention should be included in the scope of protection of the present invention.
Claims (8)
1. High-linearity low-voltage input buffer circuit with positive input end V IP And a negative input terminal V IN Using differential inputs, characterised by M N1 、M N3 Constitute the positive input terminal V IP Main buffer of M N2 、M N6 Form the negative input terminal V IN Main buffer of M P1 、M P3 And M P2 、M P4 Respectively form auxiliary buffers M N3 、M N4 And M N5 、M N6 Respectively forming a replication current amplifier; wherein M is N1 、M N2 、M N3 、M N4 、M N5 、M N6 Is NMOS transistor, M P1 、M P2 、M P3 、M P4 The low voltage input buffer circuit also comprises a replica capacitor C as a PMOS transistor c ；
M N1 Gate of (2) is connected to positive input terminal V IP ，M N1 Is connected with a power supply V DD ，M N1 Source electrode of (C) and M N3 Is connected with the drain electrode of M N3 The source electrode of the transistor is grounded; m is M N3 Gate and M of (2) N4 Is connected with the grid electrode of M N4 Is connected to the drain thereof and to M P3 A drain electrode of (2); m is M N4 The source electrode of the transistor is grounded; m is M P3 Gate of (2) is connected to positive input terminal V IP ，M P3 Source connection M of (2) P1 Drain electrode of M P1 Is connected with the bias voltage V B ，M P1 Is connected with a power supply V DD ；
M N2 Is connected with the negative input terminal V IN ，M N2 Is connected with a power supply V DD ，M N2 Source electrode of (C) and M N6 Is connected with the drain electrode of M N6 The source electrode of the transistor is grounded; m is M N6 Gate and M of (2) N5 Is connected with the grid electrode of M N5 Is connected to the drain thereof and to M P4 A drain electrode of (2); m is M N5 The source electrode of the transistor is grounded; m is M P4 Is connected with the negative input terminal V IN ，M P4 Source connection M of (2) P2 Drain electrode of M P2 Is connected with the bias voltage V B ，M P2 Is connected with a power supply V DD ；
Wherein M is N1 Source electrode of (C) and M N3 The connection point of the drain electrode of (2) is a positive output end V OUP ，M N2 Source electrode of (C) and M N6 The connection point of the drain electrode of (C) is a negative output terminal V OUN ；M P3 Source electrode of (C) and M P1 Is connected to the replica capacitor C c Is one end of M P4 Source electrode of (C) and M P2 Is connected to the replica capacitor C c And the other end of (2).
2. The low voltage input buffer circuit of claim 1, wherein the positive output terminal V OUP And a negative output terminal V OUN Respectively connected with the respective load capacitors C L 。
3. The low voltage input buffer circuit of claim 2, wherein M N3 、M N4 And M N5 、M N6 The amplification factor of the separately configured replica current amplifier is N.
4. A low voltage input buffer circuit as claimed in claim 3, characterized in that the replica capacitor C c Is the size of the load capacitance C L 1/(2N) times.
5. High-linearity low-voltage input buffer circuit with positive input end V IP And a negative input terminal V IN Using differential inputs, characterised by M P1 、M P3 Constitute the positive input terminal V IP Main buffer of M P2 、M P6 Form the negative input terminal V IN Main buffer of M N1 、M N3 And M N2 、M N4 Respectively form auxiliary buffers M P3 、M P4 And M P5 、M P6 Respectively forming a replication current amplifier; wherein M is N1 、M N2 、M N3 、M N4 Is NMOS crystalBody tube, M P1 、M P2 、M P3 、M P4 、M P5 、M P6 The low voltage input buffer circuit also comprises a replica capacitor C as a PMOS transistor c ；
M P1 Gate of (2) is connected to positive input terminal V IP ，M P1 Is grounded at the drain electrode of M P1 Source electrode of (C) and M P3 Is connected with the drain electrode of M P3 Is connected with a power supply V DD ；M P3 Gate and M of (2) P4 Is connected with the grid electrode of M P4 Is connected to the drain thereof and to M N3 A drain electrode of (2); m is M P4 Is connected with a power supply V DD ；M N3 Gate of (2) is connected to positive input terminal V IP ，M N3 Source connection M of (2) N1 Drain electrode of M N1 Is connected with the bias voltage V B ，M N1 The source electrode of the transistor is grounded;
M P2 is connected with the negative input terminal V IN ，M P2 Is grounded at the drain electrode of M P2 Source electrode of (C) and M P6 Is connected with the drain electrode of M P6 Is connected with a power supply V DD ；M P6 Gate and M of (2) P5 Is connected with the grid electrode of M P5 Is connected to the drain thereof and to M N4 A drain electrode of (2); m is M P5 Is connected with a power supply V DD ；M N4 Is connected with the negative input terminal V IN ，M N4 Source connection M of (2) N2 Drain electrode of M N2 Is connected with the bias voltage V B ，M N2 The source electrode of the transistor is grounded;
wherein M is P1 Source electrode of (C) and M P3 The connection point of the drain electrode of (2) is a positive output end V OUP ，M P2 Source electrode of (C) and M P6 The connection point of the drain electrode of (C) is a negative output terminal V OUN ；M N3 Source electrode of (C) and M N1 Is connected to the replica capacitor C c Is one end of M N4 Source electrode of (C) and M N2 Is connected to the replica capacitor C c And the other end of (2).
6. The low voltage input buffer circuit of claim 5, wherein the positive output terminal V OUP And a negative output terminal V OUN Respectively connected with the respective load capacitors C L 。
7. The low voltage input buffer circuit of claim 6, wherein M P3 、M P4 And M P5 、M P6 The amplification factor of the separately configured replica current amplifier is N.
8. The low voltage input buffer circuit of claim 7, wherein the replica capacitor C c Is the size of the load capacitance C L 1/(2N) times.
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| CN103888127A (en) * | 2014-03-28 | 2014-06-25 | 中国电子科技集团公司第二十四研究所 | Input buffer for improving linearity |
| US9209747B1 (en) * | 2015-02-05 | 2015-12-08 | Freescale Semiconductor, Inc. | Crystal oscillator with resistorless feedback biasing |
| CN105680833A (en) * | 2016-01-14 | 2016-06-15 | 厦门新页微电子技术有限公司 | Constant transconductance rail-to-rail voltage comparator |
| CN207070017U (en) * | 2017-04-18 | 2018-03-02 | 西安欣创电子技术有限公司 | Broadband is without inductance high linearity output driving buffer |
| CN108390655A (en) * | 2018-04-03 | 2018-08-10 | 南京德睿智芯电子科技有限公司 | A kind of BUFFER common-mode voltages stabilizing circuit |
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| CN111756375A (en) | 2020-10-09 |
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