CN110798203A - High-linearity unit-gain voltage buffer under nano-scale CMOS (complementary metal oxide semiconductor) process - Google Patents
High-linearity unit-gain voltage buffer under nano-scale CMOS (complementary metal oxide semiconductor) process Download PDFInfo
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- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 5
- 150000004706 metal oxides Chemical class 0.000 title abstract description 5
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- 239000003990 capacitor Substances 0.000 claims description 9
- 238000013459 approach Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
Abstract
The invention discloses a high-linearity unit gain voltage buffer under a nano-scale CMOS (complementary metal oxide semiconductor) process, which comprises an operational transconductance amplifier and a source follower, wherein the operational transconductance amplifier is connected with the source follower; when the input voltage is the lower limit, the eighth NMOS transistor N8 can fully operate in the saturation region, thereby ensuring sufficient loop gain; when the input voltage approaches to the power supply voltage, the seventh PMOS transistor P7 enters a linear region, the gate voltage of the seventh PMOS transistor P7 drops sharply, but as long as the voltage does not drop to force the ninth NMOS transistor N9 to enter the linear region, the source voltage of the sixth PMOS transistor P6 (i.e., the output voltage of the invention) can normally follow the change of the gate voltage (i.e., the output voltage of the OTA), and thus, sufficient loop gain can be ensured; the invention has the advantages that higher and constant loop gain can be maintained in a wider input voltage range, and lower voltage buffer error and nonlinear distortion are ensured.
Description
Technical Field
The invention belongs to the field of analog integrated circuit design, and particularly relates to a high-linearity unit gain voltage buffer under a nano-scale CMOS (complementary metal oxide semiconductor) process.
Background
A commonly used unity gain voltage buffer is shown in fig. 1, in which the non-inverting input terminal of an Operational Transconductance Amplifier (OTA) is used as the voltage input terminal, and the inverting terminal of the OTA is connected to the output terminal to be used as the voltage output terminal. Since the voltage gain (a) of the OTA is very high, the output voltage versus input voltage is:
the relative error of the buffered output is equal to 1/(1+ a), so the higher the gain of the OTA, the smaller the error of the unity-gain voltage buffer, i.e. the better the effect of the output voltage following the input voltage.
From the port impedance point of view, the input impedance of the unity gain voltage buffer shown in fig. 1 is equal to that of OTA, which is very high in CMOS process; its output impedance is equal to the OTA itself output impedance divided by (1+ a), a very low value. Therefore, the performance of such unity-gain voltage buffers depends on the level of the voltage gain (a) of the OTA.
As shown in fig. 2, the quadratic coefficient and the cubic coefficient after introducing negative feedback are:
in a unity gain voltage buffer, a1And f is 1, and the loop gain is the voltage gain (A) of the OTA. Thus, the higher a, the smaller the nonlinear distortion of the unity gain voltage buffer.
The SoC trend in the prior art necessitates the implementation of analog circuits in a nano-scale CMOS process, which has a supply voltage of only 1.2V, or even lower, which makes the normal operation of the unity gain voltage buffer difficult. For the unity-gain voltage buffer shown in fig. 1, if the input stage of the OTA employs the PMOS differential pair, the input common-mode voltage must be set to a level close to the ground, and at this time, the NMOS transistor of the output stage approaches the linear region when the voltage swing is large, which causes the loop gain to decrease, and thus, both the gain error and the nonlinear distortion will deteriorate. On the contrary, if the input stage of the OTA adopts the NMOS differential pair, the input common mode voltage needs to be set to a level close to the power supply, and at this time, the PMOS transistor of the output stage approaches a linear region when the voltage swing is large, resulting in a decrease in the loop gain, and thus, both the gain error and the nonlinear distortion are also deteriorated.
Disclosure of Invention
The invention aims to provide a high-linearity unit-gain voltage buffer under a nano-scale CMOS (complementary metal oxide semiconductor) process, which can maintain higher and constant loop gain in a wider input voltage range and ensure lower voltage buffer error and nonlinear distortion.
The technical scheme of the invention is as follows: a high-linearity unit gain voltage buffer under a nano-scale CMOS process comprises an operational transconductance amplifier and a source follower;
the operational transconductance amplifier adopts a folding cascode input operational transconductance amplifier and comprises a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a resistor R, a capacitor C and a voltage source VDD; the source follower comprises a ninth NMOS transistor N9, a tenth NMOS transistor N10, a sixth PMOS transistor P6, a seventh PMOS transistor P7 and an eighth PMOS transistor P8;
meanwhile, the gate of the first NMOS transistor N1 is connected to a voltage input terminal, the source of the first NMOS transistor N1 is connected to the source of the second NMOS transistor N2 and the drain of the third NMOS transistor N3, respectively, and the drain of the first NMOS transistor N1 is connected to the source of the second PMOS transistor P2 and the drain of the fourth PMOS transistor P4, respectively; the drain electrode of the second NMOS transistor N2 is connected to the source electrode of the first PMOS transistor P1 and the drain electrode of the third PMOS transistor P3; the source electrode of the fourth NMOS transistor N4 is connected to the drain electrode of a sixth NMOS transistor N6, and the drain electrode of the fourth NMOS transistor N4 is respectively connected to the gate electrode of the sixth NMOS transistor N6, the gate electrode of the seventh NMOS transistor N7 and the drain electrode of the first PMOS transistor P1; the source electrode of the fifth NMOS transistor N5 is connected to the drain electrode of a seventh NMOS transistor N7, the drain electrode of the fifth NMOS transistor N5 is respectively connected to the gate electrode of an eighth NMOS transistor N8, the drain electrode of a second PMOS transistor P2 and one end of a resistor R, the other end of the resistor R is connected with one end of a capacitor C, and the other end of the capacitor C is connected with the drain electrode of the eighth NMOS transistor N8, the drain electrode of a fifth PMOS transistor P5 and the gate electrode of a sixth PMOS transistor P6; a source electrode of the ninth NMOS transistor N9 is respectively connected to a drain electrode of the tenth NMOS transistor N10 and a drain electrode of the sixth PMOS transistor P6, and a drain electrode of the ninth NMOS transistor N9 is respectively connected to a gate electrode of the seventh PMOS transistor P7 and a drain electrode of the eighth PMOS transistor P8;
a gate of the third PMOS transistor P3, a gate of the fourth PMOS transistor P4, a gate of the fifth PMOS transistor P5, and a gate of the eighth PMOS transistor P8 are connected to a first bias voltage Vbias1, a gate of the first PMOS transistor P1 and a gate of the second PMOS transistor P2 are connected to a second bias voltage Vbias2, a gate of the fourth NMOS transistor N4, a gate of the fifth NMOS transistor N5, and a gate of the ninth NMOS transistor N9 are connected to a third bias voltage Vbias3, and a gate of the third NMOS transistor N3 and a gate of the tenth NMOS transistor N10 are connected to a fourth bias voltage Vbias 4; the grid electrode of the second NMOS transistor N2, the source electrode of the sixth PMOS transistor P6 and the drain electrode of the seventh PMOS transistor P7 are connected to a voltage output end.
Preferably, the source of the third PMOS transistor P3, the source of the fourth PMOS transistor P4, the source of the fifth PMOS transistor P5, the source of the seventh PMOS transistor P7, and the source of the eighth PMOS transistor P8 are all connected to a voltage source VDD.
Preferably, the source of the third NMOS transistor N3, the source of the sixth NMOS transistor N6, the source of the seventh NMOS transistor N7, the source of the eighth NMOS transistor N8, and the source of the tenth NMOS transistor N10 are all grounded.
The invention has the advantages that:
1. the high-linearity unit-gain voltage buffer under the nano-scale CMOS process can maintain higher and constant loop gain within a wider input voltage range, and lower voltage buffer error and nonlinear distortion are guaranteed;
2. according to the high-linearity unit gain voltage buffer under the nano-scale CMOS process, the load is only the parasitic capacitance of the input end (namely the P6 grid) of the source follower, so that the frequency compensation of the operational transconductance amplifier is easier to realize.
Drawings
The invention is further described with reference to the following figures and examples:
FIG. 1 is a diagram of a conventional circuit structure of a unity-gain voltage buffer implemented by OTA in the prior art;
FIG. 2 is a schematic diagram of the principle of suppressing non-linearity by negative feedback technique;
FIG. 3 is a schematic diagram of a high linearity unity gain voltage buffer under a nano-scale CMOS process according to the present invention;
FIG. 4 is a graph of a simulated curve of the relationship between loop gain and input common mode voltage at 1kHz (dashed line in the figure) in accordance with the present invention, compared to a simulated curve of a conventional structure in the same process (solid line in the figure);
FIG. 5 is a comparison graph of simulated curves of voltage gain versus input common mode voltage at 100kHz for the present invention and a conventional structure;
FIG. 6 is a graph comparing simulated Total Harmonic Distortion (THD) versus input power for a 100kHz sinusoidal voltage signal buffered using the present invention and a conventional configuration.
Detailed Description
Example (b): referring to fig. 3, a high linearity unity gain voltage buffer under a nano-scale CMOS process includes an operational transconductance amplifier and a source follower; the operational transconductance amplifier adopts a folding cascode input operational transconductance amplifier and comprises a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a resistor R, a capacitor C and a voltage source VDD; the source follower comprises a ninth NMOS transistor N9, a tenth NMOS transistor N10, a sixth PMOS transistor P6, a seventh PMOS transistor P7 and an eighth PMOS transistor P8.
Meanwhile, the gate of the first NMOS transistor N1 is connected to a voltage input terminal, the source of the first NMOS transistor N1 is connected to the source of the second NMOS transistor N2 and the drain of the third NMOS transistor N3, respectively, and the drain of the first NMOS transistor N1 is connected to the source of the second PMOS transistor P2 and the drain of the fourth PMOS transistor P4, respectively; the drain electrode of the second NMOS transistor N2 is connected to the source electrode of the first PMOS transistor P1 and the drain electrode of the third PMOS transistor P3; the source electrode of the fourth NMOS transistor N4 is connected to the drain electrode of a sixth NMOS transistor N6, and the drain electrode of the fourth NMOS transistor N4 is respectively connected to the gate electrode of the sixth NMOS transistor N6, the gate electrode of the seventh NMOS transistor N7 and the drain electrode of the first PMOS transistor P1; the source electrode of the fifth NMOS transistor N5 is connected to the drain electrode of a seventh NMOS transistor N7, the drain electrode of the fifth NMOS transistor N5 is respectively connected to the gate electrode of an eighth NMOS transistor N8, the drain electrode of a second PMOS transistor P2 and one end of a resistor R, the other end of the resistor R is connected with one end of a capacitor C, and the other end of the capacitor C is connected with the drain electrode of the eighth NMOS transistor N8, the drain electrode of a fifth PMOS transistor P5 and the gate electrode of a sixth PMOS transistor P6; a source electrode of the ninth NMOS transistor N9 is respectively connected to a drain electrode of the tenth NMOS transistor N10 and a drain electrode of the sixth PMOS transistor P6, and a drain electrode of the ninth NMOS transistor N9 is respectively connected to a gate electrode of the seventh PMOS transistor P7 and a drain electrode of the eighth PMOS transistor P8; a gate of the third PMOS transistor P3, a gate of the fourth PMOS transistor P4, a gate of the fifth PMOS transistor P5, and a gate of the eighth PMOS transistor P8 are connected to a first bias voltage Vbias1, a gate of the first PMOS transistor P1 and a gate of the second PMOS transistor P2 are connected to a second bias voltage Vbias2, a gate of the fourth NMOS transistor N4, a gate of the fifth NMOS transistor N5, and a gate of the ninth NMOS transistor N9 are connected to a third bias voltage Vbias3, and a gate of the third NMOS transistor N3 and a gate of the tenth NMOS transistor N10 are connected to a fourth bias voltage Vbias 4; the grid electrode of the second NMOS transistor N2, the source electrode of the sixth PMOS transistor P6 and the drain electrode of the seventh PMOS transistor P7 are connected to a voltage output end.
Wherein the source of the third PMOS transistor P3, the source of the fourth PMOS transistor P4, the source of the fifth PMOS transistor P5, the source of the seventh PMOS transistor P7, and the source of the eighth PMOS transistor P8 are all connected to a voltage source VDD.
Wherein the source of the third NMOS transistor N3, the source of the sixth NMOS transistor N6, the source of the seventh NMOS transistor N7, the source of the eighth NMOS transistor N8, and the source of the tenth NMOS transistor N10 are all grounded.
The width-to-length ratio of the sixth PMOS pipe P6 takes a larger value, and the substrate of the sixth PMOS pipe P6 is connected with the source electrode thereof so as to reduce the threshold voltage as much as possible; the width-length ratio of the seventh PMOS tube P7 is as large as possible, and the channel length of the seventh PMOS tube P7 is small.
This embodiment is built at 40nm CMOS process and 1.2V voltage, since the inputs are NMOS differential pairs and the common mode level is chosen to be 0.95V to ensure: when the input voltage amplitude reaches 0.25V (the upper limit of the input voltage is the power supply voltage), the lower limit of the input voltage (0.7V) does not force the third NMOS transistor N3 into the linear region. The sixth PMOS transistor P6 has a larger width-to-length ratio to operate in the sub-threshold region, so that VGSP6 is equal to about 0.4V, and the quiescent voltage of the output terminal of the OTA (i.e., the gate of the sixth PMOS transistor P6, the drain of the fifth PMOS transistor P5, and the drain of the eighth NMOS transistor N8) is equal to about 0.55V.
The working principle of the invention is as follows: when the input voltage is the lower limit, the VDS of the eighth NMOS transistor N8 is about 0.3V, and the eighth NMOS transistor N8 can fully operate in the saturation region, thereby ensuring sufficient loop gain; when the input voltage approaches to the power supply voltage, the seventh PMOS transistor P7 enters a linear region, the gate voltage of the seventh PMOS transistor P7 drops sharply, but as long as the voltage does not drop to force the ninth NMOS transistor N9 to enter the linear region, the source voltage of the sixth PMOS transistor P6 (i.e., the output voltage of the present invention) can normally follow the change of the gate voltage (i.e., the output voltage of the OTA), and thus, sufficient loop gain can be ensured. The drain bias voltage of the tenth NMOS transistor N10 can be made equal to the drain-source saturation voltage drop (Vdsat) by the bias circuit, and then the source follower can normally operate as long as the gate voltage of the seventh PMOS transistor P7 is not lowered to less than 2Vdsat, so that sufficient loop gain can be ensured, and thus a low gain error and nonlinear distortion can be obtained.
The invention and a unit gain voltage buffer (the structure shown in figure 1) with a traditional structure based on an Operational Transconductance Amplifier (OTA) are both provided with a circuit under the condition of 40nm CMOS process and 1.2V power voltage and are simulated. As can be seen from fig. 4, the present invention is able to maintain a high and relatively constant loop gain over a wide input voltage range, which means adequate suppression of voltage buffer errors and non-linearities. As can be seen from fig. 5, the present invention can maintain a flat voltage gain over a wider range, and the buffering error (i.e., the difference between the gain and 0 dB) is more constant. As can be seen from fig. 6, the THD of the present invention is about 2 orders of magnitude lower than the conventional structure.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (3)
1. A high linearity unit gain voltage buffer under a nano CMOS process is characterized by comprising an operational transconductance amplifier and a source follower;
the operational transconductance amplifier adopts a folding cascode input operational transconductance amplifier and comprises a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a resistor R, a capacitor C and a voltage source VDD; the source follower comprises a ninth NMOS transistor N9, a tenth NMOS transistor N10, a sixth PMOS transistor P6, a seventh PMOS transistor P7 and an eighth PMOS transistor P8;
meanwhile, the gate of the first NMOS transistor N1 is connected to a voltage input terminal, the source of the first NMOS transistor N1 is connected to the source of the second NMOS transistor N2 and the drain of the third NMOS transistor N3, respectively, and the drain of the first NMOS transistor N1 is connected to the source of the second PMOS transistor P2 and the drain of the fourth PMOS transistor P4, respectively; the drain electrode of the second NMOS transistor N2 is connected to the source electrode of the first PMOS transistor P1 and the drain electrode of the third PMOS transistor P3; the source electrode of the fourth NMOS transistor N4 is connected to the drain electrode of a sixth NMOS transistor N6, and the drain electrode of the fourth NMOS transistor N4 is respectively connected to the gate electrode of the sixth NMOS transistor N6, the gate electrode of the seventh NMOS transistor N7 and the drain electrode of the first PMOS transistor P1; the source electrode of the fifth NMOS transistor N5 is connected to the drain electrode of a seventh NMOS transistor N7, the drain electrode of the fifth NMOS transistor N5 is respectively connected to the gate electrode of an eighth NMOS transistor N8, the drain electrode of a second PMOS transistor P2 and one end of a resistor R, the other end of the resistor R is connected with one end of a capacitor C, and the other end of the capacitor C is connected with the drain electrode of the eighth NMOS transistor N8, the drain electrode of a fifth PMOS transistor P5 and the gate electrode of a sixth PMOS transistor P6; a source electrode of the ninth NMOS transistor N9 is respectively connected to a drain electrode of the tenth NMOS transistor N10 and a drain electrode of the sixth PMOS transistor P6, and a drain electrode of the ninth NMOS transistor N9 is respectively connected to a gate electrode of the seventh PMOS transistor P7 and a drain electrode of the eighth PMOS transistor P8;
a gate of the third PMOS transistor P3, a gate of the fourth PMOS transistor P4, a gate of the fifth PMOS transistor P5, and a gate of the eighth PMOS transistor P8 are connected to a first bias voltage Vbias1, a gate of the first PMOS transistor P1 and a gate of the second PMOS transistor P2 are connected to a second bias voltage Vbias2, a gate of the fourth NMOS transistor N4, a gate of the fifth NMOS transistor N5, and a gate of the ninth NMOS transistor N9 are connected to a third bias voltage Vbias3, and a gate of the third NMOS transistor N3 and a gate of the tenth NMOS transistor N10 are connected to a fourth bias voltage Vbias 4; the grid electrode of the second NMOS transistor N2, the source electrode of the sixth PMOS transistor P6 and the drain electrode of the seventh PMOS transistor P7 are connected to a voltage output end.
2. The buffer of claim 1, wherein the source of the third PMOS transistor P3, the source of the fourth PMOS transistor P4, the source of the fifth PMOS transistor P5, the source of the seventh PMOS transistor P7, and the source of the eighth PMOS transistor P8 are all connected to a voltage source VDD.
3. The buffer of claim 1, wherein the source of the third NMOS transistor N3, the source of the sixth NMOS transistor N6, the source of the seventh NMOS transistor N7, the source of the eighth NMOS transistor N8, and the source of the tenth NMOS transistor N10 are all grounded.
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| CN112511110A (en) * | 2021-01-14 | 2021-03-16 | 苏州大学 | High-linearity programmable gain amplifier |
| CN112506259A (en) * | 2020-11-12 | 2021-03-16 | 苏州大学 | CMOS reference voltage buffer with low output resistance |
| CN116317996A (en) * | 2023-05-23 | 2023-06-23 | 盈力半导体(上海)有限公司 | Error amplifier and power supply conversion device |
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| CN210724750U (en) * | 2019-12-02 | 2020-06-09 | 苏州大学 | High-linearity unit-gain voltage buffer under nano-scale CMOS (complementary metal oxide semiconductor) process |
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| CN112506259A (en) * | 2020-11-12 | 2021-03-16 | 苏州大学 | CMOS reference voltage buffer with low output resistance |
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