CN103825557A - Transconductance amplifier with low power consumption and high linearity - Google Patents

Abstract

The invention relates to the technical field of simulative integrated operational amplifiers, in particular to a Push-Pull transconductance amplifier with low power consumption and high linearity. The transconductance amplifier comprises a biasing circuit, a Rail-to-Rail input stage and a Push-Pull output stage which are connected in sequence, wherein the biasing circuit is formed by an image current telescope and is used for providing bias voltage for the Rail-to-Rail input stage and the Push-Pull output stage; the Rail-to-Rail input stage adopts a folding NMOS (N-Channel Metal Oxide Semiconductor) differential pair and a PMOS (P-Channel Metal Oxide Semiconductor) differential pair to realize rail-to-rail in a common-mode input range, and adopts negative feedback of a source electrode to realize linear transconductance; the Push-Pull output stage adopts bias with low power consumption to realize push-pull output with low power consumption, and adopts image current amplification to improve the output driving capacity. The transconductance amplifier has the advantages of simple structure, high linearity, low power consumption, high power supply rejection ratio, small chip area and the like, and is particularly suitable for the transconductance amplifier.

Description

A kind of low-power consumption high linearity trsanscondutance amplifier

Technical field

The present invention relates to Analog Integrated Operation amplifier technical field, be specifically related to a kind of low-power consumption high linearity Push-Pull trsanscondutance amplifier.

Background technology

Operation transconductance amplifier (OTA), as one of basis important in analog circuitry system and key modules, is widely used in the systems such as power supply, power amplification, signal processing, and the performance level of amplifier has directly determined the quality of whole system performance.Due to different application occasion to operation transconductance amplifier index parameter require different, the many requirements to its performance index based on application system of the design of operation transconductance amplifier.

In field of switch power, as the error amplifier of voltage control loop core, its index request is just different under different system topological structure, different feedback signal type.The error amplifier that will use low-power consumption high linearity under some system topology and feedback signal type forms voltage control loop, for example in practical application in the time that feedback signal type is AC signal, error amplifier just need to be accepted wide region input, and the nonlinear problem that wide input range is introduced also needs designer to consider; When the output of error amplifier drives PWM(Pulse Width Modulation) controller is while requiring large adjustable range, and error amplifier just needs large output voltage swing; In the time that chip is comparatively strict to the requirement of power consumption, the design of error amplifier will reduce power consumption as much as possible.Just based on this kind of application demand, design the low-power consumption high linearity trsanscondutance amplifier that can make error amplifier and there is good realistic meaning.

The OTA linearity that tradition source electrode coupled difference structure for amplifying is realized is limited to tail current I _sSand β (

), improve linear input range if want and just must increase tail current I _sSor reduce β; Contradiction be increase I _sScan increase power consumption, reduce β and can reduce common-mode input range, thereby traditional amplifier does not also possess and has high linearity, low-power consumption and wide input range simultaneously.

Summary of the invention

To be solved by this invention, it is exactly the problem existing for above-mentioned traditional amplifier, in order to realize the requirement of supply voltage switch control loop to error amplifier low-power consumption and high linearity, a kind of low-power consumption high linearity Push-Pull trsanscondutance amplifier of making error amplifier has been proposed simultaneously.

The present invention solves the problems of the technologies described above adopted technical scheme: a kind of low-power consumption high linearity trsanscondutance amplifier, it is characterized in that, and comprise the biasing circuit, Rail-to-Rail input stage and the Push-Pull output stage that connect successively; Described biasing circuit is made up of image current mirror pipe, for Rail-to-Rail input stage and Push-Pull output stage provide bias voltage; Described Rail-to-Rail input stage adopts collapsible nmos differential to realizing common-mode input range rail-to-rail with PMOS differential pair, and adopts source negative feedback to realize linearisation mutual conductance; Described Push-Pull output stage adopts low-power consumption biasing to realize low-power consumption and recommends output, and adopts image current to amplify raising output driving force.

Concrete, described biasing circuit comprises a PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, a NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3 and current source;

Described Rail-to-Rail input stage comprises the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the 7th PMOS pipe MP7, the 8th PMOS pipe MP8, the 9th PMOS pipe MP9, the tenth PMOS pipe MP10, the 11 PMOS pipe MP11, the 12 PMOS pipe MP12, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 6th NMOS pipe MN6, the 7th NMOS pipe MN7, the 8th NMOS pipe MN8, the 9th NMOS pipe MN9, the tenth NMOS pipe MN10, the 11 NMOS pipe MN11, the first resistance R SN and the second resistance R SP,

Described Push-Pull output stage comprises the 13 PMOS pipe MP13, the 14 PMOS pipe MP14, the 15 PMOS pipe MP15, the 16 PMOS pipe MP16, the 17 PMOS pipe MP17, the 18 PMOS pipe MP18, the 12 NMOS pipe MN12, the 13 NMOS pipe MN13, the 14 NMOS pipe MN14, the 15 NMOS pipe MN15, the 16 NMOS pipe MN16, the 17 NMOS pipe MN17, the 3rd resistance R BP and the 4th resistance R BN; Wherein,

The lining termination power voltage of the source lining end of the one PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the 9th PMOS pipe MP9, the tenth PMOS pipe MP10, the 15 PMOS pipe MP15, the 16 PMOS pipe MP16 and the 11 PMOS pipe MP11, the 12 PMOS pipe MP12, the 17 PMOS pipe MP17, the 18 PMOS pipe MP18;

The grid end of the grid leak end of the one PMOS pipe MP1, the grid end of the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the grid end of the 5th PMOS pipe MP5, the grid end of the 6th PMOS pipe MP6 all connect current source forward end, current source negative end earthing potential;

The grid end of the grid end of the grid leak end of the one NMOS pipe MN1, the grid end of the tenth NMOS pipe MN10, the 11 NMOS pipe MN11, the grid end of the 16 NMOS pipe MN16, the 17 NMOS pipe MN17 is all connected with the drain terminal of the 2nd PMOS pipe MP2;

The grid end of the grid end of the grid leak end of the 2nd NMOS pipe MN2, the grid end of the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the grid of the 5th NMOS pipe MN5, the 8th NMOS pipe MN8, the grid end of the 9th NMOS pipe MN9 are all connected with the drain terminal of the 3rd PMOS pipe MP3;

The grid end of the grid end of the grid leak end of the 4th PMOS pipe MP4, the grid end of the 11 PMOS pipe MP11, the 12 PMOS pipe MP12, the grid end of the 17 PMOS pipe MP17, the 18 PMOS pipe MP18 is all connected with the drain terminal of the 3rd NMOS pipe MN3;

The grid end of the 6th NMOS pipe MN6 is connected as an input with the grid end of the 7th PMOS pipe MP7, the grid end of the 7th NMOS pipe MN7 is connected as another input with the grid end of the 8th PMOS pipe MP8, and the source lining end of the 6th NMOS pipe MN6, the source lining end of the 7th NMOS pipe MN7 are connected and pass through the first resistance R SN cross-over connection with the drain terminal of the 4th NMOS pipe MN4, the drain terminal of the 5th NMOS pipe MN5 respectively;

The source lining end of the 7th PMOS pipe MP7, the source lining end of the 8th PMOS pipe MP8 are connected and pass through the second resistance R SP cross-over connection with the drain terminal of the 5th PMOS pipe MP5, the drain terminal of the 6th PMOS pipe MP6 respectively;

The drain terminal of the 9th PMOS pipe MP9, the source of the 11 PMOS pipe MP11 are connected with the drain terminal of the 7th NMOS pipe MN7; The drain terminal of the tenth PMOS pipe MP10, the source of the 12 PMOS pipe MP12 are connected with the drain terminal of the 6th NMOS pipe MN6;

The drain terminal of the 8th NMOS pipe MN8, the source of the tenth NMOS pipe MN10 are connected with the drain terminal of the 8th PMOS pipe MP8; The drain terminal of the 9th NMOS pipe MN9, the source of the 11 NMOS pipe MN11 are connected with the drain terminal of the 7th PMOS pipe MP7;

The drain terminal of the grid end of the 9th PMOS pipe MP9, the grid end of the tenth PMOS pipe MP10, the 11 PMOS pipe MP11 is all connected with the drain terminal of the tenth NMOS pipe MN10; The source of the drain terminal of the 12 PMOS pipe MP12, the source lining end of the 14 PMOS pipe MP14, the 13 NMOS pipe MN13 is all connected with the drain terminal of the 11 NMOS pipe MN11;

The 12 NMOS pipe MN12 drain-gate end, the 13 NMOS pipe MN13 grid termination the 3rd resistance R BP are to power supply; The 13 PMOS pipe MP13 drain-gate end, the 14 PMOS pipe MP14 grid termination the 4th resistance R BN are to earth potential, and the source of the 12 NMOS pipe MN12 connects the source lining end of the 13 PMOS pipe MP13;

The drain terminal of the grid end of the 15 PMOS pipe MP15, the grid end of the 16 PMOS pipe MP16, the 17 PMOS pipe MP17 is all connected with the drain terminal of the 13 NMOS pipe MN13; The drain terminal of the grid end of the 14 NMOS pipe MN14, the grid end of the 15 NMOS pipe MN15, the 16 NMOS pipe MN16 is all connected with the drain terminal of the 14 PMOS pipe MP14;

The drain terminal of the 15 PMOS pipe MP15, the drain terminal of the 16 PMOS pipe MP16 are connected with the source of the 17 PMOS pipe MP17, the source of the 18 PMOS pipe MP18 respectively;

The drain terminal of the 14 NMOS pipe MN14, the drain terminal of the 15 NMOS pipe MN15 are connected with the source of the 16 NMOS pipe MN16, the source of the 17 NMOS pipe MN17 respectively; The drain terminal of the 17 NMOS pipe MN17 is connected as output with the drain terminal of the 18 PMOS pipe MP18;

The lining of the source lining end of the one NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 8th NMOS pipe MN8, the 9th NMOS pipe MN9, the 14 NMOS pipe MN14, the 15 NMOS pipe MN15 and the tenth NMOS pipe MN10, the 11 NMOS pipe MN11, the 12 NMOS pipe MN12, the 13 NMOS pipe MN13, the 16 NMOS pipe MN16, the 17 NMOS pipe MN17 is held equal earthing potential.

Beneficial effect of the present invention is, has the advantages such as simple in structure, high linearity, low-power consumption, high PSRR, chip area be little.Compared with prior art, described low-power consumption high linearity Push-Pull trsanscondutance amplifier has overcome for improving the linearity increases the problems such as complex structure, power consumption that additional circuit causes are large, chip area is large, meet supply voltage switch control loop to the application conditions of error amplifier requirement under, realized the compact circuit design of high linearity low-power consumption.

Accompanying drawing explanation

Fig. 1 is the source resistance cross connection type negative feedback structure schematic diagram of linearisation mutual conductance;

Fig. 2 is the source resistance separate type negative feedback structure schematic diagram of linearisation mutual conductance;

Fig. 3 is low-power consumption high linearity trsanscondutance amplifier integrated circuit structural representation of the present invention.

Embodiment

Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:

Low-power consumption high linearity trsanscondutance amplifier of the present invention, comprise Rail-to-Rail input stage, Push-Pull push-pull output stage and biasing circuit, wherein low-power consumption high linearity Push-Pull trsanscondutance amplifier adopts source resistance cross connection type negative feedback structure (Fig. 1) to realize high linear transconductance, source pressure drop can not raise compared with source resistance separate type negative feedback structure (Fig. 2), has guaranteed the coefficient common mode electrical level wide ranges of two differential pair tubes; It is large that the high linearity of low-power consumption simultaneously Push-Pull trsanscondutance amplifier adopts current delivery amplification push-pull output stage to make to export driving force, can drive PWM controller to realize large duty cycle adjustment scope; Low-power consumption high linearity Push-Pull trsanscondutance amplifier output stage adopts low-power consumption biasing can reduce circuit power consumption, emulation show 25 ℃ in typical case power consumption only have 708uw; Low-power consumption high linearity Push-Pull transconductance amplifier circuit is simple in structure, and domain compact design adopts BCD350 technique chip area to only have 300 × 270um ²; In addition, the cascode(cascade that input and output level all adopts) structure can obtain high PSRR, and emulation shows that in 100kHz frequency range, PSRR, more than 45db, meets system requirements.

As shown in Figure 3, for the circuit structure of low-power consumption high linearity trsanscondutance amplifier entirety of the present invention, described biasing circuit comprises a PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, a NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3 and current source;

Described Rail-to-Rail input stage comprises the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the 7th PMOS pipe MP7, the 8th PMOS pipe MP8, the 9th PMOS pipe MP9, the tenth PMOS pipe MP10, the 11 PMOS pipe MP11, the 12 PMOS pipe MP12, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 6th NMOS pipe MN6, the 7th NMOS pipe MN7, the 8th NMOS pipe MN8, the 9th NMOS pipe MN9, the tenth NMOS pipe MN10, the 11 NMOS pipe MN11, the first resistance R SN and the second resistance R SP,

Described Push-Pull output stage comprises the 13 PMOS pipe MP13, the 14 PMOS pipe MP14, the 15 PMOS pipe MP15, the 16 PMOS pipe MP16, the 17 PMOS pipe MP17, the 18 PMOS pipe MP18, the 12 NMOS pipe MN12, the 13 NMOS pipe MN13, the 14 NMOS pipe MN14, the 15 NMOS pipe MN15, the 16 NMOS pipe MN16, the 17 NMOS pipe MN17, the 3rd resistance R BP and the 4th resistance R BN; Wherein,

The lining termination power voltage of the source lining end of the one PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the 9th PMOS pipe MP9, the tenth PMOS pipe MP10, the 15 PMOS pipe MP15, the 16 PMOS pipe MP16 and the 11 PMOS pipe MP11, the 12 PMOS pipe MP12, the 17 PMOS pipe MP17, the 18 PMOS pipe MP18;

The grid end of the grid leak end of the one PMOS pipe MP1, the grid end of the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the grid end of the 5th PMOS pipe MP5, the grid end of the 6th PMOS pipe MP6 all connect current source forward end, current source negative end earthing potential;

The grid end of the grid end of the grid leak end of the one NMOS pipe MN1, the grid end of the tenth NMOS pipe MN10, the 11 NMOS pipe MN11, the grid end of the 16 NMOS pipe MN16, the 17 NMOS pipe MN17 is all connected with the drain terminal of the 2nd PMOS pipe MP2;

The grid end of the grid end of the grid leak end of the 2nd NMOS pipe MN2, the grid end of the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the grid of the 5th NMOS pipe MN5, the 8th NMOS pipe MN8, the grid end of the 9th NMOS pipe MN9 are all connected with the drain terminal of the 3rd PMOS pipe MP3;

The grid end of the grid end of the grid leak end of the 4th PMOS pipe MP4, the grid end of the 11 PMOS pipe MP11, the 12 PMOS pipe MP12, the grid end of the 17 PMOS pipe MP17, the 18 PMOS pipe MP18 is all connected with the drain terminal of the 3rd NMOS pipe MN3;

The grid end of the 6th NMOS pipe MN6 is connected as an input with the grid end of the 7th PMOS pipe MP7, the grid end of the 7th NMOS pipe MN7 is connected as another input with the grid end of the 8th PMOS pipe MP8, and the source lining end of the 6th NMOS pipe MN6, the source lining end of the 7th NMOS pipe MN7 are connected and pass through the first resistance R SN cross-over connection with the drain terminal of the 4th NMOS pipe MN4, the drain terminal of the 5th NMOS pipe MN5 respectively;

The source lining end of the 7th PMOS pipe MP7, the source lining end of the 8th PMOS pipe MP8 are connected and pass through the second resistance R SP cross-over connection with the drain terminal of the 5th PMOS pipe MP5, the drain terminal of the 6th PMOS pipe MP6 respectively;

The drain terminal of the 9th PMOS pipe MP9, the source of the 11 PMOS pipe MP11 are connected with the drain terminal of the 7th NMOS pipe MN7; The drain terminal of the tenth PMOS pipe MP10, the source of the 12 PMOS pipe MP12 are connected with the drain terminal of the 6th NMOS pipe MN6;

The drain terminal of the 8th NMOS pipe MN8, the source of the tenth NMOS pipe MN10 are connected with the drain terminal of the 8th PMOS pipe MP8; The drain terminal of the 9th NMOS pipe MN9, the source of the 11 NMOS pipe MN11 are connected with the drain terminal of the 7th PMOS pipe MP7;

The drain terminal of the grid end of the 9th PMOS pipe MP9, the grid end of the tenth PMOS pipe MP10, the 11 PMOS pipe MP11 is all connected with the drain terminal of the tenth NMOS pipe MN10; The source of the drain terminal of the 12 PMOS pipe MP12, the source lining end of the 14 PMOS pipe MP14, the 13 NMOS pipe MN13 is all connected with the drain terminal of the 11 NMOS pipe MN11;

The 12 NMOS pipe MN12 drain-gate end, the 13 NMOS pipe MN13 grid termination the 3rd resistance R BP are to power supply; The 13 PMOS pipe MP13 drain-gate end, the 14 PMOS pipe MP14 grid termination the 4th resistance R BN are to earth potential, and the source of the 12 NMOS pipe MN12 connects the source lining end of the 13 PMOS pipe MP13;

The drain terminal of the grid end of the 15 PMOS pipe MP15, the grid end of the 16 PMOS pipe MP16, the 17 PMOS pipe MP17 is all connected with the drain terminal of the 13 NMOS pipe MN13; The drain terminal of the grid end of the 14 NMOS pipe MN14, the grid end of the 15 NMOS pipe MN15, the 16 NMOS pipe MN16 is all connected with the drain terminal of the 14 PMOS pipe MP14;

The drain terminal of the 15 PMOS pipe MP15, the drain terminal of the 16 PMOS pipe MP16 are connected with the source of the 17 PMOS pipe MP17, the source of the 18 PMOS pipe MP18 respectively;

The drain terminal of the 14 NMOS pipe MN14, the drain terminal of the 15 NMOS pipe MN15 are connected with the source of the 16 NMOS pipe MN16, the source of the 17 NMOS pipe MN17 respectively; The drain terminal of the 17 NMOS pipe MN17 is connected as output with the drain terminal of the 18 PMOS pipe MP18;

The lining of the source lining end of the one NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 8th NMOS pipe MN8, the 9th NMOS pipe MN9, the 14 NMOS pipe MN14, the 15 NMOS pipe MN15 and the tenth NMOS pipe MN10, the 11 NMOS pipe MN11, the 12 NMOS pipe MN12, the 13 NMOS pipe MN13, the 16 NMOS pipe MN16, the 17 NMOS pipe MN17 is held equal earthing potential

Wherein, described current source IB, NMOS pipe MN1, MN2, MN3 and PMOS pipe MP1, MP2, MP3, MP4 form biasing circuit.Power vd D powers on and can produce bias voltage VB1, VB2, VB3, VB4 and provide bias voltage for Rail-to-Rail input stage and Push-Pull output stage.

Described NMOS pipe MN4～MN11, PMOS pipe MP5～MP12, resistance R SN, RSP composition Rail-to-Rail input stage.Adopt the input of double folding differential pair can realize ICMR rail-to-rail, adopt the negative feedback of source resistance cross connection type can realize linearisation mutual conductance, adopt cascade cascode structure not only can improve current delivery accuracy and also can improve PSRR.

Described NMOS pipe MN12～MN17, PMOS pipe MP13～MP18, resistance R BN, RBP composition Push-Pull output stage.Wherein MN12, MP13, RBP, RBN can provide low-power consumption biasing for MN13, MP14, by regulating RBP, RBN size can realize the compromise of chip area and power consumption, NMOS pipe MN14～MN17, PMOS pipe MP15～MP18 current mirror structure can be realized electric current and amplify, and improves the ability that drives load.

Operation principle of the present invention:

For biasing circuit, all pipes are set and are all operated in saturation region.In order to guarantee that thereby nmos differential has identical tail current source to MN6, MN7 and PMOS differential pair MP7, MP8 and guarantees to have identical mutual conductance, must arrange ${(W/L)}_{P1}={(W/L)}_{P3}=\frac{1}{2}{(W/L)}_{P5}=\frac{1}{2}{(W/L)}_{P6},{(W/L)}_{\mathrm{<figure-callout\; id="2"\; label="N"\; filenames="HDA0000471407550000011.png,HDA0000471407550000012.png"\; state="\{\{state\}\}">N</figure-callout>}2}={(W/L)}_{N4}={(W/L)}_{N5};$ In order to guarantee that thereby the suitable amplitude of oscillation scope that makes of cascade pipe biasing maximizes, and must arrange (WL) _n1be about (WL) _n2's

in order to guarantee the accuracy of image current, the ditch length of mirror image pipe must be arranged larger to reduce the impact of channel-length modulation.

For Rail-to-Rail input stage circuit, all pipe works are set in saturation region.Nmos differential is to realizing common-mode input range (V _gSN6,7+ V _dSATN4,5)～VDD, PMOS differential pair can be realized common-mode input range VSS～(VDD-V _dSATP5,6-V _gS7,8), two differential pair structures can be easy to realize common-mode input range rail-to-rail, in order to make two differential pair actings in conjunction interval larger, adopt resistance cross connection type structure (shown in Fig. 1) to realize linearisation mutual conductance, and acting in conjunction interval is now (V _gSN6,7+ V _dSATN4,5)～(VDD-V _dSATP5,6-V _gS7,8), be (V and adopt the acting in conjunction interval of resistance separate type (shown in Fig. 2) _gSN6,7+ V _dSATN4,5+ V _rSN)～(VDD-V _dSATP5,6-V _gS7,8-V _rSP), clearly structure shown in Fig. 1 can obtain larger acting in conjunction interval; RSN=RSP=RS is set, has:

$G_{\mathrm{mN}\mathrm{6,7}}=\frac{g_{\mathrm{mN}\mathrm{6,7}}}{1+g_{\mathrm{mN}\mathrm{6,7}}\&CenterDot;(\frac{\mathrm{RSN}}{2}//r_{\mathrm{dsN}\mathrm{4,5}})}\&ap;\frac{g_{\mathrm{mN}\mathrm{6,7}}}{1+g_{\mathrm{mN}\mathrm{6,7}}\&CenterDot;\frac{\mathrm{RSN}}{2}}\&ap;\frac{2}{\mathrm{RSN}}---\left(4\right)$

$G_{\mathrm{mP}\mathrm{7,8}}=\frac{g_{\mathrm{mP}\mathrm{7,8}}}{1+g_{\mathrm{mP}\mathrm{7,8}}\&CenterDot;(\frac{\mathrm{<figure-callout\; id="2"\; label="RSP"\; filenames="HDA0000471407550000011.png,HDA0000471407550000012.png"\; state="\{\{state\}\}">RSP</figure-callout>}}{2}//r_{\mathrm{dsP}\mathrm{5,6}})}\&ap;\frac{g_{\mathrm{mP}\mathrm{7,8}}}{1+g_{\mathrm{mP}\mathrm{7,8}}\&CenterDot;\frac{\mathrm{<figure-callout\; id="2"\; label="RSP"\; filenames="HDA0000471407550000011.png,HDA0000471407550000012.png"\; state="\{\{state\}\}">RSP</figure-callout>}}{2}}\&ap;\frac{2}{\mathrm{RSP}}---\left(2\right)$

$G_{\mathrm{mN}\mathrm{6,7}}=G_{\mathrm{mP}\mathrm{7,8}}\&ap;\frac{2}{\mathrm{RS}}---\left(3\right)$

Wherein G _mN6,7and G _mP7,8represent that respectively equivalent transconductance and PMOS differential pair MP7, MP8 that nmos differential adds after source negative feedback MN6, MN7 add the equivalent transconductance after source negative feedback, g _mNi, r _dsNirepresent respectively mutual conductance, the drain-source resistance of i NMOS pipe, g _mPi, r _dsPirepresent respectively mutual conductance, the drain-source resistance of i PMOS pipe.

Can find out that by expression formula (3) the right mutual conductance of input difference is only determined by source cross-over connection resistance, realize linearisation, adopt isolated resistance and matching technique can make nmos differential to more accurate with the mutual conductance of PMOS differential pair on domain, linearisation is better.

For Push-Pull output-stage circuit, be mainly to realize current delivery to amplify, adopt current buffer and current mirror structure for amplifying.The connection of MN12 diode, the connection of MP13 diode, RBN, RBP setover for current buffer metal-oxide-semiconductor MN13, MP14 provide low-power consumption, and the resistance that increases RBN, RBP can reduce power consumption; The output of input stage from the source input of MN13, MP14, drain terminal output through current mirror structure for amplifying MN14～MN17 and MP15～MP18 ratio amplified current; When large-signal, input stage exporting change Amplitude Ratio is larger, can make MN13, MP14 have individual pipe to enter cut-off region, recommends output thereby realize;

Can find out, a kind of low-power consumption high linearity Push-Pull trsanscondutance amplifier that the present invention proposes is simple in structure, only use 17 NMOS, 18 PMOS pipes and 4 resistance, be applicable to being very much applied to the error amplifier of field of switch power as voltage control loop core.

Claims (2)

1. a low-power consumption high linearity trsanscondutance amplifier, is characterized in that, comprises the biasing circuit, Rail-to-Rail input stage and the Push-Pull output stage that connect successively; Described biasing circuit is made up of image current mirror pipe, for Rail-to-Rail input stage and Push-Pull output stage provide bias voltage; Described Rail-to-Rail input stage adopts collapsible nmos differential to realizing common-mode input range rail-to-rail with PMOS differential pair, and adopts source negative feedback to realize linearisation mutual conductance; Described Push-Pull output stage adopts low-power consumption biasing to realize low-power consumption and recommends output, and adopts image current to amplify raising output driving force.

2. a kind of low-power consumption high linearity trsanscondutance amplifier according to claim 1, it is characterized in that, described biasing circuit comprises a PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, a NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3 and current source;

Described Rail-to-Rail input stage comprises the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the 7th PMOS pipe MP7, the 8th PMOS pipe MP8, the 9th PMOS pipe MP9, the tenth PMOS pipe MP10, the 11 PMOS pipe MP11, the 12 PMOS pipe MP12, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 6th NMOS pipe MN6, the 7th NMOS pipe MN7, the 8th NMOS pipe MN8, the 9th NMOS pipe MN9, the tenth NMOS pipe MN10, the 11 NMOS pipe MN11, the first resistance R SN and the second resistance R SP,

Described Push-Pull output stage comprises the 13 PMOS pipe MP13, the 14 PMOS pipe MP14, the 15 PMOS pipe MP15, the 16 PMOS pipe MP16, the 17 PMOS pipe MP17, the 18 PMOS pipe MP18, the 12 NMOS pipe MN12, the 13 NMOS pipe MN13, the 14 NMOS pipe MN14, the 15 NMOS pipe MN15, the 16 NMOS pipe MN16, the 17 NMOS pipe MN17, the 3rd resistance R BP and the 4th resistance R BN; Wherein,

The lining termination power voltage of the source lining end of the one PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the 9th PMOS pipe MP9, the tenth PMOS pipe MP10, the 15 PMOS pipe MP15, the 16 PMOS pipe MP16 and the 11 PMOS pipe MP11, the 12 PMOS pipe MP12, the 17 PMOS pipe MP17, the 18 PMOS pipe MP18;

The grid end of the grid leak end of the one PMOS pipe MP1, the grid end of the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the grid end of the 5th PMOS pipe MP5, the grid end of the 6th PMOS pipe MP6 all connect current source forward end, current source negative end earthing potential;

The grid end of the grid end of the grid leak end of the one NMOS pipe MN1, the grid end of the tenth NMOS pipe MN10, the 11 NMOS pipe MN11, the grid end of the 16 NMOS pipe MN16, the 17 NMOS pipe MN17 is all connected with the drain terminal of the 2nd PMOS pipe MP2;

The grid end of the grid end of the grid leak end of the 2nd NMOS pipe MN2, the grid end of the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the grid of the 5th NMOS pipe MN5, the 8th NMOS pipe MN8, the grid end of the 9th NMOS pipe MN9 are all connected with the drain terminal of the 3rd PMOS pipe MP3;

The grid end of the grid end of the grid leak end of the 4th PMOS pipe MP4, the grid end of the 11 PMOS pipe MP11, the 12 PMOS pipe MP12, the grid end of the 17 PMOS pipe MP17, the 18 PMOS pipe MP18 is all connected with the drain terminal of the 3rd NMOS pipe MN3;

The grid end of the 6th NMOS pipe MN6 is connected as an input with the grid end of the 7th PMOS pipe MP7, the grid end of the 7th NMOS pipe MN7 is connected as another input with the grid end of the 8th PMOS pipe MP8, and the source lining end of the 6th NMOS pipe MN6, the source lining end of the 7th NMOS pipe MN7 are connected and pass through the first resistance R SN cross-over connection with the drain terminal of the 4th NMOS pipe MN4, the drain terminal of the 5th NMOS pipe MN5 respectively;

The source lining end of the 7th PMOS pipe MP7, the source lining end of the 8th PMOS pipe MP8 are connected and pass through the second resistance R SP cross-over connection with the drain terminal of the 5th PMOS pipe MP5, the drain terminal of the 6th PMOS pipe MP6 respectively;

The drain terminal of the 9th PMOS pipe MP9, the source of the 11 PMOS pipe MP11 are connected with the drain terminal of the 7th NMOS pipe MN7; The drain terminal of the tenth PMOS pipe MP10, the source of the 12 PMOS pipe MP12 are connected with the drain terminal of the 6th NMOS pipe MN6;

The drain terminal of the 8th NMOS pipe MN8, the source of the tenth NMOS pipe MN10 are connected with the drain terminal of the 8th PMOS pipe MP8; The drain terminal of the 9th NMOS pipe MN9, the source of the 11 NMOS pipe MN11 are connected with the drain terminal of the 7th PMOS pipe MP7;

The drain terminal of the grid end of the 9th PMOS pipe MP9, the grid end of the tenth PMOS pipe MP10, the 11 PMOS pipe MP11 is all connected with the drain terminal of the tenth NMOS pipe MN10; The source of the drain terminal of the 12 PMOS pipe MP12, the source lining end of the 14 PMOS pipe MP14, the 13 NMOS pipe MN13 is all connected with the drain terminal of the 11 NMOS pipe MN11;

The 12 NMOS pipe MN12 drain-gate end, the 13 NMOS pipe MN13 grid termination the 3rd resistance R BP are to power supply; The 13 PMOS pipe MP13 drain-gate end, the 14 PMOS pipe MP14 grid termination the 4th resistance R BN are to earth potential, and the source of the 12 NMOS pipe MN12 connects the source lining end of the 13 PMOS pipe MP13;

The drain terminal of the grid end of the 15 PMOS pipe MP15, the grid end of the 16 PMOS pipe MP16, the 17 PMOS pipe MP17 is all connected with the drain terminal of the 13 NMOS pipe MN13; The drain terminal of the grid end of the 14 NMOS pipe MN14, the grid end of the 15 NMOS pipe MN15, the 16 NMOS pipe MN16 is all connected with the drain terminal of the 14 PMOS pipe MP14;

The drain terminal of the 15 PMOS pipe MP15, the drain terminal of the 16 PMOS pipe MP16 are connected with the source of the 17 PMOS pipe MP17, the source of the 18 PMOS pipe MP18 respectively;

The drain terminal of the 14 NMOS pipe MN14, the drain terminal of the 15 NMOS pipe MN15 are connected with the source of the 16 NMOS pipe MN16, the source of the 17 NMOS pipe MN17 respectively; The drain terminal of the 17 NMOS pipe MN17 is connected as output with the drain terminal of the 18 PMOS pipe MP18;

The lining of the source lining end of the one NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 8th NMOS pipe MN8, the 9th NMOS pipe MN9, the 14 NMOS pipe MN14, the 15 NMOS pipe MN15 and the tenth NMOS pipe MN10, the 11 NMOS pipe MN11, the 12 NMOS pipe MN12, the 13 NMOS pipe MN13, the 16 NMOS pipe MN16, the 17 NMOS pipe MN17 is held equal earthing potential.

Images