CN103457554A - Rail-to-rail operation amplifier - Google Patents
Rail-to-rail operation amplifier Download PDFInfo
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- CN103457554A CN103457554A CN2013103694325A CN201310369432A CN103457554A CN 103457554 A CN103457554 A CN 103457554A CN 2013103694325 A CN2013103694325 A CN 2013103694325A CN 201310369432 A CN201310369432 A CN 201310369432A CN 103457554 A CN103457554 A CN 103457554A
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Abstract
The invention provides a rail-to-rail operation amplifier, which comprises an input stage and an output stage, wherein the input stage comprises a first current source, a first input stage, a second current source, a second input stage, a third current source, a fourth current source and a folding stage, the first current source generates first constant current signals, the first input stage converts first differential voltage signals into first different current signals to be input into the folding stage, the second current source generates second constant current signals, the second input stage converts the first differential voltage signals into second differential current signals to be input to the output stage, the third current source generates third constant current signals, the fourth current source generates fourth constant current signals, and the folding stage inputs the first differential current signals into the output stage. The rail-to-rail operation amplifier provided by the invention has the advantages that the input stages are asymmetrical, so the common mode voltage output by the input stage is not Vdd/2, and the driving voltage of the output stage is higher, so the bandwidth of the signals output by the output stage is greater.
Description
Technical field
The present invention relates to electric and electronic technical field, relate in particular to a kind of rail-to-rail operational amplifier.
Background technology
At present, along with reducing gradually of integrated circuit technology characteristic size, the size of chip is also more and more less, and in chip, the voltage Vdd of power supply is also reducing gradually.
In prior art, the input stage of traditional rail-to-rail operational amplifier is symmetrical structure, and the common-mode voltage of input stage output is Vdd/2.The circuit diagram that Fig. 1 is existing rail-to-rail operational amplifier, as shown in Figure 1, comprise input stage 100 and output stage 200, wherein in input stage: the first field effect transistor 1, the second field effect transistor 2 are N-type metal-oxide semiconductor (MOS) (N-Mental-Oxide-Semiconductor, be called for short NMOS) input pipe, comprise that the current source of the 3rd NMOS field effect transistor 3 provides electric current for it; The 4th field effect transistor 4, the 5th field effect transistor 5 are that P-type mos (P-Mental-Oxide-Semiconductor is called for short PMOS) input, to pipe, comprises that the current source of the 6th PMOS field effect transistor 6 provides electric current for it; The 7th field effect transistor 7, the 8th field effect transistor 8, for the PMOS folded stages of NMOS input to pipe, comprise that the current source of the 9th PMOS field effect transistor 9, the tenth PMOS field effect transistor 10 provides electric current for it; The 13 field effect transistor the 13, the 14 field effect transistor 14, for the NMOS folded stages of PMOS input to pipe, comprises that the current source of the 11 NMOS field effect transistor 11, the 12 NMOS field effect transistor 12 provides electric current for it.Its operation principle is: input voltage is amplified by two paths, the NMOS input is converted to electric current to pipe by input voltage on the one hand, and export after the PMOS folded stages, the PMOS input is converted to electric current to pipe by input voltage on the other hand, and export after the NMOS folded stages, input to the output stage of rail-to-rail operational amplifier after the stack of two-way output signal as final output voltage.
But there is following defect in prior art: because the common-mode voltage of input stage output is Vdd/2, at supply voltage Vdd hour, the driving voltage of output stage is less, causes the bandwidth of signal of output stage output less.
Summary of the invention
The invention provides a kind of rail-to-rail operational amplifier, in order to solve in prior art, exist at supply voltage Vdd hour, the less problem of bandwidth of the signal of output stage output.
The invention provides a kind of rail-to-rail operational amplifier, comprising: input stage and output stage, described input stage comprises the first current source, the first input stage, the second current source, the second input stage, the 3rd current source, the 4th current source and folded stages, wherein:
Described the first current source, for generating the first constant current signal;
Described the first input stage, for receiving the first differential voltage signal and described the first constant current signal, and be converted to the first differential current signal by described the first differential voltage signal and input to described folded stages;
Described the second current source, for generating the second constant current signal;
Described the second input stage, for receiving described the first differential voltage signal and described the second constant current signal, and be converted to the second differential current signal by described the first differential voltage signal and input to described output stage;
Described the 3rd current source, for generating the 3rd constant current signal;
Described the 4th current source, for generating the 4th constant current signal;
Described folded stages, for receiving described the first differential current signal, described the 4th constant current signal and described the 3rd constant current signal, and input to described output stage by described the first differential current signal.
Rail-to-rail operational amplifier provided by the invention, owing to after the second input stage, there is no folded stages, the input stage that is the rail-to-rail operational amplification circuit of the present embodiment is dissymmetrical structure, the first differential voltage signal that input stage is received, export after the first input stage and folded stages on one tunnel, one tunnel is directly output after the second input stage, and then the common-mode voltage that makes input stage output is not Vdd/2, at supply voltage Vdd hour, the driving voltage of output stage is larger, thereby makes the bandwidth of signal of output stage output larger.
The accompanying drawing explanation
The circuit diagram that Fig. 1 is existing rail-to-rail operational amplifier;
The circuit diagram that Fig. 2 is an embodiment of rail-to-rail operational amplifier provided by the invention;
The circuit diagram that Fig. 3 is rail-to-rail another embodiment of operational amplifier provided by the invention;
The circuit diagram that Fig. 4 is rail-to-rail another embodiment of operational amplifier provided by the invention;
The circuit diagram of the embodiment of output stage that Fig. 5 is rail-to-rail operational amplifier provided by the invention;
The circuit diagram of another embodiment of output stage that Fig. 6 is rail-to-rail operational amplifier provided by the invention;
The circuit diagram of another embodiment of output stage that Fig. 7 is rail-to-rail operational amplifier provided by the invention.
Embodiment
Below by specific embodiment and accompanying drawing, technical scheme of the present invention is described in further detail.
The circuit diagram that Fig. 2 is an embodiment of rail-to-rail operational amplifier provided by the invention.As shown in Figure 2, this rail-to-rail operational amplifier comprises: input stage 21 and output stage 22, input stage 21 comprises the first current source 23, the first input stage 24, the second current source 25, the second input stage 26, the 3rd current source 27, the 4th current source 28 and folded stages 29, wherein:
The first current source 23, for generating the first constant current signal;
The first input stage 24, for receiving the first differential voltage signal and the first constant current signal, and be converted to the first differential current signal by the first differential voltage signal and input to folded stages 29;
The second current source 25, for generating the second constant current signal;
The second input stage 26, for receiving the first differential voltage signal and the second constant current signal, and be converted to the second differential current signal by the first differential voltage signal and input to output stage 22;
The 3rd current source 27, for generating the 3rd constant current signal;
The 4th current source 28, for generating the 4th constant current signal;
Folded stages 29, for receiving the first differential current signal, the 4th constant current signal and the 3rd constant current signal, and input to output stage 22 by the first differential current signal.
Concrete, the first differential voltage signal that inputs to input stage 21 is exaggerated through two different paths, one tunnel is converted into the first differential current signal after the first input stage 24, and input to output stage 22 after folded stages 29, another road be converted into the second differential current signal after the second input stage 26 and be directly inputted into output stage 22, the first differential current signal and the second differential current signal stack after input to output stage 22.Output stage 22 is specifically as follows the output stage of existing various rail-to-rail operational amplifiers.
The rail-to-rail operational amplifier that the present embodiment provides, owing to after the second input stage, there is no folded stages, the input stage that is the rail-to-rail operational amplification circuit of the present embodiment is dissymmetrical structure, the first differential voltage signal that input stage is received, export after the first input stage and folded stages on one tunnel, one tunnel is directly output after the second input stage, and then the common-mode voltage that makes input stage output is not Vdd/2, at supply voltage Vdd hour, can supply with the overdrive voltage that output stage is larger, make the bandwidth of signal of output stage output larger.
The circuit diagram that Fig. 3 is rail-to-rail another embodiment of operational amplifier provided by the invention.As shown in Figure 3, the present embodiment, on basis embodiment illustrated in fig. 2, has further described a kind of concrete structure of input stage 21, and this input stage 21 comprises a plurality of NMOS pipes and a plurality of PMOS pipe, concrete:
The first input stage 24 comprises the first field effect transistor 1 and the second field effect transistor 2, the first current source 23 comprises the 3rd field effect transistor 3, the second input stage 26 comprises the 4th field effect transistor 4 and the 5th field effect transistor 5, the second current source 25 comprises the 6th field effect transistor 6, folded stages 29 comprises the 7th field effect transistor 7 and the 8th field effect transistor 8, the 3rd current source 27 comprises that the 9th field effect transistor 9 and the tenth field effect transistor 10, the four current sources 28 comprise the 11 field effect transistor 11 and the 12 field effect transistor 12;
The source electrode of the source electrode of the first field effect transistor 1 and the second field effect transistor 2 is electrically connected to the drain electrode of the 3rd field effect transistor 3 respectively, the drain electrode of the first field effect transistor 1 is electrically connected to the source electrode of the 7th field effect transistor 7, the grid of the first field effect transistor 1 is electrically connected to the grid of the 4th field effect transistor 4, the drain electrode of the second field effect transistor 2 is electrically connected to the source electrode of the 8th field effect transistor 8, and the grid of the second field effect transistor 2 is electrically connected to the grid of the 5th field effect transistor 5;
The grid of the 3rd field effect transistor 3 is electrically connected to the grid of the 11 field effect transistor 11 and the grid of the 12 field effect transistor 12 respectively;
The source electrode of the source electrode of the 4th field effect transistor 4 and the 5th field effect transistor 5 is electrically connected to the drain electrode of the 6th field effect transistor 6 respectively, the drain electrode of the 4th field effect transistor 4 is electrically connected to the drain electrode of the 7th field effect transistor 7, and the drain electrode of the 5th field effect transistor 5 is electrically connected to the drain electrode of the 8th field effect transistor 8;
The grid of the 6th field effect transistor 6 is electrically connected to the grid of the 9th field effect transistor 9 and the grid of the tenth field effect transistor 10 respectively;
The grid of the 7th field effect transistor 7 is electrically connected to the grid of the 8th field effect transistor 8, the source electrode of the 7th field effect transistor 7 is electrically connected to the drain electrode of the 9th field effect transistor 9, the drain electrode of the 7th field effect transistor 7 is electrically connected to drain electrode and the output stage 22 of the 11 field effect transistor 11 respectively, the source electrode of the 8th field effect transistor 8 is electrically connected to the drain electrode of the tenth field effect transistor 10, and the drain electrode of the 8th field effect transistor 8 is electrically connected to drain electrode and the output stage 22 of the 12 field effect transistor 12 respectively.
Wherein, the first field effect transistor 1, the second field effect transistor 2, the 3rd field effect transistor the 3, the 11 field effect transistor 11 and the 12 field effect transistor 12 are N-type metal-oxide semiconductor (MOS) NMOS field effect transistor;
The 4th field effect transistor 4, the 5th field effect transistor 5, the 6th field effect transistor 6, the 7th field effect transistor 7, the 8th field effect transistor 8, the 9th field effect transistor 9 and the tenth field effect transistor 10 are P-type mos PMOS field effect transistor;
The source electrode of the source electrode of the 3rd field effect transistor 3, the source electrode of the 11 field effect transistor 11 and the 12 field effect transistor 12 is ground connection respectively, and the source electrode of the source electrode of the 6th field effect transistor 6, the 9th field effect transistor 9 and the source electrode of the tenth field effect transistor 10 are electrically connected to power supply respectively.
Concrete, input stage 21 receives the first differential voltage signal of input by input port IN1+, IN1-, positive signal in the first differential voltage signal inputs to respectively the grid of the first field effect transistor 1 and the grid of the 4th field effect transistor 4 by input port IN1+, and the negative signal in the first differential voltage signal inputs to respectively the grid of the second field effect transistor 2 and the grid of the 5th field effect transistor 5 by input port IN1-.
The first field effect transistor 1 receives the positive signal in the first differential voltage signal by grid, and export the source electrode of positive signal to the seven field effect transistor 7 in the first differential current signal by drain electrode, the 7th field effect transistor 7 is exported the positive signal in the first differential current signal by drain electrode.The 4th field effect transistor 4 receives the positive signal in the first differential voltage signal by grid, and exports the positive signal in the second differential current signal by drain electrode.Input to output stage 22 after positive signal stack in the second differential current signal of the positive signal in the first differential current signal of the 7th field effect transistor 7 drain electrode outputs and the 4th field effect transistor 4 drain electrode outputs.
The second field effect transistor 2 receives the negative signal in the first differential voltage signal by grid, and export the source electrode of negative signal to the eight field effect transistor 8 in the first differential current signal by drain electrode, the 8th field effect transistor 8 is exported the negative signal in the first differential current signal by drain electrode.The 5th field effect transistor 5 receives the negative signal in the first differential voltage signal by grid, and exports the negative signal in the second differential current signal by drain electrode.Input to output stage 22 after negative signal stack in the second differential current signal of the negative signal in the first differential current signal of the 8th field effect transistor 8 drain electrode outputs and the 5th field effect transistor 5 drain electrode outputs.
The rail-to-rail operational amplifier that the present embodiment provides, owing to after the second input stage, there is no folded stages, the input stage that is the rail-to-rail operational amplification circuit of the present embodiment is dissymmetrical structure, the first differential voltage signal that input stage is received, export after the first input stage and folded stages on one tunnel, one tunnel is directly output after the second input stage, and then the common-mode voltage that makes input stage output is not Vdd/2, be generally less than Vdd/2, at supply voltage Vdd hour, can supply with the overdrive voltage that output stage is larger, thereby make the bandwidth of signal of output stage output larger.
The circuit diagram that Fig. 4 is rail-to-rail another embodiment of operational amplifier provided by the invention.As shown in Figure 4, the present embodiment, on basis embodiment illustrated in fig. 2, has further described the another kind of concrete structure of input stage 21, this input stage 21 with embodiment illustrated in fig. 3 in input stage 21 symmetries, also comprise that a plurality of NMOS pipes and a plurality of PMOS manage, concrete:
The first input stage 24 comprises the first field effect transistor 1 and the second field effect transistor 2, the first current source 23 comprises the 3rd field effect transistor 3, the second input stage 26 comprises the 4th field effect transistor 4 and the 5th field effect transistor 5, the second current source 25 comprises the 6th field effect transistor 6, folded stages 29 comprises the 7th field effect transistor 7 and the 8th field effect transistor 8, the 3rd current source 27 comprises that the 9th field effect transistor 9 and the tenth field effect transistor 10, the four current sources 28 comprise the 11 field effect transistor 11 and the 12 field effect transistor 12;
The source electrode of the source electrode of the first field effect transistor 1 and the second field effect transistor 2 is electrically connected to the drain electrode of the 3rd field effect transistor 3 respectively, the drain electrode of the first field effect transistor 1 is electrically connected to the source electrode of the 7th field effect transistor 7, the grid of the first field effect transistor 1 is electrically connected to the grid of the 4th field effect transistor 4, the drain electrode of the second field effect transistor 2 is electrically connected to the source electrode of the 8th field effect transistor 8, and the grid of the second field effect transistor 2 is electrically connected to the grid of the 5th field effect transistor 5;
The grid of the 3rd field effect transistor 3 is electrically connected to the grid of the 11 field effect transistor 11 and the grid of the 12 field effect transistor 12 respectively;
The source electrode of the source electrode of the 4th field effect transistor 4 and the 5th field effect transistor 5 is electrically connected to the drain electrode of the 6th field effect transistor 6 respectively, the drain electrode of the 4th field effect transistor 4 is electrically connected to the drain electrode of the 7th field effect transistor 7, and the drain electrode of the 5th field effect transistor 5 is electrically connected to the drain electrode of the 8th field effect transistor 8;
The grid of the 6th field effect transistor 6 is electrically connected to the grid of the 9th field effect transistor 9 and the grid of the tenth field effect transistor 10 respectively;
The grid of the 7th field effect transistor 7 is electrically connected to the grid of the 8th field effect transistor 8, the source electrode of the 7th field effect transistor 7 is electrically connected to the drain electrode of the 9th field effect transistor 9, the drain electrode of the 7th field effect transistor 7 is electrically connected to drain electrode and the output stage 22 of the 11 field effect transistor 11 respectively, the source electrode of the 8th field effect transistor 8 is electrically connected to the drain electrode of the tenth field effect transistor 10, and the drain electrode of the 8th field effect transistor 8 is electrically connected to drain electrode and the output stage 22 of the 12 field effect transistor 12 respectively.
From embodiment illustrated in fig. 3 different, wherein, the first field effect transistor 1, the second field effect transistor 2, the 3rd field effect transistor the 3, the 11 field effect transistor 11 and the 12 field effect transistor 12 are P-type mos PMOS field effect transistor;
The 4th field effect transistor 4, the 5th field effect transistor 5, the 6th field effect transistor 6, the 7th field effect transistor 7, the 8th field effect transistor 8, the 9th field effect transistor 9 and the tenth field effect transistor 10 are N-type metal-oxide semiconductor (MOS) NMOS field effect transistor;
The source electrode of the source electrode of the 3rd field effect transistor 3, the source electrode of the 11 field effect transistor 11 and the 12 field effect transistor 12 is electrically connected to power supply respectively, and the source electrode of the source electrode of the source electrode of the 6th field effect transistor 6, the 9th field effect transistor 9 and the tenth field effect transistor 10 is ground connection respectively.
Concrete, input stage 21 receives the first differential voltage signal of input by input port IN1+, IN1-, positive signal in the first differential voltage signal inputs to respectively the grid of the first field effect transistor 1 and the grid of the 4th field effect transistor 4 by input port IN1+, and the negative signal in the first differential voltage signal inputs to respectively the grid of the second field effect transistor 2 and the grid of the 5th field effect transistor 5 by input port IN1-.
The first field effect transistor 1 receives the positive signal in the first differential voltage signal by grid, and export the source electrode of positive signal to the seven field effect transistor 7 in the first differential current signal by drain electrode, the 7th field effect transistor 7 is exported the positive signal in the first differential current signal by drain electrode.The 4th field effect transistor 4 receives the positive signal in the first differential voltage signal by grid, and exports the positive signal in the second differential current signal by drain electrode.Input to output stage 22 after positive signal stack in the second differential current signal of the positive signal in the first differential current signal of the 7th field effect transistor 7 drain electrode outputs and the 4th field effect transistor 4 drain electrode outputs.
The second field effect transistor 2 receives the negative signal in the first differential voltage signal by grid, and export the source electrode of negative signal to the eight field effect transistor 8 in the first differential current signal by drain electrode, the 8th field effect transistor 8 is exported the negative signal in the first differential current signal by drain electrode.The 5th field effect transistor 5 receives the negative signal in the first differential voltage signal by grid, and exports the negative signal in the second differential current signal by drain electrode.Input to output stage 22 after negative signal stack in the second differential current signal of the negative signal in the first differential current signal of the 8th field effect transistor 8 drain electrode outputs and the 5th field effect transistor 5 drain electrode outputs.
The rail-to-rail operational amplifier that the present embodiment provides, owing to after the second input stage, there is no folded stages, the input stage that is the rail-to-rail operational amplification circuit of the present embodiment is dissymmetrical structure, the first differential voltage signal that input stage is received, export after the first input stage and folded stages on one tunnel, one tunnel is directly output after the second input stage, and then the common-mode voltage that makes input stage output is not Vdd/2, generally be greater than Vdd/2, at supply voltage Vdd hour, can supply with the overdrive voltage that output stage is larger, thereby make the bandwidth of signal of output stage output larger.
The circuit diagram of the embodiment of output stage that Fig. 5 is rail-to-rail operational amplifier provided by the invention.As shown in Figure 5, the present embodiment has further described the circuit structure of Fig. 2, Fig. 3 and middle output stage 22 embodiment illustrated in fig. 4, this output stage comprises: the 5th current source 51, the 3rd input stage 52, the first mirror image circuit 53, the 6th current source 54, the 4th input stage 55, the second mirror image circuit 56, the 7th current source 57, the first biasing circuit 58, the 3rd mirror image circuit 59, the 8th current source 60, the second biasing circuit 61, the 4th mirror image circuit 62, wherein:
The 5th current source 51, for generating the 5th constant current signal;
The 3rd input stage 52, for receiving the second differential voltage signal and the 5th constant current signal of input stage 21 input, and the negative signal in the second differential voltage signal is converted to the first current signal inputs to respectively the first mirror image circuit 53 and the 4th mirror image circuit 62;
The first mirror image circuit 53, for inputing to the first current signal the output plus terminal of rail-to-rail operational amplifier;
The 6th current source 54, for generating the 6th constant current signal;
The 4th input stage 55, for receiving the second differential voltage signal and the 6th constant current signal of input stage 21 input, and the positive signal in the second differential voltage signal is converted to the second current signal inputs to respectively the second mirror image circuit 56 and the 3rd mirror image circuit 59;
The second mirror image circuit 56, for inputing to the second current signal the output negative terminal of rail-to-rail operational amplifier;
The 7th current source 57, for generating the 7th constant current signal;
The first biasing circuit 58, for inputing to the 3rd mirror image circuit 59 by the 7th constant current signal;
The 3rd mirror image circuit 59, for receiving the second current signal and the 7th constant current signal, and input to the second current signal the output plus terminal of rail-to-rail operational amplifier;
The 8th current source 60, for generating the 8th constant current signal;
The second biasing circuit 61, for inputing to the 4th mirror image circuit 62 by the 8th constant current signal;
The 4th mirror image circuit 62, for receiving the first current signal and the 8th constant current signal, and input to the first current signal the output negative terminal of rail-to-rail operational amplifier.
Concrete, the output stage that the present embodiment provides adopts fully differential low pressure AB class amplification circuit.Negative signal in the second differential voltage signal of input stage 21 outputs is converted into the first current signal after the 3rd input stage 52, and input to the output plus terminal of rail-to-rail operational amplifier and the output negative terminal that inputs to rail-to-rail operational amplifier after the 4th mirror image circuit 62 after the first mirror image circuit 53.Positive signal in the second differential voltage signal of input stage 21 outputs is converted into the second current signal after the 4th input stage 55, and input to the output negative terminal of rail-to-rail operational amplifier and the output plus terminal that inputs to rail-to-rail operational amplifier after the 3rd mirror image circuit 59 after the second mirror image circuit 56.Input to the first current signal and the rear output of the second current signal stack of the output plus terminal of rail-to-rail operational amplifier, input to the first current signal and the rear output of the second current signal stack of the output negative terminal of rail-to-rail operational amplifier.
The output stage of the rail-to-rail operational amplifier that the present embodiment provides, at the common-mode voltage of input stage output during not at Vdd/2, can the larger signal of output bandwidth.
The circuit diagram of another embodiment of output stage that Fig. 6 is rail-to-rail operational amplifier provided by the invention.As shown in Figure 6, the present embodiment, on basis embodiment illustrated in fig. 5, has further described a kind of concrete structure of output stage 22, and this output stage 22 comprises a plurality of NMOS pipes and a plurality of PMOS pipe, concrete:
The 3rd input stage 52 comprises the 15 field effect transistor 71 and the 16 field effect transistor 72, the 5th current source 51 comprises the 17 field effect transistor 73, the first mirror image circuit 53 comprises the 18 field effect transistor 74 and the 19 field effect transistor 75, the 4th input stage 55 comprises the 20 field effect transistor 76 and the 21 field effect transistor 77, the 6th current source 54 comprises the 22 field effect transistor 78, the second mirror image circuit 56 comprises the 23 field effect transistor 79 and the 24 field effect transistor 80, the 7th current source 57 comprises the 25 field effect transistor 81, the first biasing circuit 58 comprises the 26 field effect transistor 82, the 3rd mirror image circuit 59 comprises the 27 field effect transistor 83 and the 28 field effect transistor 84, the 8th current source 60 comprises the 29 field effect transistor 85, the second biasing circuit 61 comprises the 30 field effect transistor 86, the 4th mirror image circuit 62 comprises the 31 field effect transistor 87 and the 32 field effect transistor 88.
The source electrode of the 15 field effect transistor 71 and the source electrode of the 16 field effect transistor 72 are electrically connected to the drain electrode of the 18 field effect transistor 74 respectively, the grid of the 15 field effect transistor 71 is electrically connected to the grid of the 21 field effect transistor 77, the drain electrode of the 15 field effect transistor 71 respectively with the grid of the 18 field effect transistor 74, the drain electrode of the grid of the 19 field effect transistor 75 and the 17 field effect transistor 73 is electrically connected to, the grid of the 16 field effect transistor 72 is electrically connected to the grid of the 22 field effect transistor 78, the drain electrode of the 16 field effect transistor 72 is electrically connected to the source electrode of the 30 field effect transistor 86 and the drain electrode of the 31 field effect transistor 87 respectively.
The source electrode of the 19 field effect transistor 75 is electrically connected to the source electrode of the 18 field effect transistor 74, the source electrode of the 23 field effect transistor 79 and the source electrode of the 24 field effect transistor 80 respectively, the drain electrode of the 19 field effect transistor 75 is electrically connected to the drain electrode of the 28 field effect transistor 84, and the drain electrode of the 24 field effect transistor 80 is electrically connected to the drain electrode of the 32 field effect transistor 88.
The source electrode of the 20 field effect transistor 76 and the source electrode of the 21 field effect transistor 77 are electrically connected to the drain electrode of the 23 field effect transistor 79 respectively, the drain electrode of the 20 field effect transistor 76 is electrically connected to the source electrode of the 26 field effect transistor 82 and the drain electrode of the 27 field effect transistor 83 respectively, and the drain electrode of the 21 field effect transistor 77 is electrically connected to the grid of the 23 field effect transistor 79, the grid of the 24 field effect transistor 80 and the drain electrode of the 22 field effect transistor 78 respectively.
The source electrode of the 17 field effect transistor 73 is electrically connected to the source electrode of the 22 field effect transistor 78;
The source electrode of the 25 field effect transistor 81 is electrically connected to the source electrode of the 29 field effect transistor 85, the drain electrode of the 25 field effect transistor 81 is electrically connected to the drain electrode of the 26 field effect transistor 82, the grid of the 27 field effect transistor 83 and the grid of the 28 field effect transistor 84 respectively, and the drain electrode of the 29 field effect transistor 85 is electrically connected to the drain electrode of the 30 field effect transistor 86, the grid of the 31 field effect transistor 87 and the grid of the 32 field effect transistor 88 respectively;
The source electrode of the 28 field effect transistor 84 is electrically connected to the source electrode of the 27 field effect transistor 83, the source electrode of the 31 field effect transistor 87 and the source electrode of the 32 field effect transistor 88 respectively.
Wherein, the 15 field effect transistor the 71, the 16 field effect transistor the 72, the 18 field effect transistor the 74, the 19 crystal 75 pipes, the 20 field effect transistor the 76, the 21 field effect transistor the 77, the 23 field effect transistor the 79, the 24 field effect transistor the 80, the 25 field effect transistor 81 and the 29 field effect transistor 85 are P-type mos PMOS field effect transistor;
The 17 field effect transistor the 73, the 22 field effect transistor the 78, the 26 field effect transistor the 82, the 27 field effect transistor the 83, the 28 field effect transistor the 84, the 30 field effect transistor 86 and the 31 field effect transistor 87 and the 32 field effect transistor 88 are N-type metal-oxide semiconductor (MOS) NMOS field effect transistor;
The source electrode of the source electrode of the 18 field effect transistor 74, the source electrode of the 19 field effect transistor 75, the 23 field effect transistor 79, the source electrode of the 24 field effect transistor 80, the source electrode of the 25 field effect transistor 81 and the source electrode of the 29 field effect transistor 85 are electrically connected to power supply respectively, and the source electrode of the source electrode of the source electrode of the 17 field effect transistor 73, the source electrode of the 22 field effect transistor 78, the 27 field effect transistor 83, the source electrode of the 28 field effect transistor 84, the 31 field effect transistor 87 and the source electrode of the 32 field effect transistor 88 be ground connection respectively.
Concrete, the output stage 22 that the present embodiment provides and embodiment illustrated in fig. 3 in input stage 21 be used in conjunction with, the larger signal with output bandwidth.Output stage 22 receives the second differential voltage signal of input stage 21 outputs by input port IN2+, IN2-, positive signal in the second differential voltage signal inputs to respectively the grid of the 15 field effect transistor 71 and the grid of the 20 field effect transistor 76 by input port IN2+, and the negative signal in the second differential voltage signal inputs to respectively the grid of the 16 field effect transistor 72 and the grid of the 21 field effect transistor 77 by input port IN2-.
The 16 field effect transistor 72 receives the negative signal in the second differential voltage signal by grid, and the drain electrode of exporting the first current signal to the 18 field effect transistor 74 by source electrode, the 18 field effect transistor 74 inputs to the first current signal by grid the grid of the 19 field effect transistor 75, the 19 field effect transistor 75 is exported this first current signal by drain electrode, and the drain electrode of exporting the first current signal to the 31 field effect transistor 87 by drain electrode, the 31 field effect transistor 87 inputs to the first current signal by grid the grid of the 32 field effect transistor 88, the 32 field effect transistor 88 is exported this first current signal by drain electrode.
The 20 field effect transistor 76 receives the positive signal in the second differential voltage signal by grid, and the drain electrode of exporting the second current signal to the 23 field effect transistor 79 by source electrode, and the drain electrode of exporting the second current signal to the 27 field effect transistor 83 by drain electrode, the 23 field effect transistor 79 inputs to the second current signal by grid the grid of the 24 field effect transistor 80, the 24 field effect transistor 80 is exported this second current signal by drain electrode, the 27 field effect transistor 83 inputs to the second current signal by grid the grid of the 28 field effect transistor 84, the 28 field effect transistor 84 is exported this second current signal by drain electrode.
Pass through the output plus terminal output of rail-to-rail operational amplifier after the second current signal stack of the first current signal of the drain electrode output of the 19 field effect transistor 75 and the drain electrode output of the 28 field effect transistor 84.
After the first current signal stack of the second current signal of the drain electrode output of the 24 field effect transistor 80 and the drain electrode output of the 32 field effect transistor 88, by the output negative terminal of rail-to-rail operational amplifier, export.
The output stage of the rail-to-rail operational amplifier that the present embodiment provides, when the common-mode voltage of input stage output is less than Vdd/2, can the larger signal of output bandwidth.
The circuit diagram of another embodiment of output stage that Fig. 7 is rail-to-rail operational amplifier provided by the invention.As shown in Figure 7, the present embodiment, on basis embodiment illustrated in fig. 5, has further described the another kind of concrete structure of output stage 22, this output stage 22 with embodiment illustrated in fig. 6 in output stage 22 symmetries, also comprise that a plurality of NMOS pipes and a plurality of PMOS manage, concrete:
The 3rd input stage 52 comprises the 15 field effect transistor 71 and the 16 field effect transistor 72, the 5th current source 51 comprises the 17 field effect transistor 73, the first mirror image circuit 53 comprises the 18 field effect transistor 74 and the 19 field effect transistor 75, the 4th input stage 55 comprises the 20 field effect transistor 76 and the 21 field effect transistor 77, the 6th current source 54 comprises the 22 field effect transistor 78, the second mirror image circuit 56 comprises the 23 field effect transistor 79 and the 24 field effect transistor 80, the 7th current source 57 comprises the 25 field effect transistor 81, the first biasing circuit 58 comprises the 26 field effect transistor 82, the 3rd mirror image circuit 59 comprises the 27 field effect transistor 83 and the 28 field effect transistor 84, the 8th current source 60 comprises the 29 field effect transistor 85, the second biasing circuit 61 comprises the 30 field effect transistor 86, the 4th mirror image circuit 62 comprises the 31 field effect transistor 87 and the 32 field effect transistor 88,
The source electrode of the 15 field effect transistor 71 and the source electrode of the 16 field effect transistor 72 are electrically connected to the drain electrode of the 18 field effect transistor 74 respectively, the grid of the 15 field effect transistor 71 is electrically connected to the grid of the 21 field effect transistor 77, the drain electrode of the 15 field effect transistor 71 respectively with the grid of the 18 field effect transistor 74, the drain electrode of the grid of the 19 field effect transistor 75 and the 17 field effect transistor 73 is electrically connected to, the grid of the 16 field effect transistor 72 is electrically connected to the grid of the 22 field effect transistor 78, the drain electrode of the 16 field effect transistor 72 is electrically connected to the source electrode of the 30 field effect transistor 86 and the drain electrode of the 31 field effect transistor 87 respectively,
The source electrode of the 19 field effect transistor 75 is electrically connected to the source electrode of the 18 field effect transistor 74, the source electrode of the 23 field effect transistor 79 and the source electrode of the 24 field effect transistor 80 respectively, the drain electrode of the 19 field effect transistor 75 is electrically connected to the drain electrode of the 28 field effect transistor 84, and the drain electrode of the 24 field effect transistor 80 is electrically connected to the drain electrode of the 32 field effect transistor 88;
The source electrode of the 20 field effect transistor 76 and the source electrode of the 21 field effect transistor 77 are electrically connected to the drain electrode of the 23 field effect transistor 79 respectively, the drain electrode of the 20 field effect transistor 76 is electrically connected to the source electrode of the 26 field effect transistor 82 and the drain electrode of the 27 field effect transistor 83 respectively, and the drain electrode of the 21 field effect transistor 77 is electrically connected to the grid of the 23 field effect transistor 79, the grid of the 24 field effect transistor 80 and the drain electrode of the 22 field effect transistor 78 respectively;
The source electrode of the 17 field effect transistor 73 is electrically connected to the source electrode of the 22 field effect transistor 78;
The source electrode of the 25 field effect transistor 81 is electrically connected to the source electrode of the 29 field effect transistor 85, the drain electrode of the 25 field effect transistor 81 is electrically connected to the drain electrode of the 26 field effect transistor 82, the grid of the 27 field effect transistor 83 and the grid of the 28 field effect transistor 84 respectively, and the drain electrode of the 29 field effect transistor 85 is electrically connected to the drain electrode of the 30 field effect transistor 86, the grid of the 31 field effect transistor 87 and the grid of the 32 field effect transistor 88 respectively;
The source electrode of the 28 field effect transistor 84 is electrically connected to the source electrode of the 27 field effect transistor 83, the source electrode of the 31 field effect transistor 87 and the source electrode of the 32 field effect transistor 88 respectively.
From embodiment illustrated in fig. 6 different, wherein, the 15 field effect transistor the 71, the 16 field effect transistor the 72, the 18 field effect transistor the 74, the 19 crystal 75 pipes, the 20 field effect transistor the 76, the 21 field effect transistor the 77, the 23 field effect transistor the 79, the 24 field effect transistor the 80, the 25 field effect transistor 81 and the 29 field effect transistor 85 are N-type metal-oxide semiconductor (MOS) NMOS field effect transistor;
The 17 field effect transistor the 73, the 22 field effect transistor the 78, the 26 field effect transistor the 82, the 27 field effect transistor the 83, the 28 field effect transistor the 84, the 30 field effect transistor 86 and the 31 field effect transistor 87 and the 32 field effect transistor 88 are P-type mos PMOS field effect transistor;
The source electrode of the source electrode of the source electrode of the 18 field effect transistor 74, the source electrode of the 19 field effect transistor 75, the 23 field effect transistor 79, the source electrode of the 24 field effect transistor 80, the 25 field effect transistor 81 and the source electrode of the 29 field effect transistor 85 be ground connection respectively, and the source electrode of the 17 field effect transistor 73, the source electrode of the 22 field effect transistor 78, the source electrode of the 27 field effect transistor 83, the source electrode of the 28 field effect transistor 84, the source electrode of the 31 field effect transistor 87 and the source electrode of the 32 field effect transistor 88 are electrically connected to power supply respectively.
Concrete, the output stage 22 that the present embodiment provides and embodiment illustrated in fig. 4 in input stage 21 be used in conjunction with, the larger signal with output bandwidth.Output stage 22 receives the second differential voltage signal of input stage 21 outputs by input port IN2+, IN2-, positive signal in the second differential voltage signal inputs to respectively the grid of the 15 field effect transistor 71 and the grid of the 20 field effect transistor 76 by input port IN2+, and the negative signal in the second differential voltage signal inputs to respectively the grid of the 16 field effect transistor 72 and the grid of the 21 field effect transistor 77 by input port IN2-.
The 16 field effect transistor 72 receives the negative signal in the second differential voltage signal by grid, and the drain electrode of exporting the first current signal to the 18 field effect transistor 74 by source electrode, the 18 field effect transistor 74 inputs to the first current signal by grid the grid of the 19 field effect transistor 75, the 19 field effect transistor 75 is exported this first current signal by drain electrode, and the drain electrode of exporting the first current signal to the 31 field effect transistor 87 by drain electrode, the 31 field effect transistor 87 inputs to the first current signal by grid the grid of the 32 field effect transistor 88, the 32 field effect transistor 88 is exported this first current signal by drain electrode.
The 20 field effect transistor 76 receives the positive signal in the second differential voltage signal by grid, and the drain electrode of exporting the second current signal to the 23 field effect transistor 79 by source electrode, and the drain electrode of exporting the second current signal to the 27 field effect transistor 83 by drain electrode, the 23 field effect transistor 79 inputs to the second current signal by grid the grid of the 24 field effect transistor 80, the 24 field effect transistor 80 is exported this second current signal by drain electrode, the 27 field effect transistor 83 inputs to the second current signal by grid the grid of the 28 field effect transistor 84, the 28 field effect transistor 84 is exported this second current signal by drain electrode.
Pass through the output plus terminal output of rail-to-rail operational amplifier after the second current signal stack of the first current signal of the drain electrode output of the 19 field effect transistor 75 and the drain electrode output of the 28 field effect transistor 84.
After the first current signal stack of the second current signal of the drain electrode output of the 24 field effect transistor 80 and the drain electrode output of the 32 field effect transistor 88, by the output negative terminal of rail-to-rail operational amplifier, export.
The output stage of the rail-to-rail operational amplifier that the present embodiment provides, when the common-mode voltage of input stage output is greater than Vdd/2, can the larger signal of output bandwidth.
Finally it should be noted that: above each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to aforementioned each embodiment, the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: its technical scheme that still can put down in writing aforementioned each embodiment is modified, or some or all of technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the scope of various embodiments of the present invention technical scheme.
Claims (8)
1. a rail-to-rail operational amplifier, is characterized in that, comprising: input stage and output stage, and described input stage comprises the first current source, the first input stage, the second current source, the second input stage, the 3rd current source, the 4th current source and folded stages, wherein:
Described the first current source, for generating the first constant current signal;
Described the first input stage, for receiving the first differential voltage signal and described the first constant current signal, and be converted to the first differential current signal by described the first differential voltage signal and input to described folded stages;
Described the second current source, for generating the second constant current signal;
Described the second input stage, for receiving described the first differential voltage signal and described the second constant current signal, and be converted to the second differential current signal by described the first differential voltage signal and input to described output stage;
Described the 3rd current source, for generating the 3rd constant current signal;
Described the 4th current source, for generating the 4th constant current signal;
Described folded stages, for receiving described the first differential current signal, described the 4th constant current signal and described the 3rd constant current signal, and input to described output stage by described the first differential current signal.
2. rail-to-rail operational amplifier according to claim 1, is characterized in that,
Described the first input stage comprises the first field effect transistor and the second field effect transistor, described the first current source comprises the 3rd field effect transistor, described the second input stage comprises the 4th field effect transistor and the 5th field effect transistor, described the second current source comprises the 6th field effect transistor, described folded stages comprises the 7th field effect transistor and the 8th field effect transistor, described the 3rd current source comprises the 9th field effect transistor and the tenth field effect transistor, and described the 4th current source comprises the 11 field effect transistor and the 12 field effect transistor;
The source electrode of the source electrode of described the first field effect transistor and described the second field effect transistor is electrically connected to the drain electrode of described the 3rd field effect transistor respectively, the drain electrode of described the first field effect transistor is electrically connected to the source electrode of described the 7th field effect transistor, and the grid of described the first field effect transistor is electrically connected to the grid of described the 4th field effect transistor;
The drain electrode of described the second field effect transistor is electrically connected to the source electrode of described the 8th field effect transistor, and the grid of described the second field effect transistor is electrically connected to the grid of described the 5th field effect transistor;
The grid of described the 3rd field effect transistor is electrically connected to the grid of described the 11 field effect transistor and the grid of described the 12 field effect transistor respectively;
The source electrode of the source electrode of described the 4th field effect transistor and described the 5th field effect transistor is electrically connected to the drain electrode of described the 6th field effect transistor respectively, and the drain electrode of described the 4th field effect transistor is electrically connected to the drain electrode of described the 7th field effect transistor;
The drain electrode of described the 5th field effect transistor is electrically connected to the drain electrode of described the 8th field effect transistor;
The grid of described the 6th field effect transistor is electrically connected to the grid of described the 9th field effect transistor and the grid of described the tenth field effect transistor respectively;
The grid of described the 7th field effect transistor is electrically connected to the grid of described the 8th field effect transistor, the source electrode of described the 7th field effect transistor is electrically connected to the drain electrode of described the 9th field effect transistor, and the drain electrode of described the 7th field effect transistor is electrically connected to drain electrode and the described output stage of described the 11 field effect transistor respectively;
The source electrode of described the 8th field effect transistor is electrically connected to the drain electrode of described the tenth field effect transistor, and the drain electrode of described the 8th field effect transistor is electrically connected to drain electrode and the described output stage of described the 12 field effect transistor respectively.
3. rail-to-rail operational amplifier according to claim 2, it is characterized in that, described the first field effect transistor, described the second field effect transistor, described the 3rd field effect transistor, described the 11 field effect transistor and described the 12 field effect transistor are N-type metal-oxide semiconductor (MOS) NMOS field effect transistor;
Described the 4th field effect transistor, described the 5th field effect transistor, described the 6th field effect transistor, described the 7th field effect transistor, described the 8th field effect transistor, described the 9th field effect transistor and described the tenth field effect transistor are P-type mos PMOS field effect transistor;
The source electrode of the source electrode of described the 3rd field effect transistor, the source electrode of described the 11 field effect transistor and described the 12 field effect transistor is ground connection respectively;
The source electrode of the source electrode of the source electrode of described the 6th field effect transistor, described the 9th field effect transistor and described the tenth field effect transistor is electrically connected to power supply respectively.
4. rail-to-rail operational amplifier according to claim 2, it is characterized in that, described the first field effect transistor, described the second field effect transistor, described the 3rd field effect transistor, described the 11 field effect transistor and described the 12 field effect transistor are P-type mos PMOS field effect transistor;
Described the 4th field effect transistor, described the 5th field effect transistor, described the 6th field effect transistor, described the 7th field effect transistor, described the 8th field effect transistor, described the 9th field effect transistor and described the tenth field effect transistor are N-type metal-oxide semiconductor (MOS) NMOS field effect transistor;
The source electrode of the source electrode of described the 3rd field effect transistor, the source electrode of described the 11 field effect transistor and described the 12 field effect transistor is electrically connected to power supply respectively;
The source electrode of the source electrode of the source electrode of described the 6th field effect transistor, described the 9th field effect transistor and described the tenth field effect transistor is ground connection respectively.
5. according to the described rail-to-rail operational amplifier of claim 1-4, it is characterized in that, described output stage comprises the 5th current source, the 3rd input stage, the first mirror image circuit, the 6th current source, the 4th input stage, the second mirror image circuit, the 7th current source, the first biasing circuit, the 3rd mirror image circuit, the 8th current source, the second biasing circuit, the 4th mirror image circuit, wherein:
Described the 5th current source, for generating the 5th constant current signal;
Described the 3rd input stage, for receiving the second differential voltage signal and described the 5th constant current signal of the input of described input stage, and the negative signal in described the second differential voltage signal is converted to the 3rd differential current signal inputs to respectively described the first mirror image circuit and described the 4th mirror image circuit;
Described the first mirror image circuit, for inputing to described the 3rd differential current signal the output plus terminal of described rail-to-rail operational amplifier;
Described the 6th current source, for generating the 6th constant current signal;
Described the 4th input stage, for receiving the second differential voltage signal and described the 6th constant current signal of the input of described input stage, and the positive signal in described the second differential voltage signal is converted to the 4th differential current signal inputs to respectively described the second mirror image circuit and described the 3rd mirror image circuit;
Described the second mirror image circuit, for inputing to described the 4th differential current signal the output negative terminal of described rail-to-rail operational amplifier;
Described the 7th current source, for generating the 7th constant current signal;
Described the first biasing circuit, for inputing to described the 3rd mirror image circuit by described the 7th constant current signal;
Described the 3rd mirror image circuit, for receiving described the 4th differential current signal and described the 7th constant current signal, and input to described the 4th differential current signal the output plus terminal of described rail-to-rail operational amplifier;
Described the 8th current source, for generating the 8th constant current signal;
Described the second biasing circuit, for inputing to described the 4th mirror image circuit by described the 8th constant current signal;
Described the 4th mirror image circuit, for receiving described the 3rd differential current signal and described the 8th constant current signal, and input to described the 3rd differential current signal the output negative terminal of described rail-to-rail operational amplifier.
6. rail-to-rail operational amplifier according to claim 5, it is characterized in that, described the 3rd input stage comprises the 15 field effect transistor and the 16 field effect transistor, described the 5th current source comprises the 17 field effect transistor, described the first mirror image circuit comprises the 18 field effect transistor and the 19 field effect transistor, described the 4th input stage comprises the 20 field effect transistor and the 21 field effect transistor, described the 6th current source comprises the 22 field effect transistor, described the second mirror image circuit comprises the 23 field effect transistor and the 24 field effect transistor, described the 7th current source comprises the 25 field effect transistor, described the first biasing circuit comprises the 26 field effect transistor, described the 3rd mirror image circuit comprises the 27 field effect transistor and the 28 field effect transistor, described the 8th current source comprises the 29 field effect transistor, described the second biasing circuit comprises the 30 field effect transistor, described the 4th mirror image circuit comprises the 31 field effect transistor and the 32 field effect transistor,
The source electrode of described the 15 field effect transistor and the source electrode of described the 16 field effect transistor are electrically connected to the drain electrode of described the 18 field effect transistor respectively, the grid of described the 15 field effect transistor is electrically connected to the grid of described the 21 field effect transistor, and the drain electrode of described the 15 field effect transistor is electrically connected to the grid of described the 18 field effect transistor, the grid of the 19 field effect transistor and the drain electrode of described the 17 field effect transistor respectively;
The grid of described the 16 field effect transistor is electrically connected to the grid of described the 22 field effect transistor, and the drain electrode of described the 16 field effect transistor is electrically connected to the source electrode of described the 30 field effect transistor and the drain electrode of described the 31 field effect transistor respectively;
The source electrode of described the 19 field effect transistor is electrically connected to the source electrode of the source electrode of described the 18 field effect transistor, described the 23 field effect transistor and the source electrode of described the 24 field effect transistor respectively, and the drain electrode of described the 19 field effect transistor is electrically connected to the drain electrode of described the 28 field effect transistor;
The drain electrode of described the 24 field effect transistor is electrically connected to the drain electrode of described the 32 field effect transistor;
The source electrode of described the 20 field effect transistor and the source electrode of described the 21 field effect transistor are electrically connected to the drain electrode of described the 23 field effect transistor respectively, the drain electrode of described the 20 field effect transistor is electrically connected to the source electrode of described the 26 field effect transistor and the drain electrode of described the 27 field effect transistor respectively, and the drain electrode of described the 21 field effect transistor is electrically connected to the grid of described the 23 field effect transistor, the grid of the 24 field effect transistor and the drain electrode of described the 22 field effect transistor respectively;
The source electrode of described the 17 field effect transistor is electrically connected to the source electrode of described the 22 field effect transistor;
The source electrode of described the 25 field effect transistor is electrically connected to the source electrode of described the 29 field effect transistor, and the drain electrode of described the 25 field effect transistor is electrically connected to the grid of the drain electrode of described the 26 field effect transistor, described the 27 field effect transistor and the grid of described the 28 field effect transistor respectively;
The drain electrode of described the 29 field effect transistor is electrically connected to the grid of the drain electrode of described the 30 field effect transistor, described the 31 field effect transistor and the grid of described the 32 field effect transistor respectively;
The source electrode of described the 28 field effect transistor is electrically connected to the source electrode of the source electrode of described the 27 field effect transistor, described the 31 field effect transistor and the source electrode of described the 32 field effect transistor respectively.
7. rail-to-rail operational amplifier according to claim 6, it is characterized in that, described the 15 field effect transistor, described the 16 field effect transistor, described the 18 field effect transistor, described the 19 field effect transistor, described the 20 field effect transistor, described the 21 field effect transistor, described the 23 field effect transistor, described the 24 field effect transistor, described the 25 field effect transistor and described the 29 field effect transistor are P-type mos PMOS field effect transistor;
Described the 17 field effect transistor, described the 22 field effect transistor, described the 26 field effect transistor, described the 27 field effect transistor, described the 28 field effect transistor, described the 30 field effect transistor and described the 31 field effect transistor and described the 32 field effect transistor are N-type metal-oxide semiconductor (MOS) NMOS field effect transistor;
The source electrode of described the 18 field effect transistor, the source electrode of described the 19 field effect transistor, the source electrode of described the 23 field effect transistor, the source electrode of described the 24 field effect transistor, the source electrode of described the 25 field effect transistor and the source electrode of described the 29 field effect transistor are electrically connected to power supply respectively;
The source electrode of the source electrode of described the 17 field effect transistor, the source electrode of described the 22 field effect transistor, the source electrode of described the 27 field effect transistor, the source electrode of described the 28 field effect transistor, described the 31 field effect transistor and the source electrode of described the 32 field effect transistor be ground connection respectively.
8. rail-to-rail operational amplifier according to claim 6, it is characterized in that, described the 15 field effect transistor, described the 16 field effect transistor, described the 18 field effect transistor, described the 19 field effect transistor, described the 20 field effect transistor, described the 21 field effect transistor, described the 23 field effect transistor, described the 24 field effect transistor, described the 25 field effect transistor and described the 29 field effect transistor are N-type metal-oxide semiconductor (MOS) NMOS field effect transistor;
Described the 17 field effect transistor, described the 22 field effect transistor, described the 26 field effect transistor, described the 27 field effect transistor, described the 28 field effect transistor, described the 30 field effect transistor and described the 31 field effect transistor and described the 32 field effect transistor are P-type mos PMOS field effect transistor;
The source electrode of the source electrode of described the 18 field effect transistor, the source electrode of described the 19 field effect transistor, the source electrode of described the 23 field effect transistor, the source electrode of described the 24 field effect transistor, described the 25 field effect transistor and the source electrode of described the 29 field effect transistor be ground connection respectively;
The source electrode of described the 17 field effect transistor, the source electrode of described the 22 field effect transistor, the source electrode of described the 27 field effect transistor, the source electrode of described the 28 field effect transistor, the source electrode of described the 31 field effect transistor and the source electrode of described the 32 field effect transistor are electrically connected to power supply respectively.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103825557A (en) * | 2014-02-28 | 2014-05-28 | 电子科技大学 | Transconductance amplifier with low power consumption and high linearity |
| CN103825557B (en) * | 2014-02-28 | 2017-01-11 | 电子科技大学 | Transconductance amplifier with low power consumption and high linearity |
| WO2016066075A1 (en) * | 2014-10-30 | 2016-05-06 | 华为技术有限公司 | Ultra-low working voltage rail to rail operational amplifier and differential input amplification-stage circuit and output-stage circuit thereof |
| CN104506150B (en) * | 2014-10-30 | 2017-11-17 | 华为技术有限公司 | A kind of rail-to-rail operational amplifier of ultra-low operating voltage and its Differential Input amplification grade circuit and output-stage circuit |
| US10270391B2 (en) | 2014-10-30 | 2019-04-23 | Huawei Technologies Co., Ltd. | Ultra-low working voltage rail-to-rail operational amplifier, and differential input amplification-stage circuit and output-stage circuit thereof |
| CN107154786A (en) * | 2017-04-11 | 2017-09-12 | 东南大学 | A kind of rail-to-rail operation transconductance amplifier of low-voltage |
| CN107508567A (en) * | 2017-08-29 | 2017-12-22 | 南京邮电大学南通研究院有限公司 | A kind of constant rail-to-rail difference amplifier of low-voltage mutual conductance |
| CN107508567B (en) * | 2017-08-29 | 2019-06-04 | 南京邮电大学南通研究院有限公司 | A kind of constant rail-to-rail difference amplifier of low-voltage mutual conductance |
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