CN103036516B - Low supply voltage high cmrr operational amplifier - Google Patents
Low supply voltage high cmrr operational amplifier Download PDFInfo
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- CN103036516B CN103036516B CN201210591649.6A CN201210591649A CN103036516B CN 103036516 B CN103036516 B CN 103036516B CN 201210591649 A CN201210591649 A CN 201210591649A CN 103036516 B CN103036516 B CN 103036516B
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- mos transistor
- type mos
- drain electrode
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- transconductance stage
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Abstract
The invention discloses high cmrr operational amplifier under a kind of low supply voltage, this operational amplifier comprises main transconductance stage circuit, from transconductance stage circuit, first order load circuit and second level amplifying circuit; Wherein, main transconductance stage circuit comprises the 5th P type MOS transistor, the 6th P type MOS transistor, the 7th P type MOS transistor, the 4th N-type MOS transistor and the 5th N-type MOS transistor; The 2nd P type MOS transistor, the 3rd P type MOS transistor, the 4th P type MOS transistor, the second N-type MOS transistor and the 3rd N-type MOS transistor is comprised from transconductance stage circuit; Second level amplifying circuit comprises a P type MOS transistor, the first N-type MOS transistor, the first electric capacity and the first resistance.The operational amplifier of this structure can ensure the characteristic of high cmrr and high PSRR at low supply voltages.
Description
Technical field
The present invention relates to a kind of operational amplifier, this operational amplifier has high cmrr and high PSRR characteristic, can (as 0.6V) reliably working at low supply voltages.
Background technology
Operational amplifier is a critical function module of many analogue systems and mixed-signal system, and a large amount of operational amplifiers with differing complexity is used to realize various function: amplify or filtering from the generation of direct current biasing to high speed.Along with every generation CMOS technology, due to the reduction of supply voltage, the design for operational amplifier constantly proposes complicated problem.In recent years, silicon solar cell is more and more applied in Circuits System, and monolithic silicon solar cell only provides 0.6 volt of supply voltage, designs the analog circuit that can work under 0.6V supply voltage and will expand silicon solar cell power supply circuits systematic difference.As the important module of analog circuit, the realization of operational amplifier is a key technology.Because under current mainstream CMOS processes, transistor threshold voltage is greater than 350mV usually, under this supply voltage, be therefore difficult to the transistor of stacked more than three.In traditional operational amplifier configuration, input common mode inhibition is realized by the constant-current characteristics of tail current source, and the voltage margin under 0.6V supply voltage does not allow the use of the tail current source being operated in saturation region.If tail current source transistor is biased in linear zone, make tail current non-constant, output impedance reduces greatly, thus has a strong impact on common-mode rejection ratio and the Power Supply Rejection Ratio of operational amplifier.So design the operational amplifier with high cmrr and high PSRR at low supply voltages to face many challenges.
Summary of the invention
Goal of the invention: for above-mentioned prior art Problems existing and deficiency, the object of this invention is to provide a kind of low supply voltage high cmrr operational amplifier, this amplifier can work under low supply voltage (0.6 volt) environment, has the feature of high cmrr and high PSRR simultaneously.
Technical scheme: for achieving the above object, the technical solution used in the present invention is a kind of low supply voltage high cmrr operational amplifier, and this operational amplifier comprises main transconductance stage circuit, from transconductance stage circuit, first order load and second level amplifying circuit; Wherein, main transconductance stage circuit comprises the 5th P type MOS transistor, the 6th P type MOS transistor, the 7th P type MOS transistor, the 4th N-type MOS transistor and the 5th N-type MOS transistor; The 2nd P type MOS transistor, the 3rd P type MOS transistor and the 4th P type MOS transistor is comprised from transconductance stage circuit; First order load comprises the second N-type MOS transistor and the 3rd N-type MOS transistor; From 2 times that the breadth length ratio of the 2nd P type MOS transistor transconductance stage circuit, the 3rd P type MOS transistor and the 4th P type MOS transistor is the 5th P type MOS transistor in main transconductance stage circuit, the 6th P type MOS transistor and the 7th P type MOS transistor breadth length ratio respectively; Second N-type MOS transistor of first order load is identical with the breadth length ratio of the 4th N-type MOS transistor with the 3rd N-type MOS transistor; Second level amplifying circuit comprises a P type MOS transistor, the first N-type MOS transistor, the first electric capacity and the first resistance;
The grid of the 3rd P type MOS transistor is connected the one end as Differential Input with the grid of the 7th P type MOS transistor, the grid of the 4th P type MOS transistor is connected the other end as Differential Input with the grid of the 6th P type MOS transistor, the source electrode of the 3rd P type MOS transistor, the source electrode of the 4th P type MOS transistor is connected with the drain electrode of the 2nd P type MOS transistor, the drain electrode of the 4th P type MOS transistor is connected with the drain and gate of the 3rd N-type MOS transistor, the grid of the second N-type MOS transistor is connected with drain electrode with the grid of the 3rd N-type MOS transistor, the source electrode of the 6th P type MOS transistor, the source electrode of the 7th P type MOS transistor is connected with the drain electrode of the 5th P type MOS transistor, the drain electrode of the 6th P type MOS transistor, the drain electrode of the 7th P type MOS transistor is connected with the drain electrode of the 4th N-type MOS transistor, the grid of the 2nd P type MOS transistor, the grid of the 5th P type MOS transistor, the drain electrode of the 6th P type MOS transistor, the drain electrode of the 7th P type MOS transistor is connected with the drain electrode of the 4th N-type MOS transistor, the grid of the 4th N-type MOS transistor is connected with drain electrode with the grid of the 5th N-type MOS transistor, the drain electrode of the 5th N-type MOS transistor is connected with reference current, the drain electrode of the 3rd P type MOS transistor, the drain electrode of the second N-type MOS transistor, the grid of the one P type MOS transistor is connected with one end of the first resistance, the other end of the first resistance is connected with the anode of the first electric capacity, the negative terminal of the first electric capacity and the drain electrode of a P type MOS transistor, the drain electrode of the first N-type MOS transistor is connected with output, the source electrode of the one P type MOS transistor, the source electrode of the 2nd P type MOS transistor, the source electrode of the 5th P type MOS transistor is connected with power line, the source electrode of the first N-type MOS transistor, the source electrode of the second N-type MOS transistor, the source electrode of the 3rd N-type MOS transistor, the source electrode of the 4th N-type MOS transistor, the source electrode of the 5th N-type MOS transistor is connected with ground wire.
Beneficial effect: compared with conventional operational amplifiers, the present invention has following beneficial effect: this operational amplifier achieves with simple structure and normally works at low supply voltages, and can realize high cmrr and high PSRR, properties is good.
Accompanying drawing explanation
Fig. 1 is operation amplifier circuit figure of the present invention;
Fig. 2 is operational amplifier common mode rejection ratio simulation result figure of the present invention;
Fig. 3 is operational amplifier Power Supply Rejection Ratio simulation result figure of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, illustrate the present invention further, these embodiments should be understood only be not used in for illustration of the present invention and limit the scope of the invention, after having read the present invention, the amendment of those skilled in the art to the various equivalent form of value of the present invention has all fallen within the application's claims limited range.
The present invention proposes a kind of low supply voltage high cmrr operational amplifier, the tail current source of this operational amplifier is biased in linear zone, employ one and form host-guest architecture with the proportional transconductance stage that copies of the transconductance stage in amplifier and amplifier transconductance stage, the grid of main transconductance stage tail current source, the grid of Differential Input pipe respectively with being connected from transconductance stage corresponding ports in amplifier.Ignore the channel modulation effect of mutual conductance pipe, under the fluctuation of input voltage or supply voltage, main transconductance stage tail current source drain voltage and being consistent from transconductance stage, therefore copied tracking from transconductance stage current source drain voltage by main transconductance stage.And the negative-feedback circuit in main transconductance stage circuit, be operated in the tail current source grid voltage of linear zone by dynamic conditioning, the electric current summation ensureing to flow through mutual conductance pipe equals the current source loads electric current of main transconductance stage.And then can ensure, from the electric current of transconductance stage and constant, to reach the inhibit feature to common mode input and mains fluctuations.The second level of amplifier then adopts common current source load common source structure for amplifying.
The present invention is based on host-guest architecture, structure is simple, can realize under standard CMOS process; Enrich the circuit structure form under low supply voltage (0.6 volt) environment, expand the range of application of 0.6 volt of supply voltage circuit.
As shown in Figure 1, the invention provides the implementation method of high cmrr operational amplifier under a kind of low supply voltage, use standard CMOS process to realize, make this operational amplifier have simple for structure, common-mode rejection ratio is high, Power Supply Rejection Ratio is high and the advantage such as applicable low supply voltage application.The tail current source of this operational amplifier is biased in linear zone, employ one and form host-guest architecture with the proportional transconductance stage that copies of the transconductance stage in amplifier and amplifier transconductance stage, the grid of main transconductance stage tail current source, the grid of Differential Input pipe respectively with being connected from transconductance stage corresponding ports in amplifier.Ignore the channel modulation effect of mutual conductance pipe, under the fluctuation of input voltage or supply voltage, main transconductance stage tail current source drain voltage and being consistent from transconductance stage, therefore copied tracking from transconductance stage current source drain voltage by main transconductance stage.And the negative-feedback circuit in main transconductance stage circuit, be operated in the tail current source grid voltage of linear zone by dynamic conditioning, the electric current summation ensureing to flow through mutual conductance pipe equals the current source loads electric current of main transconductance stage.And then can ensure, from the electric current of transconductance stage and constant, to reach the inhibit feature to common mode input and mains fluctuations.The second level of amplifier then adopts common current source load common source structure for amplifying.
The present invention comprises main transconductance stage circuit (being called for short " primary circuit "), from transconductance stage circuit (being called for short " from level circuit "), first order load and second level amplifying circuit; Wherein, primary circuit comprises the 5th P type MOS transistor P
5, the 6th P type MOS transistor P
6, the 7th P type MOS transistor P
7, the 4th N-type MOS transistor N
4with the 5th N-type MOS transistor N
5; The 2nd P type MOS transistor P is comprised from level circuit
2, the 3rd P type MOS transistor P
3with the 4th P type MOS transistor P
4; First order load comprises the second N-type MOS transistor N
2with the 3rd N-type MOS transistor N
3; From the 2nd P type MOS transistor P level circuit
2, the 3rd P type MOS transistor P
3with the 4th P type MOS transistor P
4breadth length ratio be the 5th P type MOS transistor P in primary circuit respectively
5, the 6th P type MOS transistor P
6with the 7th P type MOS transistor P
72 times of breadth length ratio.Second N-type MOS transistor N
2, the 3rd N-type MOS transistor N
3with the 4th N-type MOS transistor N
4breadth length ratio identical; Second level amplifying circuit comprises a P type MOS transistor P
1, the first N-type MOS transistor N
1, the first electric capacity C1 and the first resistance R
1.
3rd P type MOS transistor P
3grid and the 7th P type MOS transistor P
7grid connect as one end INP of Differential Input, the 4th P type MOS transistor P
4grid and the 6th P type MOS transistor P
6grid connect as the other end INN of Differential Input, the 3rd P type MOS transistor P
3source electrode, the 4th P type MOS transistor P
4source electrode and the 2nd P type MOS transistor P
2drain electrode connect, the 3rd P type MOS transistor P
3drain electrode and the second N-type MOS transistor N
2drain electrode connect, the 4th P type MOS transistor P
4drain electrode and the 3rd N-type MOS transistor N
3drain and gate connect, the second N-type MOS transistor N
2grid and the 3rd N-type MOS transistor N
3grid with drain electrode be connected, the 6th P type MOS transistor P
6source electrode, the 7th P type MOS transistor P
7source electrode and the 5th P type MOS transistor P
5drain electrode connect, the 6th P type MOS transistor P
6drain electrode, the 7th P type MOS transistor P
7drain electrode and the 4th N-type MOS transistor N
4drain electrode connect, the 2nd P type MOS transistor P
2grid, the 5th P type MOS transistor P
5grid, the 6th P type MOS transistor P
6drain electrode, the 7th P type MOS transistor P
7drain electrode and the 4th N-type MOS transistor N
4drain electrode connect, the 4th N-type MOS transistor N
4grid and the 5th N-type MOS transistor N
5grid with drain electrode be connected, the 5th N-type MOS transistor N
5drain electrode be connected with reference current (IBIN), the 3rd P type MOS transistor P
3drain electrode, the second N-type MOS transistor N
2drain electrode, a P type MOS transistor P
1grid and the first resistance R
1one end connect, the first resistance R
1the other end and the first electric capacity C
1anode connect, the first electric capacity C
1negative terminal and a P type MOS transistor P
1drain electrode, the first N-type MOS transistor N
1drain electrode be connected with output OUT, a P type MOS transistor P
1source electrode, the 2nd P type MOS transistor P
2source electrode, the 5th P type MOS transistor P
5source electrode be connected with power line, the first N-type MOS transistor N
1source electrode, the second N-type MOS transistor N
2source electrode, the 3rd N-type MOS transistor N
3source electrode, the 4th N-type MOS transistor N
4source electrode, the 5th N-type MOS transistor N
5source electrode be connected with ground wire.
Above-mentioned operational amplifier, normally can work, and have high cmrr and high PSRR under low supply voltage (0.6 volt).And in traditional operational amplifier, in order to improve the linearity of operational amplifier, common-mode rejection ratio and Power Supply Rejection Ratio, Differential Input pipe, load pipe and tail current source transistor all need to be operated in saturation region, supply voltage equals the drain-source pressure drop sum of this three quasi-metal oxides transistor, limit by existing CMOS technology, the operational amplifier of this structure is difficult to normally work under low supply voltage (0.6 volt).
In order to enable operational amplifier work under low supply voltage (0.6 volt), in the present invention, allow Differential Input pipe the 3rd P type MOS transistor P
3with the 4th P type MOS transistor P
4be operated in sub-threshold region, now MOS transistor gate source voltage is less than the cut-in voltage of MOS transistor, the MOS transistor leakage current and the gate source voltage that are operated in sub-threshold region present exponential relationship, and the change of grid voltage can control the change of drain current.Because now gate source voltage is very little, make the drain-source saturation voltage drop of MOS transistor can be very low, this reduces the supply voltage required for operational amplifier.In order to reduce supply voltage further, the present invention allows tail current source the 2nd P type MOS transistor P
2be operated in linear zone, but be operated in the 2nd P type MOS transistor P of linear zone
2leakage current affects very large by drain voltage, this will have a strong impact on common-mode rejection ratio and the Power Supply Rejection Ratio of operational amplifier.In order to improve common-mode rejection ratio and the Power Supply Rejection Ratio of low supply voltage operational amplifier, the present invention adds by the 5th P type MOS transistor P in conventional operational amplifiers
5, the 6th P type MOS transistor P
6, the 7th P type MOS transistor P
7, the 4th N-type MOS transistor N
4with the 5th N-type MOS transistor N
5the primary circuit of composition.Because the second N-type MOS transistor N
2, the 3rd N-type MOS transistor N
3, the 4th N-type MOS transistor N
4breadth length ratio identical, under identical CMOS technology, the 5th P type MOS transistor P in primary circuit
5, the 6th P type MOS transistor P
6, the 7th P type MOS transistor P
7leakage current be the 2nd P type MOS transistor P from level circuit respectively
2, the 3rd P type MOS transistor P
3, the 4th P type MOS transistor P
4the half of leakage current, again because in primary circuit, the breadth length ratio of P type MOS transistor is the half of P type MOS transistor breadth length ratio from level circuit, at the 5th P type MOS transistor P
5with the 2nd P type MOS transistor P
2the 5th P type MOS transistor P is just made when gate source voltage is identical
5with the 2nd P type MOS transistor P
2drain voltage identical, and then the 6th P type MOS transistor P
6, the 7th P type MOS transistor P
7, the 3rd P type MOS transistor P
3, the 4th P type MOS transistor P
4drain-source voltage is identical with gate source voltage.5th P type MOS transistor P
5leakage current and the 4th N-type MOS transistor N
4leakage current is equal, and the 2nd P type MOS transistor P
2leakage current follows the trail of the 5th P type MOS transistor P
5leakage current.So just achieve the 2nd P type MOS transistor P
2leakage current does not change with its drain voltage, and then overcomes conventional operational amplifiers common-mode rejection ratio and the low shortcoming of Power Supply Rejection Ratio at low supply voltages, achieves high cmrr and the high PSRR of low supply voltage operational amplifier.
Figure 2 shows that the simulation result of operational amplifier common mode rejection ratio of the present invention, solid line is the common-mode rejection ratio simulation curve being operated in low supply voltage operational amplifier under 0.6V, dotted line is under being operated in 1.2V voltage, adopt the common-mode rejection ratio simulation curve of the conventional operational amplifiers of saturation region tail current source, as can be seen from the figure, in the present invention, the low-frequency range common-mode rejection ratio of operational amplifier can reach-74dB, higher than-the 45dB of traditional structure amplifier.
Figure 3 shows that the simulation result of operational amplifier Power Supply Rejection Ratio of the present invention, solid line is the Power Supply Rejection Ratio simulation curve being operated in low supply voltage operational amplifier under 0.6V, dotted line is under being operated in 1.2V voltage, adopt the Power Supply Rejection Ratio simulation curve of the conventional operational amplifiers of saturation region tail current source, as can be seen from the figure, the low-frequency range Power Supply Rejection Ratio of this operational amplifier can reach-47dB, higher than-the 45dB of traditional structure amplifier.
Operational amplifier of the present invention, main transconductance stage is of a size of the half from transconductance stage, and principal and subordinate's transconductance stage tail current source transistor is all operated in dark linear zone, to adapt to the requirement of low supply voltage; Main transconductance stage is responsible for following the tracks of and is changed as the tail current from transconductance stage, and automatically adjusts the grid voltage of tail current transistor by feedback loop, thus realizes the constant object of principal and subordinate's transconductance stage tail current, and then realizes high cmrr and Power Supply Rejection Ratio.
Claims (1)
1. a low supply voltage high cmrr operational amplifier, is characterized in that: this operational amplifier comprises main transconductance stage circuit, from transconductance stage circuit, first order load and second level amplifying circuit; Wherein, main transconductance stage circuit comprises the 5th P type MOS transistor (P
5), the 6th P type MOS transistor (P
6), the 7th P type MOS transistor (P
7), the 4th N-type MOS transistor (N
4) and the 5th N-type MOS transistor (N
5); The 2nd P type MOS transistor (P is comprised from transconductance stage circuit
2), the 3rd P type MOS transistor (P
3) and the 4th P type MOS transistor (P
4); First order load comprises the second N-type MOS transistor (N
2) and the 3rd N-type MOS transistor (N
3); From the 2nd P type MOS transistor (P transconductance stage circuit
2), the 3rd P type MOS transistor (P
3) and the 4th P type MOS transistor (P
4) breadth length ratio be the 5th P type MOS transistor (P in main transconductance stage circuit respectively
5), the 6th P type MOS transistor (P
6) and the 7th P type MOS transistor (P
7) 2 times of breadth length ratio; Second N-type MOS transistor (N of first order load
2) and the 3rd N-type MOS transistor (N
3) and the 4th N-type MOS transistor (N
4) breadth length ratio identical; Second level amplifying circuit comprises a P type MOS transistor (P
1), the first N-type MOS transistor (N
1), the first electric capacity (C
1) and the first resistance (R
1);
3rd P type MOS transistor (P
3) grid and the 7th P type MOS transistor (P
7) grid connect as one end (INP) of Differential Input, the 4th P type MOS transistor (P
4) grid and the 6th P type MOS transistor (P
6) grid connect as the other end (INN) of Differential Input, the 3rd P type MOS transistor (P
3) source electrode, the 4th P type MOS transistor (P
4) source electrode and the 2nd P type MOS transistor (P
2) drain electrode connect, the 4th P type MOS transistor (P
4) drain electrode and the 3rd N-type MOS transistor (N
3) drain and gate connect, the second N-type MOS transistor (N
2) grid and the 3rd N-type MOS transistor (N
3) grid with drain electrode be connected, the 6th P type MOS transistor (P
6) source electrode, the 7th P type MOS transistor (P
7) source electrode and the 5th P type MOS transistor (P
5) drain electrode connect, the 6th P type MOS transistor (P
6) drain electrode, the 7th P type MOS transistor (P
7) drain electrode and the 4th N-type MOS transistor (N
4) drain electrode connect, the 2nd P type MOS transistor (P
2) grid, the 5th P type MOS transistor (P
5) grid, the 6th P type MOS transistor (P
6) drain electrode, the 7th P type MOS transistor (P
7) drain electrode and the 4th N-type MOS transistor (N
4) drain electrode connect, the 4th N-type MOS transistor (N
4) grid and the 5th N-type MOS transistor (N
5) grid with drain electrode be connected, the 5th N-type MOS transistor (N
5) drain electrode be connected with reference current; 3rd P type MOS transistor (P
3) drain electrode, the second N-type MOS transistor (N
2) drain electrode, a P type MOS transistor (P
1) grid and the first resistance (R
1) one end connect, the first resistance (R
1) the other end and the first electric capacity (C
1) anode connect, the first electric capacity (C
1) negative terminal and a P type MOS transistor (P
1) drain electrode, the first N-type MOS transistor (N
1) drain electrode be connected with output (OUT), a P type MOS transistor (P
1) source electrode, the 2nd P type MOS transistor (P
2) source electrode, the 5th P type MOS transistor (P
5) source electrode be connected with power line, the first N-type MOS transistor (N
1) source electrode, the second N-type MOS transistor (N
2) source electrode, the 3rd N-type MOS transistor (N
3) source electrode, the 4th N-type MOS transistor (N
4) source electrode, the 5th N-type MOS transistor (N
5) source electrode be connected with ground wire.
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| CN201210591649.6A CN103036516B (en) | 2012-12-31 | 2012-12-31 | Low supply voltage high cmrr operational amplifier |
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| CN103036516B true CN103036516B (en) | 2015-09-16 |
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| CN103414441B (en) * | 2013-08-21 | 2016-04-13 | 中国电子科技集团公司第二十四研究所 | The Open-loop amplifier of output common mode voltage stabilization |
| CN106385239B (en) * | 2016-09-09 | 2019-04-16 | 中国计量大学 | A kind of CMOS wideband low noise amplifier of adjustable gain |
| CN107154786A (en) * | 2017-04-11 | 2017-09-12 | 东南大学 | A kind of rail-to-rail operation transconductance amplifier of low-voltage |
| CN107508567B (en) * | 2017-08-29 | 2019-06-04 | 南京邮电大学南通研究院有限公司 | A kind of constant rail-to-rail difference amplifier of low-voltage mutual conductance |
| US10511275B2 (en) * | 2018-01-16 | 2019-12-17 | Microchip Technology Incorporated | Common mode sensing architecture |
| CN108919874B (en) * | 2018-08-30 | 2023-07-11 | 北京神经元网络技术有限公司 | Low-dropout linear voltage regulator |
| CN110166009B (en) * | 2019-04-30 | 2022-05-13 | 思瑞浦微电子科技（苏州）股份有限公司 | Input voltage-withstanding protection framework |
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| CN101958692A (en) * | 2010-10-19 | 2011-01-26 | 杭州电子科技大学 | Low-pressure rail-to-rail calculation magnification circuit |
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| CN101958692A (en) * | 2010-10-19 | 2011-01-26 | 杭州电子科技大学 | Low-pressure rail-to-rail calculation magnification circuit |
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Effective date of registration: 20170203 Address after: 99 No. 214135 Jiangsu province Wuxi city Wuxi District Linghu Avenue Patentee after: Southeast University Wuxi branch Address before: 99 No. 214135 Jiangsu province Wuxi city Wuxi District Linghu Avenue Patentee before: Southeast University |
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