CN103036516A - Operational amplifier with low supply voltage and high common-mode rejection ratio - Google Patents

Operational amplifier with low supply voltage and high common-mode rejection ratio Download PDF

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Publication number
CN103036516A
CN103036516A CN2012105916496A CN201210591649A CN103036516A CN 103036516 A CN103036516 A CN 103036516A CN 2012105916496 A CN2012105916496 A CN 2012105916496A CN 201210591649 A CN201210591649 A CN 201210591649A CN 103036516 A CN103036516 A CN 103036516A
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China
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mos transistor
type mos
drain electrode
grid
source electrode
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CN2012105916496A
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Chinese (zh)
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CN103036516B (en
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陈超
吴建辉
赵超
李红
黄成�
田茜
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东南大学
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Abstract

The invention discloses an operational amplifier with low supply voltage and high common-mode rejection ratio. The operational amplifier comprises a main transconductance level circuit, a secondary transconductance level circuit, a first-level load circuit and a second-level amplification circuit, wherein the main transconductance level circuit comprises a fifth P-type metal oxide transistor, a sixth P-type metal oxide transistor, a seventh P-type metal oxide transistor, a fourth N-type metal oxide transistor and a fifth N-type metal oxide transistor; the secondary transconductance level circuit comprises a second P-type metal oxide transistor, a third P-type metal oxide transistor, a fourth P-type metal oxide transistor, a second N-type metal oxide transistor and a third N-type metal oxide transistor; and the second-level amplification circuit comprises a first P-type metal oxide transistor, a first N-type metal oxide transistor, a first capacitor and a first resistor. The operational amplifier disclosed by the invention can ensure the characteristics of high common-mode rejection ratio and high power supply rejection ratio under low supply voltage.

Description

Low supply voltage high cmrr operational amplifier
Technical field
The present invention relates to a kind of operational amplifier, this operational amplifier has high cmrr and high PSRR characteristic, can be under low supply voltage (such as 0.6V) reliably working.
Background technology
Operational amplifier is a critical function module of many analogue systems and mixed-signal system, and a large amount of operational amplifiers with differing complexity is used to realize various functions: amplify or filtering to high speed from the generation of direct current biasing.Be accompanied by every generation CMOS technique, because reducing of supply voltage constantly proposes the problem of complexity for the design of operational amplifier.In recent years, silicon solar cell more and more is applied in the Circuits System, and the monolithic silicon solar cell only provides 0.6 volt of supply voltage, the application that the analog circuit that design can be worked under the 0.6V supply voltage will be expanded silicon solar cell power supply circuits system.As the important module of analog circuit, the realization of operational amplifier is a key technology.Because therefore transistor threshold voltage is being difficult to stacked transistor more than three usually greater than 350mV under the main stream of CMOS technique under this supply voltage at present.In traditional operational amplifier structure, the input common mode inhibition is that the constant-current characteristics by tail current source realizes, and the voltage margin under the 0.6V supply voltage does not allow to be operated in the use of the tail current source of saturation region.If tail current source transistor is biased in linear zone, so that tail current is non-constant, output impedance reduces greatly, thereby has a strong impact on common-mode rejection ratio and the Power Supply Rejection Ratio of operational amplifier.Face many challenges so under low supply voltage, design the operational amplifier with high cmrr and high PSRR.
Summary of the invention
Goal of the invention: for the problem and shortage of above-mentioned prior art existence, the purpose of this invention is to provide a kind of low supply voltage high cmrr operational amplifier, this amplifier can be worked under low supply voltage (0.6 volt) environment, has simultaneously the characteristics of high cmrr and high PSRR.
Technical scheme: for achieving the above object, the technical solution used in the present invention is a kind of low supply voltage high cmrr operational amplifier, and this operational amplifier comprises main transconductance stage circuit, from transconductance stage circuit, first order load and second level amplifying circuit; Wherein, main transconductance stage circuit comprises the 5th P type MOS transistor, the 6th P type MOS transistor, the 7th P type MOS transistor, the 4th N-type MOS transistor and the 5th N-type MOS transistor; Comprise the 2nd P type MOS transistor, the 3rd P type MOS transistor and the 4th P type MOS transistor from transconductance stage circuit; First order load comprises the second N-type MOS transistor and the 3rd N-type MOS transistor; The breadth length ratio of the 2nd P type MOS transistor, the 3rd P type MOS transistor and the 4th P type MOS transistor from transconductance stage circuit is respectively the 5th P type MOS transistor in the main transconductance stage circuit, the 6th P type MOS transistor and the 7th P type MOS transistor breadth length ratio 2 times; The second N-type MOS transistor of first order load is identical with the breadth length ratio of the 4th N-type MOS transistor with the 3rd N-type MOS transistor; Second level amplifying circuit comprises a P type MOS transistor, the first N-type MOS transistor, the first electric capacity and the first resistance;
The grid of the 3rd P type MOS transistor is connected the end as the difference input with the grid of the 7th P type MOS transistor, the grid of the grid of the 4th P type MOS transistor and the 6th P type MOS transistor connects the other end as the difference input, the source electrode of the 3rd P type MOS transistor, the drain electrode of the source electrode of the 4th P type MOS transistor and the 2nd P type MOS transistor connects, the drain and gate of the drain electrode of the 4th P type MOS transistor and the 3rd N-type MOS transistor connects, the grid of the grid of the second N-type MOS transistor and the 3rd N-type MOS transistor and the connection that is connected, the source electrode of the 6th P type MOS transistor, the drain electrode of the source electrode of the 7th P type MOS transistor and the 5th P type MOS transistor connects, the drain electrode of the 6th P type MOS transistor, the drain electrode of the drain electrode of the 7th P type MOS transistor and the 4th N-type MOS transistor connects, the grid of the 2nd P type MOS transistor, the grid of the 5th P type MOS transistor, the drain electrode of the 6th P type MOS transistor, the drain electrode of the drain electrode of the 7th P type MOS transistor and the 4th N-type MOS transistor connects, the grid of the grid of the 4th N-type MOS transistor and the 5th N-type MOS transistor and the connection that is connected, the drain electrode of the 5th N-type MOS transistor is connected with reference current; The drain electrode of the 3rd P type MOS transistor, the drain electrode of the second N-type MOS transistor, the grid of the one P type MOS transistor be connected an end of resistance and connect, the other end of the first resistance be connected the anode of electric capacity and connect, the drain electrode of the negative terminal of the first electric capacity and a P type MOS transistor, the drain electrode of the first N-type MOS transistor is connected with output, the source electrode of the one P type MOS transistor, the source electrode of the 2nd P type MOS transistor, the source electrode of the 5th P type MOS transistor is connected with power line, the source electrode of the first N-type MOS transistor, the source electrode of the second N-type MOS transistor, the source electrode of the 3rd N-type MOS transistor, the source electrode of the 4th N-type MOS transistor, the source electrode of the 5th N-type MOS transistor is connected with ground wire.
Beneficial effect: compare with the conventional operation amplifier, the present invention has following beneficial effect: this operational amplifier has been realized working under low supply voltage with simple structure, and can realize high cmrr and high PSRR, properties is good.
Description of drawings
Fig. 1 is operation amplifier circuit figure of the present invention;
Fig. 2 is operational amplifier common-mode rejection ratio simulation result figure of the present invention;
Fig. 3 is operational amplifier Power Supply Rejection Ratio simulation result figure of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, further illustrate the present invention, should understand these embodiment only is used for explanation the present invention and is not used in and limits the scope of the invention, after having read the present invention, those skilled in the art all fall within the application's claims limited range to the modification of the various equivalent form of values of the present invention.
The present invention proposes a kind of low supply voltage high cmrr operational amplifier, the tail current source of this operational amplifier is biased in linear zone, used one with amplifier in the transconductance stage proportional transconductance stage that copies and amplifier transconductance stage consist of host-guest architecture, the grid of the grid of main transconductance stage tail current source, difference input pipe respectively with amplifier in link to each other from the transconductance stage corresponding ports.The channel modulation effect of ignoring the mutual conductance pipe, under the fluctuation of input voltage or supply voltage, main transconductance stage tail current source drain voltage with from being consistent of transconductance stage, therefore led level replication from transconductance stage current source drain voltage by main span and follow the tracks of.And the negative-feedback circuit in the main transconductance stage circuit is operated in the tail current source grid voltage of linear zone by dynamic adjustment, and the electric current summation that guarantees to flow through the mutual conductance pipe equals the current source loads electric current of main transconductance stage.And then can guarantee to reach the inhibit feature to common mode input and mains fluctuations from the electric current of transconductance stage and constant.Common current source load common source structure for amplifying is then adopted in the second level of amplifier.
The present invention is based on host-guest architecture, simple in structure, can realize under the standard CMOS process; Enrich the circuit structure form under low supply voltage (0.6 volt) environment, expanded the range of application of 0.6 volt of supply voltage circuit.
As shown in Figure 1, the invention provides the implementation method of high cmrr operational amplifier under a kind of low supply voltage, Application standard CMOS technique can realize, so that this operational amplifier has is simple for structure, common-mode rejection ratio is high, Power Supply Rejection Ratio is high and the advantage such as suitable low supply voltage application.The tail current source of this operational amplifier is biased in linear zone, used one with amplifier in the transconductance stage proportional transconductance stage that copies and amplifier transconductance stage consist of host-guest architecture, the grid of the grid of main transconductance stage tail current source, difference input pipe respectively with amplifier in link to each other from the transconductance stage corresponding ports.The channel modulation effect of ignoring the mutual conductance pipe, under the fluctuation of input voltage or supply voltage, main transconductance stage tail current source drain voltage with from being consistent of transconductance stage, therefore led level replication from transconductance stage current source drain voltage by main span and follow the tracks of.And the negative-feedback circuit in the main transconductance stage circuit is operated in the tail current source grid voltage of linear zone by dynamic adjustment, and the electric current summation that guarantees to flow through the mutual conductance pipe equals the current source loads electric current of main transconductance stage.And then can guarantee to reach the inhibit feature to common mode input and mains fluctuations from the electric current of transconductance stage and constant.Common current source load common source structure for amplifying is then adopted in the second level of amplifier.
The present invention comprises main transconductance stage circuit (be called for short " primary circuit "), from transconductance stage circuit (being called for short " from the level circuit "), first order load and second level amplifying circuit; Wherein, primary circuit comprises the 5th P type MOS transistor P 5, the 6th P type MOS transistor P 6, the 7th P type MOS transistor P 7, the 4th N-type MOS transistor N 4With the 5th N-type MOS transistor N 5Comprise the 2nd P type MOS transistor P from the level circuit 2, the 3rd P type MOS transistor P 3With the 4th P type MOS transistor P 4First order load comprises the second N-type MOS transistor N 2With the 3rd N-type MOS transistor N 3The 2nd P type MOS transistor P from the level circuit 2, the 3rd P type MOS transistor P 3With the 4th P type MOS transistor P 4Breadth length ratio be respectively the 5th P type MOS transistor P in the primary circuit 5, the 6th P type MOS transistor P 6With the 7th P type MOS transistor P 72 times of breadth length ratio.The second N-type MOS transistor N 2, the 3rd N-type MOS transistor N 3With the 4th N-type MOS transistor N 4Breadth length ratio identical; Second level amplifying circuit comprises a P type MOS transistor P 1, the first N-type MOS transistor N 1, the first capacitor C 1 and the first resistance R 1
The 3rd P type MOS transistor P 3Grid and the 7th P type MOS transistor P 7Grid connect an end INP as the difference input, the 4th P type MOS transistor P 4Grid and the 6th P type MOS transistor P 6Grid connect other end INN as the difference input, the 3rd P type MOS transistor P 3Source electrode, the 4th P type MOS transistor P 4Source electrode and the 2nd P type MOS transistor P 2Drain electrode connect the 3rd P type MOS transistor P 3Drain electrode and the second N-type MOS transistor N 2Drain electrode connect the 4th P type MOS transistor P 4Drain electrode and the 3rd N-type MOS transistor N 3Drain and gate connect the second N-type MOS transistor N 2Grid and the 3rd N-type MOS transistor N 3Grid and the connection that is connected, the 6th P type MOS transistor P 6Source electrode, the 7th P type MOS transistor P 7Source electrode and the 5th P type MOS transistor P 5Drain electrode connect the 6th P type MOS transistor P 6Drain electrode, the 7th P type MOS transistor P 7Drain electrode and the 4th N-type MOS transistor N 4Drain electrode connect the 2nd P type MOS transistor P 2Grid, the 5th P type MOS transistor P 5Grid, the 6th P type MOS transistor P 6Drain electrode, the 7th P type MOS transistor P 7Drain electrode and the 4th N-type MOS transistor N 4Drain electrode connect the 4th N-type MOS transistor N 4Grid and the 5th N-type MOS transistor N 5Grid and the connection that is connected, the 5th N-type MOS transistor N 5Drain electrode be connected IBIN with reference current) connect the 3rd P type MOS transistor P 3Drain electrode, the second N-type MOS transistor N 2Drain electrode, a P type MOS transistor P 1Grid and the first resistance R 1An end connect the first resistance R 1The other end and the first capacitor C 1Anode connect the first capacitor C 1Negative terminal and a P type MOS transistor P 1Drain electrode, the first N-type MOS transistor N 1Drain electrode be connected a P type MOS transistor P with output OUT 1Source electrode, the 2nd P type MOS transistor P 2Source electrode, the 5th P type MOS transistor P 5Source electrode be connected the first N-type MOS transistor N with power line 1Source electrode, the second N-type MOS transistor N 2Source electrode, the 3rd N-type MOS transistor N 3Source electrode, the 4th N-type MOS transistor N 4Source electrode, the 5th N-type MOS transistor N 5Source electrode be connected with ground wire.
Above-mentioned operational amplifier can work under low supply voltage (0.6 volt), and have high cmrr and high PSRR.And in traditional operational amplifier, for the linearity, common-mode rejection ratio and the Power Supply Rejection Ratio that improves operational amplifier, difference input pipe, load pipe and tail current source transistor all need be operated in the saturation region, supply voltage equals the transistorized drain-source pressure drop of this three quasi-metal oxides sum, be subjected to existing CMOS process technology limit, the operational amplifier of this structure is difficult in the lower normal operation of low supply voltage (0.6 volt).
In order to make the operational amplifier can be in the lower work of low supply voltage (0.6 volt), allow difference input pipe the 3rd P type MOS transistor P among the present invention 3With the 4th P type MOS transistor P 4Be operated in sub-threshold region, the MOS transistor gate source voltage is less than the cut-in voltage of MOS transistor at this moment, the MOS transistor leakage current and the gate source voltage that are operated in sub-threshold region present exponential relationship, and the variation of grid voltage can be controlled the variation of drain current.Because this moment, gate source voltage was very little, so that the drain-source saturation voltage drop of MOS transistor can be very low, this has just reduced the needed supply voltage of operational amplifier.In order further to reduce supply voltage, the present invention allows tail current source the 2nd P type MOS transistor P 2Be operated in linear zone, but be operated in the 2nd P type MOS transistor P of linear zone 2It is very large that leakage current is affected by drain voltage, and this will have a strong impact on common-mode rejection ratio and the Power Supply Rejection Ratio of operational amplifier.For common-mode rejection ratio and the Power Supply Rejection Ratio of improving the low supply voltage operational amplifier, the present invention adds in the conventional operation amplifier by the 5th P type MOS transistor P 5, the 6th P type MOS transistor P 6, the 7th P type MOS transistor P 7, the 4th N-type MOS transistor N 4With the 5th N-type MOS transistor N 5The primary circuit that forms.Because the second N-type MOS transistor N 2, the 3rd N-type MOS transistor N 3, the 4th N-type MOS transistor N 4Breadth length ratio identical, under identical CMOS technique, the 5th P type MOS transistor P in the primary circuit 5, the 6th P type MOS transistor P 6, the 7th P type MOS transistor P 7Leakage current be respectively the 2nd P type MOS transistor P from the level circuit 2, the 3rd P type MOS transistor P 3, the 4th P type MOS transistor P 4Half of leakage current is again because the breadth length ratio of P type MOS transistor is half of P type MOS transistor breadth length ratio from the level circuit in the primary circuit, at the 5th P type MOS transistor P 5With the 2nd P type MOS transistor P 2In the identical situation of gate source voltage just so that the 5th P type MOS transistor P 5With the 2nd P type MOS transistor P 2Drain voltage identical, and then the 6th P type MOS transistor P 5, the 7th P type MOS transistor P 7, the 3rd P type MOS transistor P 3, the 4th P type MOS transistor P 4Drain-source voltage is identical with gate source voltage.The 5th P type MOS transistor P 5Leakage current and the 4th N-type MOS transistor N 4Leakage current equates, and the 2nd P type MOS transistor P 2Leakage current is followed the trail of the 5th P type MOS transistor P 5Leakage current.So just realized the 2nd P type MOS transistor P 2Leakage current does not change with its drain voltage, and then overcomes conventional operation amplifier common-mode rejection ratio and the low shortcoming of Power Supply Rejection Ratio under low supply voltage, has realized high cmrr and the high PSRR of low supply voltage operational amplifier.
Figure 2 shows that the simulation result of operational amplifier common-mode rejection ratio of the present invention, solid line is the common-mode rejection ratio simulation curve that is operated in low supply voltage operational amplifier under the 0.6V, dotted line is to be operated under the 1.2V voltage, adopt the common-mode rejection ratio simulation curve of the conventional operation amplifier of saturation region tail current source, as can be seen from the figure, the low-frequency range common-mode rejection ratio of operational amplifier can reach-74dB among the present invention, be higher than the traditional structure amplifier-45dB.
Figure 3 shows that the simulation result of operational amplifier Power Supply Rejection Ratio of the present invention, solid line is the Power Supply Rejection Ratio simulation curve that is operated in low supply voltage operational amplifier under the 0.6V, dotted line is to be operated under the 1.2V voltage, adopt the Power Supply Rejection Ratio simulation curve of the conventional operation amplifier of saturation region tail current source, as can be seen from the figure, the low-frequency range Power Supply Rejection Ratio of this operational amplifier can reach-47dB, be higher than the traditional structure amplifier-45dB.
Operational amplifier of the present invention, main transconductance stage is of a size of half from transconductance stage, and principal and subordinate's transconductance stage tail current source transistor all is operated in dark linear zone, to adapt to the requirement of low supply voltage; The tail current that main transconductance stage is responsible for following the tracks of as from transconductance stage changes, and automatically adjusts the grid voltage of tail current transistor by feedback loop, thereby realizes the constant purpose of principal and subordinate's transconductance stage tail current, and then realizes high cmrr and Power Supply Rejection Ratio.

Claims (1)

1. low supply voltage high cmrr operational amplifier is characterized in that: this operational amplifier comprises main transconductance stage circuit, from transconductance stage circuit, first order load and second level amplifying circuit; Wherein, main transconductance stage circuit comprises the 5th P type MOS transistor (P 5), the 6th P type MOS transistor (P 6), the 7th P type MOS transistor (P 7), the 4th N-type MOS transistor (N 4) and the 5th N-type MOS transistor (N 5); Comprise the 2nd P type MOS transistor (P from transconductance stage circuit 2), the 3rd P type MOS transistor (P 3) and the 4th P type MOS transistor (P 4); First order load comprises the second N-type MOS transistor (N 2) and the 3rd N-type MOS transistor (N 3); The 2nd P type MOS transistor (P from transconductance stage circuit 2), the 3rd P type MOS transistor (P 3) and the 4th P type MOS transistor (P 4) breadth length ratio be respectively the 5th P type MOS transistor (P in the main transconductance stage circuit 5), the 6th P type MOS transistor (P 6) and the 7th P type MOS transistor (P 7) 2 times of breadth length ratio; The second N-type MOS transistor (N of first order load 2) and the 3rd N-type MOS transistor (N 3) and the 4th N-type MOS transistor (N 4) breadth length ratio identical; Second level amplifying circuit comprises a P type MOS transistor (P 1), the first N-type MOS transistor (N 1), the first electric capacity (C 1) and the first resistance (R 1);
The 3rd P type MOS transistor (P 3) grid and the 7th P type MOS transistor (P 7) grid connect a end (INP) as the difference input, the 4th P type MOS transistor (P 4) grid and the 6th P type MOS transistor (P 6) grid connect the other end (INN) as the difference input, the 3rd P type MOS transistor (P 3) source electrode, the 4th P type MOS transistor (P 4) source electrode and the 2nd P type MOS transistor (P 2) drain electrode connect the 4th P type MOS transistor (P 4) drain electrode and the 3rd N-type MOS transistor (N 3) drain and gate connect the second N-type MOS transistor (N 2) grid and the 3rd N-type MOS transistor (N 3) grid and the connection that is connected, the 6th P type MOS transistor (P 6) source electrode, the 7th P type MOS transistor (P 7) source electrode and the 5th P type MOS transistor (P 5) drain electrode connect the 6th P type MOS transistor (P 6) drain electrode, the 7th P type MOS transistor (P 7) drain electrode and the 4th N-type MOS transistor (N 4) drain electrode connect the 2nd P type MOS transistor (P 2) grid, the 5th P type MOS transistor (P 5) grid, the 6th P type MOS transistor (P 6) drain electrode, the 7th P type MOS transistor (P 7) drain electrode and the 4th N-type MOS transistor (N 4) drain electrode connect the 4th N-type MOS transistor (N 4) grid and the 5th N-type MOS transistor (N 5) grid and the connection that is connected, the 5th N-type MOS transistor (N 5) drain electrode be connected with reference current; The 3rd P type MOS transistor (P 3) drain electrode, the second N-type MOS transistor (N 2) drain electrode, a P type MOS transistor (P 1) grid and the first resistance (R 1) an end connect the first resistance (R 1) the other end and the first electric capacity (C 1) anode connect the first electric capacity (C 1) negative terminal and a P type MOS transistor (P 1) drain electrode, the first N-type MOS transistor (N 1) drain electrode be connected OUT with output) connect a P type MOS transistor (P 1) source electrode, the 2nd P type MOS transistor (P 2) source electrode, the 5th P type MOS transistor (P 5) source electrode be connected the first N-type MOS transistor (N with power line 1) source electrode, the second N-type MOS transistor (N 2) source electrode, the 3rd N-type MOS transistor (N 3) source electrode, the 4th N-type MOS transistor (N 4) source electrode, the 5th N-type MOS transistor (N 5) source electrode be connected with ground wire.
CN201210591649.6A 2012-12-31 2012-12-31 Low supply voltage high cmrr operational amplifier CN103036516B (en)

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CN103414441A (en) * 2013-08-21 2013-11-27 中国电子科技集团公司第二十四研究所 Open loop amplifier with stable output common-mode voltage
CN106385239A (en) * 2016-09-09 2017-02-08 中国计量大学 Gain-adjustable CMOS (Complementary Metal-Oxide-Semiconductor Transistor) broadband low-noise amplifier
CN107154786A (en) * 2017-04-11 2017-09-12 东南大学 A kind of rail-to-rail operation transconductance amplifier of low-voltage
CN107508567A (en) * 2017-08-29 2017-12-22 南京邮电大学南通研究院有限公司 A kind of constant rail-to-rail difference amplifier of low-voltage mutual conductance
CN110166009A (en) * 2019-04-30 2019-08-23 思瑞浦微电子科技(苏州)股份有限公司 A kind of pressure-resistant protection architecture of input

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103414441A (en) * 2013-08-21 2013-11-27 中国电子科技集团公司第二十四研究所 Open loop amplifier with stable output common-mode voltage
CN106385239A (en) * 2016-09-09 2017-02-08 中国计量大学 Gain-adjustable CMOS (Complementary Metal-Oxide-Semiconductor Transistor) broadband low-noise amplifier
CN106385239B (en) * 2016-09-09 2019-04-16 中国计量大学 A kind of CMOS wideband low noise amplifier of adjustable gain
CN107154786A (en) * 2017-04-11 2017-09-12 东南大学 A kind of rail-to-rail operation transconductance amplifier of low-voltage
CN107508567A (en) * 2017-08-29 2017-12-22 南京邮电大学南通研究院有限公司 A kind of constant rail-to-rail difference amplifier of low-voltage mutual conductance
CN107508567B (en) * 2017-08-29 2019-06-04 南京邮电大学南通研究院有限公司 A kind of constant rail-to-rail difference amplifier of low-voltage mutual conductance
CN110166009A (en) * 2019-04-30 2019-08-23 思瑞浦微电子科技(苏州)股份有限公司 A kind of pressure-resistant protection architecture of input

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