CN204810238U

CN204810238U - Auto bias CMOS difference amplifier and integrator

Info

Publication number: CN204810238U
Application number: CN201520184428.6U
Authority: CN
Inventors: 刘华瑞; 马清杰
Original assignee: China Aviation Chongqing Microelectronics Co Ltd
Current assignee: China Resources Microelectronics Chongqing Ltd
Priority date: 2015-03-30
Filing date: 2015-03-30
Publication date: 2015-11-25
Anticipated expiration: 2025-03-30

Abstract

The utility model relates to a circuit design field, definite theory, the utility model discloses an auto bias CMOS difference amplifier and applied auto bias CMOS difference amplifier's integrator, be applied to and reduce the consumption by a wide margin, and reduce the input noise and save the area of chip, the device includes the difference operational circuit of the auto bias transistor in a pair of differential input transistor and a conduct tail current source, through inputing differential voltage signal at this input to the differential input transistor, it gives the differential input transistor to make the auto bias transistor produce the tail current, avoided traditional mode to need the problem of external extra power and port.

Description

A kind of automatic biasing CMOS differential amplifier and a kind of integrator

Technical field

The utility model relates to circuit design field, specifically, is specifically related to a kind of automatic biasing CMOS differential amplifier and a kind of integrator applying automatic biasing CMOS differential amplifier.

Background technology

Along with the development of electronic circuit technology, discharge circuit application is more and more extensive, in current cmos circuit design, general extra voltage source generation bias voltage or the applying bias voltage of all needing provides tail current source, bias voltage is produced by extra voltage source and considerably increases power consumption, and applying bias needs extra port to also increase the area of chip.

Therefore, do not need to add extra port without the need to extra voltage source while how providing bias voltage yet and become a great problem that those skilled in the art face.

Utility model content

The utility model provides a kind of automatic biasing CMOS differential amplifier and a kind of integrator applying automatic biasing CMOS differential amplifier according to the deficiencies in the prior art, by the grid of a bias transistor is connected with drain electrode, a pair differential voltage signal is inputted in differential input transistor, automatic biasing transistor as tail current source provides tail current for this to differential input transistor, concrete, the technical solution of the utility model is:

A kind of automatic biasing CMOS differential amplifier, wherein, specifically comprises:

A pair differential input transistor, for inputting a pair differential voltage signal;

An automatic biasing transistor as tail current source, for this provides tail current to differential input transistor, the mode that this automatic biasing transistor connects with diode by drain coupled to grid.

Above-mentioned automatic biasing CMOS differential amplifier, wherein, a load transistor M3 is connected with between a transistor M1 in described a pair differential input transistor and supply voltage VDD, a load transistor M4 is connected with between another transistor M2 in a pair differential input transistor and supply voltage VDD, wherein the grid of transistor M3 be connected to its drain electrode and the grid of transistor M3 and transistor M4 links together as current-mirror structure, the common node arranging transistor M4 and transistor M2 interconnection place is output node.

Above-mentioned automatic biasing CMOS differential amplifier, wherein, described transistor M1 and transistor M2 is N-type transistor, and described transistor M3 and transistor M4 is P-type crystal pipe.

Above-mentioned automatic biasing CMOS differential amplifier, wherein, described automatic biasing transistor is a N-type transistor, and described automatic biasing transistor is connected between a pair differential input transistor and earth terminal.

Apply an integrator for above-mentioned automatic biasing CMOS differential amplifier, it is characterized in that, described integrator comprises:

One CMOS differential amplifier;

One electric capacity, between the inverting input of described capacitive coupling in described a pair differential input transistor and the output of automatic biasing CMOS differential amplifier;

One switching circuit, described switching circuit and described Capacitance parallel connection.

The integrator of above-mentioned employing automatic biasing CMOS differential amplifier, wherein, described switching circuit comprises a complementary P type metal-oxide-semiconductor and a N-type metal-oxide-semiconductor, in switching circuit, one end of electric capacity is linked in the source electrode of P type metal-oxide-semiconductor and the drain electrode of N-type metal-oxide-semiconductor, in switching circuit, the drain electrode of P type metal-oxide-semiconductor and the source electrode of N-type metal-oxide-semiconductor link the other end of electric capacity, the grid of P type metal-oxide-semiconductor and the grid corresponding driving being subject to the control signal of a pair complementation respectively of N-type metal-oxide-semiconductor in switching circuit.

A method for automatic biasing tail current is provided in CMOS differential amplifier, wherein, comprises the following steps:

Gate terminal one of in a pair Differential Input crystal inputs a voltage signal in a pair differential voltage signal and the gate terminal of another one inputs this to another voltage signal in voltage signal in a pair differential input transistor;

An automatic biasing transistor is utilized to provide tail current for this to differential input transistor;

Flow through a pair differential input transistor automatic biasing transistor of electric current common stream through connecting with diode fashion separately, the total current flowing through a pair differential input transistor is clamped down at a pre-set current value by this automatic biasing transistor.

The utility model solves biasing circuit in prior art to be needed to provide extra voltage source or need to provide additional port could form the problem of tail current, without the need to providing extra voltage thus decreasing power consumption, simultaneously without the need to providing additional port, reducing the area of chip, effectively reducing noise.

Accompanying drawing explanation

By reading the detailed description done non-limiting example with reference to the following drawings, the utility model and feature, profile and advantage will become more obvious.Mark identical in whole accompanying drawing indicates identical part.Deliberately proportionally do not draw accompanying drawing, focus on purport of the present utility model is shown.

Fig. 1 is auto bias circuit structural representation in the utility model embodiment differential operational amplifier;

Fig. 2 uses the integrator circuit structure chart of operational amplifier of making the rounds of the wards disclosed in the utility model for one.

Embodiment

In the following description, give a large amount of concrete details to provide to understand more thoroughly the utility model.But, it is obvious to the skilled person that the utility model can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the utility model, technical characteristics more well known in the art are not described.

Should be understood that, the utility model can be implemented in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present utility model is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.

In order to thoroughly understand the utility model, by proposing detailed step and detailed structure in following description, to explain the technical solution of the utility model.Preferred embodiment of the present utility model is described in detail as follows, but except these are described in detail, the utility model can also have other execution modes.

The utility model provides a kind of automatic biasing CMOS differential amplifier and a kind of integrator applying automatic biasing CMOS differential amplifier, provides an embodiment to be further elaborated the utility model below.

With reference to structure shown in accompanying drawing 1, the utility model provides a kind of automatic biasing CMOS differential amplifier, wherein, this automatic biasing CMOS differential amplification implement body mainly comprises a pair differential input transistor (N-type transistor M1 and N-type transistor M2), an automatic biasing transistor as tail current source (N-type transistor M5).Here the transistor mentioned is the P type or the N-type MOS transistor that are compatible with stand CMOS.

A load P type transistor M3 is connected with between a N-type transistor M1 in a pair differential input transistor and supply voltage VDD, a P type load transistor M4 is connected with between another N-type transistor M2 in a pair differential input transistor and supply voltage VDD, wherein the grid of transistor M3 be connected to its drain electrode and the grid of transistor M3 and transistor M4 links together as current-mirror structure, the common node 110 of M4 and M2 is set to output node.

Automatic biasing transistor is a N-type transistor M5, the mode that transistor M5 connects with diode by drain electrode be coupled to grid, for this provides tail current to differential input transistor M1, M2, the drain electrode of transistor M5 is connected to input transistors M1, M2 source electrode separately at node 100 place, and the electric current flowing through input transistors M1 and the electric current merging flowing through input transistors M2 flow through automatic biasing transistor M5.

With reference to structure shown in Fig. 2, for a kind of structural representation of integrator circuit, this integrator circuit application CMOS differential amplifier that automatic biasing tail current can be provided disclosed in the utility model, in the present embodiment, with the grid of the M2 in a pair differential input transistor M1 and the M2 inverting input as automatic biasing CMOS differential amplifier, an electric capacity C is coupled with, a switching circuit in parallel at the two ends of this electric capacity C between inverting input and the output 110 of automatic biasing CMOS differential amplifier.

Although switching circuit can comprise an independent electron crystal tube device as diverter switch in certain embodiments, but as the present invention's preferred embodiment, this switching circuit can also be made up of a P-type crystal pipe M6 and N-type transistor M7, wherein the source electrode of M6 and the drain electrode of M7 are connected to one end of electric capacity C, the drain electrode of transistor M6 and the source electrode of transistor M7 are connected to the other end relative to this one end of electric capacity C, the grid corresponding driving being subject to the control signal of a pair complementation respectively of metal-oxide-semiconductor M6 and metal-oxide-semiconductor M7, such as, the grid of a control signal RSTF driving N metal-oxide-semiconductor M7, the control signal RSTI of another and control signal RSTF complementation drives the grid of PMOS M6, the inversion signal of control signal RSTF and control signal RSTI logic low and high level each other.

Based on this CMOS differential amplifier, the utility model provides a kind of method providing automatic biasing tail current in CMOS differential amplifier, and the method comprises:

Gate input one of in a pair differential input transistor inputs a voltage signal in a pair differential voltage signal and the gate terminal of another one inputs another voltage signal in this pair differential voltage signal in this pair differential input transistor.

As the utility model preferred embodiment, structure shown in Figure 1, transistor M1 and transistor M2 forms a pair differential input transistor, in the gate terminal input difference voltage signal INP of transistor M1, in the gate terminal input difference voltage signal INN of transistor M2, wherein voltage signal INP and voltage signal INN is a pair differential voltage signal.

An automatic biasing transistor is utilized to provide tail current for this to differential input transistor.

By providing tail current by the grid of bias transistor with the mode be connected that drains, in the utility model preferred embodiment, transistor M5 is as bias transistor.

In the utility model preferred embodiment, differential voltage signal INN is contrary with INP size equidirectional, therefore the size of current produced respective circuit is equal, direction is contrary, and the current signal therefore flowing through automatic biasing transistor M5 and size before non-input difference voltage signal INN with INP, direction are identical.

The utility model is by automatic biasing CMOS differential amplifier, form and there is correlated-double-sampling (CDS, CorrelationDoubleClickSampling) integrator of function, considerably reduce power consumption, input noise decreases more than 80% than fixed bias CMOS amplifier, more saves chip area.

In sum, because the utility model have employed above technical scheme, difference operational amplifying circuit biasing problem is solved, simultaneously without the need to providing extra voltage source or separate port, decreasing chip area, reducing power consumption, save production cost further, technique is simple, is applicable to promoting the use of.

Above preferred embodiment of the present utility model is described.It is to be appreciated that the utility model is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solutions of the utility model ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solutions of the utility model, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present utility model.Therefore, every content not departing from technical solutions of the utility model, according to technical spirit of the present utility model to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solutions of the utility model protection.

Claims

1. an automatic biasing CMOS differential amplifier, is characterized in that, comprising:

2. automatic biasing CMOS differential amplifier according to claim 1, it is characterized in that, a load transistor M3 is connected with between a transistor M1 in described a pair differential input transistor and supply voltage VDD, a load transistor M4 is connected with between another transistor M2 in a pair differential input transistor and supply voltage VDD, wherein the grid of transistor M3 be connected to its drain electrode and the grid of transistor M3 and transistor M4 links together as current-mirror structure, the common node arranging transistor M4 and transistor M2 interconnection place is output node.

3. automatic biasing CMOS differential amplifier according to claim 2, it is characterized in that, described transistor M1 and transistor M2 is N-type transistor, and described transistor M3 and transistor M4 is P-type crystal pipe.

4. automatic biasing CMOS differential amplifier according to claim 1, it is characterized in that, described automatic biasing transistor is a N-type transistor, and described automatic biasing transistor is connected between a pair differential input transistor and earth terminal.

5. have an integrator for automatic biasing CMOS differential amplifier according to claim 1, it is characterized in that, described integrator comprises:

One CMOS differential amplifier;

6. the integrator of automatic biasing CMOS differential amplifier according to claim 5, it is characterized in that, described switching circuit comprises a complementary P type metal-oxide-semiconductor and a N-type metal-oxide-semiconductor, in switching circuit, one end of electric capacity is linked in the source electrode of P type metal-oxide-semiconductor and the drain electrode of N-type metal-oxide-semiconductor, in switching circuit, the drain electrode of P type metal-oxide-semiconductor and the source electrode of N-type metal-oxide-semiconductor link the other end of electric capacity, the grid of P type metal-oxide-semiconductor and the grid corresponding driving being subject to the control signal of a pair complementation respectively of N-type metal-oxide-semiconductor in switching circuit.