CN102355212A - Rail-to-rail input stage with current compensation function - Google Patents
Rail-to-rail input stage with current compensation function Download PDFInfo
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- CN102355212A CN102355212A CN2011102267668A CN201110226766A CN102355212A CN 102355212 A CN102355212 A CN 102355212A CN 2011102267668 A CN2011102267668 A CN 2011102267668A CN 201110226766 A CN201110226766 A CN 201110226766A CN 102355212 A CN102355212 A CN 102355212A
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Abstract
The invention belongs to the technical field of analogue circuit designing, and particularly discloses a rail-to-rail input stage with a current compensation function. The rail-to-rail input stage is formed by connecting four input differential tubes, eight triple current mirrors and eight compensation variable current sources by a circuit. The rail-to-rail input stage realizes current compensation under different input common mode levels by utilizing the variable current sources to make direct current extracted from a post stage unrelated with the input common mode levels, thereby reducing the output imbalance of the post stage.
Description
Technical field
The invention belongs to the Analog Circuit Design technical field, be specifically related to the input stage of the amplifier in a kind of analog circuit.
Background technology
In analog circuit, the common mode electrical level of signal is indefinite often, and therefore possible signal common mode electrical level scope can be as big as by negative supply voltage to positive voltage.In order to handle the common mode electrical level various signals, rail-to-rail input stage is the important component part of amplifier.
In practical application, when being implemented in different input common mode electrical level the mutual conductance of overall input stage constant, need when different input common mode electrical levels, give the different direct current of input transistors usually.Directly the level output stage extracts from the back because this electric current is by input stage, therefore just makes the direct current of output stage when difference input common mode electrical level, change.The direct result of the change of this direct current is exactly that output stage exists the output imbalance, promptly can change with the input common mode electrical level in that output DC is flat, thereby influence the performance of amplifier.
Summary of the invention
The objective of the invention is to propose a kind of new rail-to-rail input stage,, the input stage direct current that level extracts from the back is not changed with common mode electrical level, thereby reduce the output drift through using current compensation.
The rail-to-rail input stage that the present invention proposes, its circuit structure as shown in Figure 1.By input difference to the pipe: M1, M2, M3, M4; Three times of current mirror: MB1, MB2, MB3, MB4, MB5, MB6, M5, M6; And compensate for variable current source: I1, I2, I3, I4, I5, I6, I7, I8; Connect to form through circuit; Compensating action through variable current source; When being implemented in incoming level by negative supply voltage to positive voltage, this input stage direct current that level extracts from the back is constant.
Wherein, input pipe M1 and M2 are NMOS, and input pipe M3 and M4 are PMOS.Difference input in1 connects the grid of input pipe M1 and M3, and difference input in2 connects the grid of input pipe M2 and M4.The source end of input pipe M1 and M2 is connected to the drain terminal of three times of current mirror pipe MB2, MB3 and the source end of three times of current mirror pipe M6.The source end of input pipe M3 and M4 is connected to the drain terminal of three times of current mirror pipe MB5, MB6 and the source end of three times of current mirror pipe M5.The drain terminal a1 point of input pipe M1 meets variable current source I3 and I5, and links to each other with the back level, and level extracts electric current from the back.The drain terminal a2 point of input pipe M2 meets variable current source I4 and I6, and links to each other with the back level, and level extracts electric current from the back.The drain terminal a3 point of input pipe M3 meets variable current source I1 and I8, and links to each other with the back level, and level extracts electric current from the back.The drain terminal a4 point of input pipe M4 meets variable current source I2 and I7, and links to each other with the back level, and level extracts electric current from the back.The grid of three times of current mirror pipe MB6 meets external bias voltage V
B1, the grid of three times of current mirror pipe MB3 meets external bias voltage V
B2The grid of the grid level of three times of current mirror pipe MB2 and three times of current mirror pipe MB1 links to each other with drain electrode, and the breadth length ratio of three times of current mirror pipe MB1 is three times of three times of current mirror pipe MB2, forms three times of current mirrors.The drain electrode of three times of current mirror pipe MB1 links to each other with the drain electrode of three times of current mirror pipe M5 simultaneously, and the grid of three times of current mirror pipe M5 meets external reference voltage V
RnThe grid of the grid level of three times of current mirror pipe MB5 and three times of current mirror pipe MB4 links to each other with drain electrode, and the breadth length ratio of three times of current mirror pipe MB5 is three times of three times of current mirror pipe MB4, forms three times of current mirrors.The drain electrode of three times of current mirror pipe MB4 links to each other with the drain electrode of three times of current mirror pipe M6 simultaneously, and the grid of three times of current mirror pipe M5 meets external reference voltage V
Rn
When the input common mode electrical level is intermediate level, input pipe M1, M2, M3, M4 conducting simultaneously.External reference voltage V
RnAnd V
RpChoose suitable value and make M5 and M6 all turn-off this moment, then only MB3 and MB6 conducting in three times of current mirror pipes, and size of current all is 2I0.The variable current source Close All.This moment M1, M2, M3, the electric current of M4 equate that size all is I0.Input pipe M1, M2, M3, the size Selection of M4 makes M1, M2, M3, the mutual conductance of M4 equates to be gm0, then this moment input stage mutual conductance be that the mutual conductance of M1 and M3 pipe (being equivalent to M2 and M4 pipe) adds up to 2gm0, and the electric current of input stage grade extraction from the back is I0.
When the input common mode electrical level was high level (near positive voltage), input pipe M1 and M2 pipe turn-offed, and mutual conductance is that the source voltage rising of 0, three times of current mirror pipe M6 makes its conducting.This moment, the electric current 2I0 of three times of current mirror pipe MB3 all flowed into three times of current mirror pipe MB4 through M6.Because the size that three times of current mirror pipe MB5 and three times of current mirror pipe MB4 are current mirror and three times of current mirror pipe MB5 is three times of three times of current mirror pipe MB4, therefore, the electric current of three times of current mirror pipe MB5 this moments is 6I0.MB1 in three times of current mirror pipes, MB2 and M5 turn-off.So this moment, the electric current of input pipe M3 and M4 was 4I0.Because the square-law characteristic of MOSFET, promptly its mutual conductance becomes quadratic relationship with electric current under the constant situation of fixed size, and the mutual conductance of M3 and M4 all is 2gm0 at this moment.Therefore, the mutual conductance of input stage is that the mutual conductance addition of M1 and M3 pipe (being equivalent to M2 and M4 pipe) still is 2gm0.At this moment, variable current source I1, I2, I3, I4 conducting.Variable current source I1, the electric current of I2 are 3I0, and variable current source I3, the stream of I4 is I0.Like this, the input stage electric current that level extracts from the back is I0 still, compares when incoming level is intermediate level not change.
When the input common mode electrical level was low level (near negative supply voltage), input pipe M3 and M4 pipe turn-offed, and mutual conductance is that the source voltage reduction of 0, three times of current mirror pipe M5 makes its conducting.This moment, the electric current 2I0 of three times of current mirror pipe MB6 all flowed into three times of current mirror pipe MB1 through three times of current mirror pipe M5.Because three times of current mirror pipe MB1 and three times of current mirror pipe MB2 are current mirrors, and the size of three times of current mirror pipe MB2 is three times of three times of current mirror pipe MB1, and therefore the electric current of three times of current mirror pipe MB2 this moments is 6I0.MB4 in three times of current mirror pipes, MB5 and M6 turn-off.So this moment, the electric current of input pipe M1 and M2 was 4I0.Because the square-law characteristic of MOSFET; Promptly its mutual conductance becomes quadratic relationship with electric current under the constant situation of fixed size; Therefore this moment M1 and M2 mutual conductance all be 2gm0, so the mutual conductance of input stage is that M1 manages (being equivalent to M2 and M4 manages) with M3 mutual conductance addition still is 2gm0.At this moment, variable current source I5, I6, I7, I8 conducting.Variable current source I5, the electric current of I6 are 3I0, and variable current source I7, the stream of I8 is I0.Like this, the input stage electric current that level extracts from the back is I0 still, compares when incoming level is intermediate level not change.
To sum up, it is constant and electric current that level extracts from the back is constant that the rail-to-rail input stage of the belt current compensation that proposes of the present invention can satisfy mutual conductance when difference input common mode electrical level.
Description of drawings
Fig. 1 is the structure chart of the rail-to-rail input stage of belt current compensation of the present invention.
Fig. 2 is one embodiment of the present invention diagrams.
Embodiment
Through an instantiation the present invention is described in further detail below.
Fig. 2 has provided the complete circuit of the amplifier of the rail-to-rail input stage of using the belt current compensation.Wherein, variable current source is realized by transistor Mco1 ~ Mco12.Output stage then is the folded common source and common grid level, and MC1 ~ MC8 forms by transistor.
When input common mode electrical level when being intermediate level, input pipe M1, M2, M3, M4 conducting simultaneously, and only MB3 and MB6 conducting in three times of current mirror pipes, and size of current all is 2I0.This moment, therefore variable current source capsule Mco9 and the Mco10 as its current mirror do not have electric current yet because three times of current mirror pipe MB4 do not have electric current, the grid voltage of Mco9, and promptly Vco1 is high, so variable current source capsule Mco1 ~ Mco4 all turn-offs.In like manner, because three times of current mirror pipe MB1 do not have electric current, therefore variable current source capsule Mco11 and the Mco12 as its current mirror do not have electric current yet, the grid voltage of Mco12, and promptly Vco2 is low, so variable current source capsule Mco5 ~ Mco8 all turn-offs.The variable current source Close All.This moment M1, M2, M3, the electric current of M4 equate that size all is I0.Input pipe M1, M2, M3, the size Selection of M4 makes M1, M2, M3, the mutual conductance of M4 equates to be gm0, then this moment input stage mutual conductance be that the mutual conductance of M1 and M3 pipe (being equivalent to M2 and M4 pipe) adds up to 2gm0, and the electric current of input stage grade extraction from the back is I0.
When the input common mode electrical level was high level (near positive voltage), input pipe M1 and M2 pipe turn-offed, and mutual conductance is that the source voltage rising of 0, three times of current mirror pipe M6 makes its conducting.This moment, the electric current 2I0 of three times of current mirror pipe MB3 all flowed into MB4 through M6.Because MB5 and MB4 are the sizes of current mirror and MB5 is three times of MB4, so MB5 electric current at this moment is 6I0.MB1 in three times of current mirror pipes, MB2 and M5 turn-off.So this moment, the electric current of input pipe M3 and M4 was 4I0.Because the square-law characteristic of MOSFET; Promptly its mutual conductance becomes quadratic relationship with electric current under the constant situation of fixed size; Therefore this moment M3 and M4 mutual conductance all be 2gm0, so the mutual conductance of input stage is that M1 manages (being equivalent to M2 and M4 manages) with M3 mutual conductance addition still is 2gm0.At this moment; Because three times of current mirror pipe MB4 have electric current; Therefore variable current source capsule Mco9 and the Mco10 as its current mirror also has electric current; The grid voltage of Mco9; Be that Vco1 is low; Therefore the whole conductings of variable current source capsule Mco1 ~ Mco4, wherein the electric current that flows through of Mco1 and Mco2 is 3I0, and the electric current that Mco3 and Mco4 flow through is I0.On the other hand, variable current source capsule Mco5 ~ Mco8 all turn-offs.Like this, the input stage electric current that level extracts from the back is I0 still, compares when incoming level is intermediate level not change.
When the input common mode electrical level was low level (near negative supply voltage), input pipe M3 and M4 pipe turn-offed, and mutual conductance is that the source voltage reduction of 0, three times of current mirror pipe M5 makes its conducting.This moment, the electric current 2I0 of three times of current mirror pipe MB6 all flowed into MB1 through M5.Because MB1 and MB2 are the sizes of current mirror and MB2 is three times of MB1, so MB2 electric current at this moment is 6I0.MB4 in three times of current mirror pipes, MB5 and M6 turn-off.So this moment, the electric current of input pipe M1 and M2 was 4I0.Because the square-law characteristic of MOSFET; Promptly its mutual conductance becomes quadratic relationship with electric current under the constant situation of fixed size; Therefore this moment M1 and M2 mutual conductance all be 2gm0, so the mutual conductance of input stage is that M1 manages (being equivalent to M2 and M4 manages) with M3 mutual conductance addition still is 2gm0.At this moment; Because three times of current mirror pipe MB1 have electric current; Therefore variable current source capsule Mco11 and the Mco12 as its current mirror also has electric current; The grid voltage of Mco12; Be that Vco2 is high; Therefore the whole conductings of variable current source capsule Mco5 ~ Mco8, wherein the electric current that flows through of Mco5 and Mco6 is 3I0, and the electric current that Mco7 and Mco8 flow through is I0.On the other hand, variable current source capsule Mco1 ~ Mco4 all turn-offs.Like this, the input stage electric current that level extracts from the back is I0 still, compares when incoming level is intermediate level not change.
Because in the process that the input common mode electrical level changes, input stage does not change from the direct current that output stage MC1 ~ MC8 extracts, therefore system-level output imbalance has reduced.
It should be noted last that; Above embodiment is only unrestricted in order to technical scheme of the present invention to be described; Although the present invention is described in detail with reference to preferred embodiment; Those of ordinary skill in the art is to be understood that; Can make amendment or be equal to replacement technical scheme of the present invention; And not breaking away from the spirit and scope of technical scheme of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (1)
1. the rail-to-rail input stage of belt current compensation; It is characterized in that by 4 input difference pipes (M1, M2, M3, M4); 8 three times of current mirrors (MB1, MB2, MB3, MB4, MB5, MB6, M5, M6); And 8 compensate for variable current sources (I1, I2, I3, I4, I5, I6, I7, I8), connect to form through circuit;
Wherein, first input pipe (M1) and second input pipe (M2) are the NMOS pipes, and the 3rd input pipe (M3) and the 4th input pipe (M4) are the PMOS pipes; First difference input (in1) connects the grid of first input pipe (M1) and the 3rd input pipe (M3), and second difference input (in2) connects the grid of second input pipe (M2) and the 4th input pipe (M4); The source end of first input pipe (M1) and second input pipe (M2) is connected to the drain terminal of the two or three times of current mirror pipe (MB2), the three or three times of current mirror pipe (MB3) and the source end of the eight or three times of current mirror pipe (M6); The source end of the 3rd input pipe (M3) and the 4th input pipe (M4) is connected to the drain terminal of the five or three times of current mirror pipe (MB5), the six or three times of current mirror pipe (MB6) and the source end of the seven or three times of current mirror pipe (M5); The drain terminal a1 point of first input pipe (M1) connects the 3rd variable current source (I3) and the 5th variable current source (I5), and links to each other with the back level, and level extracts electric current from the back; The drain terminal a2 point of second input pipe (M2) connects the 4th variable current source (I4) and the 6th variable current source (I6), and links to each other with the back level, and level extracts electric current from the back; The drain terminal a3 point of the 3rd input pipe (M3) connects first variable current source (I1) and the 8th variable current source (I8), and links to each other with the back level, and level extracts electric current from the back; The drain terminal a4 point of the 4th input pipe (M4) connects second variable current source (I2) and the 7th variable current source (I7), and links to each other with the back level, and level extracts electric current from the back; The grid of the six or three times of current mirror pipe (MB6) meets external bias voltage V
B1, the grid of the three or three times of current mirror pipe (MB3) meets external bias voltage V
B2The grid level of the two or three times of current mirror pipe (MB2) and the grid of the one or three times of current mirror pipe (MB1) link to each other with drain electrode, and the breadth length ratio of the one or three times of current mirror pipe (MB1) is three times of the two or three times of current mirror pipe (MB2), form three times of current mirrors; The drain electrode of the one or three times of current mirror pipe (MB1) links to each other with the drain electrode of the seven or three times of current mirror pipe (M5) simultaneously, and the grid of the seven or three times of current mirror pipe (M5) meets external reference voltage V
RnThe grid level of the five or three times of current mirror pipe (MB5) and the grid of the four or three times of current mirror pipe (MB4) link to each other with drain electrode, and the breadth length ratio of the five or three times of current mirror pipe (MB5) is three times of the four or three times of current mirror pipe (MB4), form three times of current mirrors; The drain electrode of the four or three times of current mirror pipe (MB4) links to each other with the drain electrode of the eight or three times of current mirror pipe (M6) simultaneously, and the grid of the seven or three times of current mirror pipe (M5) meets external reference voltage V
Rn
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| CN2011102267668A CN102355212A (en) | 2011-08-09 | 2011-08-09 | Rail-to-rail input stage with current compensation function |
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| CN2011102267668A CN102355212A (en) | 2011-08-09 | 2011-08-09 | Rail-to-rail input stage with current compensation function |
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Cited By (5)
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| CN104320096A (en) * | 2014-10-04 | 2015-01-28 | 复旦大学 | Microcurrent and current feedback chopper modulation instrument amplifier |
| CN104967412A (en) * | 2015-06-08 | 2015-10-07 | 上海华力微电子有限公司 | Novel transconductance constant differential pair input circuit |
| CN109756192A (en) * | 2018-11-22 | 2019-05-14 | 合肥市芯海电子科技有限公司 | A kind of input stage of the rail-to-rail mutual conductance amplifying circuit of reliable low pressure |
| CN113671236A (en) * | 2021-08-25 | 2021-11-19 | 广东工业大学 | Current detection circuit and equipment applied to load resistor |
| CN114285380A (en) * | 2021-12-29 | 2022-04-05 | 华中科技大学 | Rail-to-rail operational amplifier circuit |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104320096A (en) * | 2014-10-04 | 2015-01-28 | 复旦大学 | Microcurrent and current feedback chopper modulation instrument amplifier |
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| CN109756192B (en) * | 2018-11-22 | 2023-04-28 | 合肥市芯海电子科技有限公司 | Reliable input stage of low-voltage rail-to-rail transconductance amplifying circuit |
| CN113671236A (en) * | 2021-08-25 | 2021-11-19 | 广东工业大学 | Current detection circuit and equipment applied to load resistor |
| CN113671236B (en) * | 2021-08-25 | 2023-07-25 | 广东工业大学 | Current detection circuit and equipment applied to load resistor |
| CN114285380A (en) * | 2021-12-29 | 2022-04-05 | 华中科技大学 | Rail-to-rail operational amplifier circuit |
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Application publication date: 20120215 |