CN114285380B - Rail-to-rail operational amplifier circuit - Google Patents
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Abstract
The invention discloses a rail-to-rail operational amplifier circuit which has the characteristics of high stability and low power consumption. It comprises the following steps: a rail-to-rail input stage for receiving an input signal and outputting a first signal; a constant transconductance compensation stage for controlling the transconductance of the input stage to be constant; the cascode stage is used for generating a second signal according to the first signal; and a rail-to-rail output stage for generating an output signal based on the second signal; wherein the cascode stage comprises: a cascode circuit comprising: a first branch and a second branch forming a differential structure; and a current compensation circuit comprising: the third branch, the fourth branch and the fifth branch are used for extracting current from the constant transconductance compensation stage, and the fourth branch and the fifth branch are used for mirroring the current of the third branch so as to compensate the current of the first branch and the second branch by using the mirrored current to control the output current of the cascode stage to be constant.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a rail-to-rail operational amplifier circuit.
Background
Rail-to-rail (also known as "full swing") operational amplification circuits refer to a class of circuits in which the input and/or output voltage swing of the amplification circuit is very close to or nearly equal to the supply voltage, the structure of which is widely used in image sensors, analog-to-digital converters, and the like.
As shown in fig. 1, a schematic diagram of a conventional rail-to-rail operational amplifier circuit is shown. The rail-to-rail operational amplifier circuit includes: rail-to-rail input stage 10, constant transconductance compensation stage 11, cascode stage 12, and rail-to-rail output stage 13.
Wherein the input stage 10 comprises: transistors M1-M6, wherein the gates of M1-M4 are subjected to an input signal V IN And V IP The gates of M5 and M6 are controlled by bias voltage V BP1 And V BN1 Is controlled by the control system.
Wherein the constant transconductance compensation stage 11 comprises: transistors M15-M20, wherein the gates of M17 and M20 are respectively biased by a bias voltage V BN1 And V BP1 Controlling; wherein the constant transconductance compensation stage 11 is used for providing compensation current to the input stage 10 for providing compensation current to the input signal V IN And V IP The tail current of the input stage 10 is compensated for at the same time as the common mode level of the input stage 10 is different, thereby ensuring a constant transconductance of the input stage 10. In the figure, M17 and M20 are used to output compensation currents to the input stage 10, respectively.
Wherein the cascode stage 12 comprises: transistors M7-M14 and current source I B1 And I B2 The method comprises the steps of carrying out a first treatment on the surface of the The common-source common-gate 12 is used for improving the gain of the signal output by the input stage 10, and the current source I B1 And I B2 From the current source I shown in FIG. 2 B Providing, current source I B With transistors M25-M27 to provide I B1 And I B2 The method comprises the steps of carrying out a first treatment on the surface of the The drain of M12 and the drain of M10 are connected as an output of the cascode 12, which is connected to an output stage 13.
Wherein the output stage 13 adopts a classical class AB amplifier structure based on an inverter, comprising: transistors M23 and M24 and resistor R Z And capacitor C F The method comprises the steps of carrying out a first treatment on the surface of the Wherein V is OUT Is the output signal of the rail-to-rail operational amplifier circuit.
In the rail-to-rail operational amplifier circuit shown in fig. 1, a current source I is required B1 And I B2 Absolute equality, otherwise the transconductance (i.e., output transconductance) at the output node of cascode stage 12 (i.e., at the drain junction of M12 and M10) will be unstable, resulting in an unstable output signal of output stage 13, such as a shift in the common mode level in the output signal, which is shifted from current source I B1 And I B2 Is proportional to the deviation value of (c). However, in practical applications, the current source I is due to design errors B1 And I B2 It is difficult to achieve absolute equality, therefore the graphThe rail-to-rail operational amplifier circuit shown in fig. 1 has a problem of poor stability. On the other hand, as shown in FIGS. 1 and 2, in order to provide I B1 And I B2 At least 4 current branches, i.e. two I in FIG. 1, need to be designed B1 And I B2 Branch, and two I in FIG. 2 B1 And I B2 A branch; when the operational amplifier circuit works, the 4 current branches are always in a working state, so that the power consumption of the operational amplifier circuit is improved.
Disclosure of Invention
Accordingly, the present invention is directed to a rail-to-rail operational amplifier circuit with high stability and low power consumption.
In order to achieve the above object, an embodiment of the present invention provides a rail-to-rail operational amplifier circuit, including: a rail-to-rail input stage for receiving an input signal and outputting a first signal in dependence on the input signal; a constant transconductance compensation stage for controlling the transconductance of the input stage to be constant; the cascode stage is used for generating a second signal according to the first signal; and a rail-to-rail output stage for generating an output signal of the rail-to-rail operational amplifier circuit based on the second signal; the cascode stage comprises: a cascode circuit comprising: the first branch and the second branch which form a differential structure are used for generating a second signal according to the first signal; and a current compensation circuit comprising: and the third branch is used for extracting current from the constant transconductance compensation stage, and the fourth branch and the fifth branch are used for mirroring the current of the third branch so as to compensate the current of the first branch and the second branch by using the mirrored current to control the output current of the cascode stage to be constant.
In one embodiment, the rail-to-rail input stage comprises: the first differential output port and the second differential output port are respectively used for outputting a first differential signal and a second differential signal; the first branch includes: first to fourth transistors connected in series between a power supply voltage and ground, the second branch including: fifth to eighth transistors connected in series between a power supply voltage and ground, wherein gates of the first and fifth transistors are connected to a first bias voltage, gates of the second and sixth transistors are connected to a second bias voltage, gates of the third and seventh transistors are connected to a fourth bias voltage, and gates of the fourth and eighth transistors are connected to a connection point of the second and third transistors; the connection point of the first transistor and the second transistor, and the connection point of the fourth transistor and the fifth transistor are respectively connected with two ports of the first differential output ports to receive the first differential signal; the connection point of the third transistor and the fourth transistor, and the connection point of the seventh transistor and the eighth transistor are respectively connected with two ports of the second differential output ports to receive the second differential signal; wherein the junction of the sixth and seventh transistors serves as the output port of the cascode stage.
In one embodiment, the first, second, fifth and sixth transistors are P-type field effect transistors, and the third, fourth, seventh and eighth transistors are N-type field effect transistors.
In one embodiment, the fourth branch is connected in parallel with the first transistor, and the fifth branch is connected in parallel with the seventh transistor.
In one embodiment, the fourth branch comprises: a ninth transistor, the fifth branch including: and a tenth transistor connected in series between a power supply voltage and a connection point of the first and second transistors, the tenth transistor being connected in series between the power supply voltage and the connection point of the seventh and eighth transistors, gates of the ninth and tenth transistors being connected to a fifth bias voltage.
In one embodiment, the third branch comprises: an eleventh and twelfth transistor connected in series between the supply voltage and ground, the gate of the eleventh transistor being connected to the fifth bias voltage and to a connection point of the eleventh and twelfth transistors, the twelfth transistor being connected to the constant transconductance compensation stage.
In one embodiment, the ninth to eleventh transistors are P-type field effect transistors, and the twelfth transistor is an N-type field effect transistor.
In one embodiment, the rail-to-rail output stage employs a classical class AB amplifier architecture based on inverters.
In one embodiment, the rail-to-rail output stage further comprises: an RC compensation branch connected between the input and output ports of the rail-to-rail output stage.
In one embodiment, the rail-to-rail input stage comprises: the differential input port, a pair of N-type transistors and a pair of P-type transistors, wherein two grid electrodes of the pair of N-type transistors are respectively connected with two ports in the differential input port, two grid electrodes of the pair of P-type transistors are respectively connected with two ports in the differential input port, two drain electrodes of the pair of N-type transistors are used as first differential output ports of the rail-to-rail input stage, and two drain electrodes of the pair of P-type transistors are used as first differential output ports of the rail-to-rail input stage.
The embodiment of the invention has the beneficial effects that:
the rail-to-rail operational amplifier circuit of the embodiment of the invention adopts a differential structure for the common-source common-gate circuit part in the common-source common-gate stage, and the structure does not need two branches with equal current as shown in figure 1, so that the problem of current matching does not exist, and the unstable problem caused by unequal currents of the two branches can be avoided; meanwhile, the cascode stage of the embodiment of the invention comprises a current compensation circuit for compensating the currents of the two branches in the cascode circuit, so that the stability of the output current of the cascode stage can be ensured, and the stability of the operational amplifier circuit is ensured; on the other hand, the current compensation circuit of the embodiment of the invention can realize current compensation by utilizing three branches, and at least four branches are not needed as in fig. 1, so that the embodiment of the invention saves more power consumption compared with the structure of fig. 1. Therefore, the rail-to-rail operational amplifier circuit provided by the embodiment of the invention has the characteristics of high stability and low power consumption.
Drawings
FIG. 1 is a schematic diagram of a prior art rail-to-rail operational amplifier circuit;
FIG. 2 is a schematic diagram of a prior art current source;
FIG. 3 is a schematic diagram of an embodiment of a rail-to-rail operational amplifier circuit of the present invention;
FIG. 4 is a waveform diagram of a DC simulation of the structure shown in FIG. 3; and
fig. 5 is a waveform diagram of an ac simulation of the structure shown in fig. 3.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear and obvious, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the particular embodiments described herein are illustrative only and are not limiting upon the invention.
In the following description, suffixes such as "module", "component", or "unit" for representing elements are used only for facilitating the description of the present invention, and have no specific meaning per se. Thus, "module," "component," or "unit" may be used in combination.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
The invention will now be described by way of example with reference to the accompanying drawings.
The embodiment of the invention discloses a rail-to-rail operational amplifier circuit which has higher stability and lower power consumption compared with the structure shown in fig. 1.
Specifically, the circuit comprises a rail-to-rail operational amplifier circuit: a rail-to-rail input stage for receiving an input signal and outputting a first signal in dependence on the input signal; a constant transconductance compensation stage for controlling the transconductance of the input stage to be constant; the cascode stage is used for generating a second signal according to the first signal; and a rail-to-rail output stage for generating an output signal of the rail-to-rail operational amplifier circuit based on the second signal; the cascode stage comprises: a cascode circuit comprising: the first branch and the second branch which form a differential structure are used for generating a second signal according to the first signal; and a current compensation circuit comprising: and the third branch is used for extracting current from the constant transconductance compensation stage, and the fourth branch and the fifth branch are used for mirroring the current of the third branch so as to compensate the current of the first branch and the second branch by using the mirrored current to control the output current of the cascode stage to be constant.
The rail-to-rail operational amplifier circuit disclosed by the embodiment of the invention has the advantages that as the common-source common-gate circuit part in the common-source common-gate stage adopts a differential structure, two branches with equal current are not needed as shown in fig. 1, the problem of current matching is avoided, and the problem of instability caused by unequal currents of the two branches can be avoided; meanwhile, the cascode stage of the embodiment of the invention comprises a current compensation circuit for compensating the currents of the two branches in the cascode circuit, so that the stability of the output current of the cascode stage can be ensured, and the stability of the operational amplifier circuit is ensured; on the other hand, the current compensation circuit of the embodiment of the invention can realize current compensation by utilizing three branches, and at least four branches are not needed as in fig. 1, so that the embodiment of the invention saves more power consumption compared with the structure of fig. 1. Therefore, the rail-to-rail operational amplifier circuit provided by the embodiment of the invention has the characteristics of high stability and low power consumption.
In particular, the rail-to-rail operational amplifier circuit according to the embodiment of the present invention will be described in more detail with reference to fig. 3, where fig. 3 is only one implementation of the rail-to-rail operational amplifier circuit according to the embodiment of the present invention, and not the only implementation.
Fig. 3 is a schematic diagram of an embodiment of the rail-to-rail operational amplifier circuit of the present invention. The rail-to-rail operational amplifier circuit can realize rail-to-rail input and rail-to-rail output. As shown, the operational amplifier circuit includes: a rail-to-rail input stage 30, a constant transconductance compensation stage 31, a cascode stage 32, and a rail-to-rail output stage 33.
Wherein the input stage 30 comprises: in the figure, transistors M1 to M6 are P-type transistors such as PMOS transistors, and M3, M4 and M5 are N-type transistors such as NMOS transistors. Wherein, the grids of M1-M4 receive input signals V IN And V IP The gates of M5 and M6 are controlled by bias voltage V BP1 And V BN1 Is controlled by the control system. Specifically, in the input signal V IN And V IP Under control of (a), M1 and M2 are turned on, or M3 and M4 are turned on. Wherein the input signal V IN And V IP Is a differential input signal. For example, when V IN And V IP At high voltages (e.g., high levels), M3 and M4 are on and M1 and M2 are off. While when V IN And V IP At low voltages (e.g., low levels), M3 and M4 are off and M1 and M2 are on. Wherein M5 and M6 are used as tail current tubes, and the bias voltage V BP1 And V BN1 Provided from the outside. In the figure, the drains of M1 and M2 are connected to the cascode stage 32 of the next stage, so the drains of M1 and M2 serve as a pair of differential output ports of the input stage 30; similarly, the drains of M3 and M4 are also connected to the cascode stage 32 of the next stage, so the drains of M3 and M4 serve as the other pair of differential output ports of the input stage 30.
Wherein the constant transconductance compensation stage 31 comprises: in the figure, transistors M15 to M20 are N-type transistors, such as NMOS transistors, and transistors M18 to M20 are P-type transistors, such as PMOS transistors. The constant transconductance compensation stage 31 is used to provide a compensation current to the input stage 30 to control the transconductance of the input stage 30 to be constant (i.e. stable). Specifically, the two output nodes of the constant transconductance compensation stage 31 are respectively connected to the current compensation nodes of the input stage 30 to provide the compensation current to the input stage 30. In the figure, the drain of M17 and the drain of M20 are two output nodes of the constant transconductance compensation stage 31, the drain of M6 and the drain of M5 as tail current pipes are current compensation nodes of the input stage 30, that is, M17 outputs compensation current to the drain of M6, and M20 outputs compensation current to the drain of M5. Wherein the gates of M17 and M20 are respectively biased by a bias voltage V BN1 And V BP1 And (5) controlling. Wherein M15-M20 form the structure of a current mirror, and output compensation current through the current mirror. Through the constant transconductance compensation stage 31, the input signal V can be obtained IN And V IP Is a common mode of (2)The level difference compensates the tail current of the input stage 30, thereby ensuring the transconductance of the input stage 30 to be constant.
Wherein the cascode stage 12 comprises: transistors M7 to M14, and M21 to M24; in the figure, M7-M10 and M21 are N-type transistors, such as NMOS transistors, and M11-M14 and M22-M24 are P-type transistors, such as NMOS transistors. Wherein M7-M14 form a cascode circuit for amplifying an input signal of a preceding stage circuit (i.e., the input stage 30) to increase a gain thereof. In the drawings, M7 to M14 constitute a differential cascode circuit, where M7, M9, M11 and M13 constitute a first branch, and M8, M10, M12 and M14 constitute a second branch. As shown, the gates of M13 and M14, the gates of M11 and M12, and the gates of M9 and M10 are respectively biased by a bias voltage V BP1 、V BP2 And V BN2 Controlled and bias voltage V BP1 、V BP2 And V BN2 The gates of M7 and M8 are connected to the drain of M9, which may be provided externally. Wherein the drains of M7 and M10 (or the sources of M9 and M10), and the sources of M11 and M12 (or the drains of M13 and M14) are inputs of the cascode stage 12 for receiving the input signal from the input stage 30, and the drain of M12 (or the drain of M10) is an output of the cascode stage 12 for outputting the signal to the output stage 33. Wherein M21 to M24 constitute a current compensation circuit for compensating the current of the cascode circuit to control the output current of the cascode stage 32 to be constant or the transconductance (output transconductance) to be constant. As shown, transistors M21 and M22 form a branch for mirroring current from the constant transconductance compensation stage 31, the gate of M21 is connected to the gate and drain of M16 as shown, and the gate of M22 is biased by a bias voltage V X Is controlled by the control system. Transistors M23 and 24 respectively form two compensation branches for respectively compensating the current of the drain electrode of M13 (or the source electrode of M11), the drain electrode of M14 (or the source electrode of M12), and M23 and 24 are also subjected to bias voltage V X Where Vx is generated by the M21 and M22 branches and mirrored in a current mirror configuration through M22 to M23 and M24. In the present embodiment, when the common mode level of the input signal is high, M23 and M24 compensate the current extraction of the input stage 30 from the cascode output stage 32, thereby ensuring the current stability of M10 and M12 as output pipes; specificallyThe current compensation is automatically started, when the common-mode voltage of the input signal is higher, the branches M21 and M22 are started (because the branches M15 and M16 are started when the common-mode voltage is higher, the current of M5 is compensated, the transconductance of M3 and M4 is kept stable, the grids of M15, M16 and M21 are connected together, and therefore, the branch M21 is started after the branches M15 and M16 are started), the branches M23 and M24 are started in the mirror image at the moment, otherwise, the grid end voltage Vx of the branches M23 and M24 is high, and the branches M23 and M24 are naturally shut down, so that the power consumption is saved.
The output stage 13 adopts a classical class AB amplifier structure based on an inverter, and by adopting the structure, a larger output range voltage and higher load driving capability can be realized at the same time. Which receives a signal from the cascode stage 32 and generates an output signal V of the rail-to-rail operational amplifier circuit based on the signal OUT . In the figure, the output stage 13 comprises: transistors M25 and M26 and resistor R Z And capacitor C F . The transistor M25 is a P-type transistor, such as a PMOS transistor, and the transistor M26 is an N-type transistor, such as an NMOS transistor, and the gates of the transistor M25 and the transistor M26 are connected to the output of the cascode stage 32, and are turned on or turned off under the control of the output of the cascode stage 32. For example, when the output of the cascode gate 32 is low (e.g., low), M25 is turned on, while M26 is used as a load tube; similarly, when the output of the cascode gate 32 is high (e.g., high), M26 is turned on while M25 is used as a load tube. In addition, resistance R Z And capacitor C F As RC compensating branch, where R Z The circuit is a zero compensation resistor, and is used for moving the zero of the right half plane of the circuit to the left half plane, eliminating the first non-main pole point and improving the unit gain bandwidth of the circuit; c (C) F For the first stage output (i.e. R Z The output of the left node) and the second stage output (i.e., final output V OUT ) And the Miller compensation capacitance is used for realizing the splitting of the first pole and the second pole of the operational amplifier. At R Z And C F The combined action of the two amplifiers can compensate the frequency characteristic of the operational amplifier and ensure the stability of the operational amplifier.
The common-source common-gate stage of this embodiment does not need to design two input branches with equal current as in the structure of fig. 1, so there is no current matching problem, and the problem that the output common-mode current is offset because the two branch currents are unequal can be avoided. In addition, the cascode stage of the embodiment can realize current compensation by only using one current bias branch and two compensation branches, and the three branches only work when the input common mode level is higher, so that the power consumption can be saved.
The advantages of embodiments of the present invention are further described below in conjunction with the simulated diagrams shown in fig. 4 and 5.
As shown in fig. 4, a waveform diagram of the dc simulation of the structure of fig. 3 is shown. In the simulation, the power supply Voltage (VCC) was set to 1.8V and the ground voltage (GND) was set to 0V. In the figure, the curve (1) is an output voltage curve, the curve (2) is a derivative of the curve (1), and the slope of the curve (1) is shown. As can be seen from the graph, when the input signal varies in the range of 0-1.8V on the abscissa, the output signal can well follow the variation of the input signal, especially before 0.15V to 1.65V, and the value of the (2) curve is 1, which indicates that the circuit realizes the functions of rail-to-rail input and rail-to-rail output. Under the conditions of extremely low input voltage of 0-0.15V and extremely high input voltage of 1.65-1.8V, the following effect of the output voltage and the input voltage of the operational amplifier is slightly poorer, and the operational amplifier accords with the characteristics of a rail-to-rail input and rail-to-rail output circuit in a general concept.
As shown in fig. 5, a waveform diagram of an ac simulation of the structure of fig. 3 is shown. In the simulation, the power supply Voltage (VCC) was set to 1.8V and the ground voltage (GND) was set to 0V. The ac characteristics of the circuit at 0.9V common mode voltage input are shown in the figure, where the (1) curve is the amplitude versus frequency characteristic curve, the (2) curve is the phase versus frequency characteristic curve, and the ac characteristics of the circuit at 0.15V and 1.65V common mode voltage input are summarized in table one. As can be seen from the figures and table one: the low-frequency gain of the operational amplifier circuit is 75.5dB, 80.5dB and 76.4dB under the common-mode voltage input conditions of 0.15V, 0.9V and 1.65V, the unit gain bandwidths are 17.1MHz, 16.8MHz and 18.6MHz respectively, and the phase margins are 75 DEG, 73 DEG and 70 deg respectively. Therefore, under the price adjustment of different input common-mode voltages, the performance indexes of the circuit have small difference, and the stability of the performance of the circuit under different input common-mode voltages is shown.
List one
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.
Claims (10)
1. A rail-to-rail operational amplifier circuit, comprising:
a rail-to-rail input stage for receiving an input signal and outputting a first signal in dependence on the input signal;
a constant transconductance compensation stage for controlling the transconductance of the input stage to be constant;
the cascode stage is used for generating a second signal according to the first signal; and
the rail-to-rail output stage is used for generating an output signal of the rail-to-rail operational amplification circuit according to the second signal;
the method is characterized in that the cascode stage comprises:
a cascode circuit comprising: the first branch and the second branch which form a differential structure are used for generating a second signal according to the first signal; and
a current compensation circuit comprising: and the third branch is used for extracting current from the constant transconductance compensation stage, and the fourth branch and the fifth branch are used for mirroring the current of the third branch so as to compensate the current of the first branch and the second branch by using the mirrored current to control the output current of the cascode stage to be constant.
2. The rail-to-rail operational amplifier circuit of claim 1, wherein the rail-to-rail input stage comprises: the first differential output port and the second differential output port are respectively used for outputting a first differential signal and a second differential signal;
the first branch includes: first to fourth transistors connected in series between a power supply voltage and ground, the second branch including: fifth to eighth transistors connected in series between a power supply voltage and ground, wherein gates of the first and fifth transistors are connected to a first bias voltage, gates of the second and sixth transistors are connected to a second bias voltage, gates of the third and seventh transistors are connected to a fourth bias voltage, and gates of the fourth and eighth transistors are connected to a connection point of the second and third transistors;
the connection point of the first transistor and the second transistor, and the connection point of the fifth transistor and the sixth transistor are respectively connected with two ports of the first differential output ports to receive the first differential signal;
the connection point of the third transistor and the fourth transistor, and the connection point of the seventh transistor and the eighth transistor are respectively connected with two ports of the second differential output ports to receive the second differential signal;
wherein the junction of the sixth and seventh transistors serves as the output port of the cascode stage.
3. The rail-to-rail operational amplifier circuit of claim 2, wherein the first, second, fifth and sixth transistors are P-type field effect transistors and the third, fourth, seventh and eighth transistors are N-type field effect transistors.
4. The rail-to-rail operational amplifier circuit of claim 2, wherein the fourth branch is in parallel with the first transistor and the fifth branch is in parallel with the fifth transistor.
5. The rail-to-rail operational amplifier circuit of claim 4, wherein the fourth branch comprises: a ninth transistor, the fifth branch including: and a tenth transistor connected in series between a power supply voltage and a connection point of the first and second transistors, the tenth transistor being connected in series between the power supply voltage and the connection point of the fifth and sixth transistors, gates of the ninth and tenth transistors being connected to a fifth bias voltage.
6. The rail-to-rail operational amplifier circuit of claim 5, wherein the third branch comprises: an eleventh and twelfth transistor connected in series between the supply voltage and ground, the gate of the eleventh transistor being connected to the fifth bias voltage and to a connection point of the eleventh and twelfth transistors, the twelfth transistor being connected to the constant transconductance compensation stage.
7. The rail-to-rail operational amplifier circuit of claim 6, wherein the ninth through eleventh transistors are P-type field effect transistors and the twelfth transistor is an N-type field effect transistor.
8. Rail-to-rail operational amplifier circuit according to any of the claims 1 to 7, characterized in that the rail-to-rail output stage employs a classical class AB amplifier structure based on an inverter.
9. The rail-to-rail operational amplifier circuit of claim 8, wherein the rail-to-rail output stage further comprises: an RC compensation branch connected between the input and output ports of the rail-to-rail output stage.
10. The rail-to-rail operational amplifier circuit of claim 1, wherein the rail-to-rail input stage comprises: the differential input port, the N-type transistors and the P-type transistors are connected with two ports of the differential input port respectively, the two gates of the P-type transistors are connected with two ports of the differential input port respectively, two drains of the N-type transistors are used as one differential output port of the rail-to-rail input stage, and two drains of the P-type transistors are used as the other differential output port of the rail-to-rail input stage.
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| JP2014204292A (en) * | 2013-04-04 | 2014-10-27 | 富士電機株式会社 | Operational amplification circuit |
| US11171619B2 (en) * | 2019-04-24 | 2021-11-09 | Stmicroelectronics International N.V. | Transconductance boosted cascode compensation for amplifier |
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