CN107301308A - A kind of Permeate flow full swing operational amplifier - Google Patents
A kind of Permeate flow full swing operational amplifier Download PDFInfo
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- CN107301308A CN107301308A CN201710699203.8A CN201710699203A CN107301308A CN 107301308 A CN107301308 A CN 107301308A CN 201710699203 A CN201710699203 A CN 201710699203A CN 107301308 A CN107301308 A CN 107301308A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45376—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using junction FET transistors as the active amplifying circuit
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The present invention relates to a kind of Permeate flow full swing operational amplifier, rail-to-rail input stage, gain stage and the output stage connect including being sequentially connected, rail-to-rail input stage includes complementary PMOS differential pair and nmos differential to the tail current source of, PMOS differential pair and nmos differential pair, the load circuit of nmos differential pair；Gain stage includes automatic biasing common-source common-gate current mirror, the source electrode connection automatic biasing common-source common-gate current mirror of the PMOS and NMOS tube of PMOS differential pair and nmos differential pair, output stage includes the first PMOS that common source connects and the first NMOS tube, miller-compensated, the grid connection automatic biasing common-source common-gate current mirror of first PMOS and the first NMOS tube, miller-compensated use miller-compensated electric capacity and compensation resistant series are realized.This operational amplifier can effectively ensure that input stage mutual conductance is constant in full voltage working range, and the stability of whole circuit structure is good, has also widened the operating voltage range of amplifier, available for low pressure applications, while also improving the common-mode rejection ratio of amplifier.
Description
Technical field
The present invention relates to IC design field, a kind of operational amplifier is concretely related to, more particularly to it is a kind of
Rail-to-rail folded common source and common grid across leading full swing operational amplifier.
Background technology
Traditional rail-to-rail operational amplifier is using complementary PMOS and nmos differential to as input stage, its structure is as schemed
Shown in 1, wherein, M2 and M3 are PMOS Differential Inputs pair, and M1 and M4 are nmos differential input pair.So, in relatively low input electricity
In the range of pressure, PMOS Differential Inputs are to work, and nmos differential is to shut-off；In higher input voltage range, nmos differential is defeated
Enter to work, PMOS differential pair shut-off；Only in middle input voltage range, NMOS, PMOS differential pair work simultaneously.From
And, total common-mode input range is obtained for full swing VSS＜ VCM＜ VDD。
However, because the input stage of the rail-to-rail operational amplifier of this structure has three kinds of working conditions：PMOS or NMOS
Work independently and work simultaneously, therefore, the problem of mutual conductance has non-constant.This allows for unity gain bandwidth and varied widely
When can bring difficulty to frequency compensation.The curve that input stage equivalent transconductance changes with input common mode voltage is illustrated in figure 2, from figure
In it can be seen that mutual conductance maximum in gamut has changed 2 times, this influence to common-mode rejection ratio and stability is quite big
's.
The content of the invention
It is an object of the invention to provide a kind of Permeate flow full swing operational amplifier, the overall structure of the operational amplifier
It is ingenious in design, be improved by the input stage circuit structure to operational amplifier, it is ensured that full swing operational amplifier it is defeated
Enter that grade mutual conductance is constant in full power supply voltage working range, the stability of whole circuit structure is good, and maximum output pendulum
Width is close to full power supply voltage scope 0-VDD。
To achieve these goals, the technical solution adopted by the present invention is that a kind of Permeate flow full swing operational amplifier is wrapped
Rail-to-rail input stage, gain stage and the output stage for being sequentially connected and connecing are included, the rail-to-rail input stage includes complementary PMOS difference
Pair and nmos differential to the tail current source of, PMOS differential pair and nmos differential pair, the load circuit of nmos differential pair, the PMOS
Differential pair realizes that the grid of one of PMOS, which is drawn, is used as operational amplifier using the PMOS of two common source connections
In-phase input end, the grid of another PMOS draws the inverting input as operational amplifier, and the nmos differential is to adopting
The NMOS tube connected with two common sources realizes that the grid of one of NMOS tube draws the homophase input as operational amplifier
End, the grid of another NMOS tube draws the inverting input as operational amplifier, the tail current source of the PMOS differential pair
The source electrode and supply voltage VDD of the PMOS of PMOS differential pair are connected, the tail current source connection NMOS of the nmos differential pair is poor
Point to NMOS tube source electrode and ground, the tail current source of the PMOS differential pair and the tail current source passing ratio of nmos differential pair
Current mirror is connected, the drain electrode of the load circuit connection nmos differential pair of the nmos differential pair and supply voltage VDD；It is described to increase
Beneficial level includes automatic biasing common-source common-gate current mirror, the drain electrode connection automatic biasing cascade electricity of the NMOS tube of the nmos differential pair
Mirror is flowed, automatic biasing common-source common-gate current mirror connection supply voltage VDD, the output stage includes the first PMOS that common source is connected
With the first NMOS tube, miller-compensated, the grid connection bias voltage Vb of first PMOS, the grid connection of the first NMOS tube
The output of gain stage, the miller-compensated use miller-compensated electric capacity and compensation resistant series realize that two compensation resistance are distinguished
The two ends of automatic biasing common-source common-gate current mirror are connected, miller-compensated electric capacity connects the drain electrode of the first PMOS and the first NMOS tube,
The output end as operational amplifier is drawn in the drain electrode of first PMOS and the first NMOS tube, and the source electrode of the first PMOS connects
Meet supply voltage VDD, the source ground of the first NMOS tube.
As a modification of the present invention, the tail current source of the PMOS differential pair uses the second PMOS, the NMOS
The tail current source of differential pair uses the second NMOS tube, and electricity is provided between PMOS differential pair and the tail current source of nmos differential pair
Stream extracts duplicate circuit, and the current draw duplicate circuit includes the 3rd PMOS, regulation and control resistance, by the 3rd NMOS tube and the 4th
The current mirror of NMOS tube composition, the source electrode of the 3rd PMOS connects the drain electrode of the second PMOS, the drain electrode of the 3rd PMOS
One end of connection regulation and control resistance, the other end of regulation and control resistance connects the drain and gate of the 3rd NMOS tube, the source of the 3rd NMOS tube
Pole is grounded, the source ground of the 4th NMOS tube, and the grid of the 3rd NMOS tube connects the grid of the 4th PMOS, the 2nd PMOS
The source electrode of the PMOS of the drain electrode connection PMOS differential pair of pipe, source electrode connection the supply voltage VDD, the 2nd PMOS of the second PMOS
The grid connection bias voltage Vb of pipe, the source ground of the second NMOS tube, the drain electrode connection nmos differential pair of the second NMOS tube
The source electrode of NMOS tube.
As a modification of the present invention, the load circuit of the nmos differential pair includes the 4th PMOS, the 5th PMOS
Pipe and the 6th PMOS, the 5th PMOS and the 6th PMOS are used as the load of nmos differential pair, the 4th PMOS
Biasing is provided for the 5th PMOS and the 6th PMOS, the source electrode of the 4th to the 6th PMOS connects supply voltage VDD, the
The grid of four PMOSs connects the grid of the 5th PMOS, and the grid of the 5th PMOS connects the grid of the 6th PMOS, the 4th
The grid of PMOS connects the drain electrode of the 4th NMOS tube, and the drain electrode of the 5th PMOS and the 6th PMOS connects nmos differential pair
The drain electrode of NMOS tube.
As a modification of the present invention, the first bias voltage is connected with the grid of the 3rd PMOS electricity is provided
Road, first bias voltage, which provides circuit, includes the 7th PMOS and the 8th PMOS, and the source electrode of the 7th PMOS connects
Supply voltage VDD is met, the grid of the 7th PMOS connects the grid of the 8th PMOS, the drain electrode connection the 8th of the 7th PMOS
The source electrode of PMOS, the grid of the 8th PMOS connects the grid of the 3rd PMOS.
As a modification of the present invention, the gain stage also includes automatic biasing cascode current source, the automatic biasing
Common-source common-gate current mirror includes the 9th PMOS, the tenth PMOS, the 11st PMOS, the 9th NMOS tube, the tenth NMOS tube, the
12 PMOSs, the 13rd PMOS, the 14th PMOS and the 15th PMOS, the automatic biasing cascode current source bag
Include the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th PMOS, the tenth PMOS, the tenth
Source electrode connection the supply voltage VDD, the 9th PMOS, the 12nd PMOS, the 14th PMOS of two PMOSs, the 13rd PMOS
The grid connection bias voltage Vb of pipe, the drain electrode of drain electrode the 9th NMOS tube of connection of the 9th PMOS, the drain electrode of the tenth PMOS
Connect the source electrode of the 11st PMOS, the drain electrode of drain electrode the tenth NMOS tube of connection of the 11st PMOS, the grid of the tenth PMOS
Pole connects the drain electrode of the 11st PMOS, the source electrode of drain electrode the 13rd PMOS of connection of the 12nd PMOS, the 14th PMOS
The source electrode of drain electrode the 15th PMOS of connection of pipe, the grid of the 11st PMOS connects the 13rd PMOS and the 15th PMOS
The grid of the grid of pipe, the grid of drain electrode the first NMOS tube of connection of the 15th PMOS, the 5th NMOS tube and the 6th NMOS tube
It is connected, the 7th NMOS tube is connected with the grid of the 8th NMOS tube, and the 9th NMOS tube is connected with the grid of the tenth NMOS tube, the 5th
The source electrode of NMOS tube connects the drain electrode of the 7th NMOS tube, and the source electrode of the 6th NMOS tube connects the drain electrode of the 8th NMOS tube, the 7th
The source ground of NMOS tube and the 8th NMOS tube and the 9th NMOS tube and the tenth NMOS tube；12nd PMOS and the 14th
The drain electrode of PMOS connects the drain electrode of the NMOS tube of nmos differential pair, the source electrode connection of the 5th NMOS tube and the 6th NMOS tube respectively
The drain electrode of the PMOS of PMOS differential pair.
As a modification of the present invention, the offer of the second bias voltage is connected with the automatic biasing common-source common-gate current mirror
Circuit, described have the second bias voltage to provide circuit to include the 11st NMOS tube, the grid connection the of the 11st NMOS tube
The grid of nine NMOS tubes and the tenth NMOS tube, the drain electrode of drain electrode the 8th PMOS of connection of the 11st NMOS tube, the 11st NMOS
The source ground of pipe.
As a modification of the present invention, the miller-compensated quantity is 2, including the first miller-compensated electric capacity, the
One compensation resistance, the second miller-compensated electric capacity and the second compensation resistance, first miller-compensated electric capacity and the first compensation resistance
Series connection, second miller-compensated electric capacity and the second compensation resistant series, the first compensation resistance connection supply voltage VDD, second
The drain electrode that resistance connects the 15th PMOS is compensated, the first miller-compensated electric capacity and the second miller-compensated electric capacity connect the first PMOS
The drain electrode of pipe and the first NMOS tube.
Relative to prior art, the circuit structure of Permeate flow full swing operational amplifier proposed by the invention is by rail-to-rail
Input stage, the gain stage of cascade and output stage composition, by complementary PMOS and nmos differential in rail-to-rail input stage
To realizing the full swing 0-VDD of common-mode input range, then made using automatic biasing common-source common-gate current mirror for intermediate gain level
For load, so than traditional cascade operational amplifier working range more than twice of overdrive voltage VON(this crosses drive
Dynamic voltage is gate source voltage VGSWith threshold voltage VTDifference), output stage use common-source stage connect PMOS and NMOS tube
And the miller-compensated realization being made up of miller-compensated electric capacity and compensation resistant series, it may be such that whole circuit structure reaches well
Stability and maximum output voltage swing close to full power supply voltage scope 0-VDD, effectively widened the work of operational amplifier
Voltage range, makes it can be used for low pressure applications occasion.In addition, the rail-to-rail input stage in this operational amplifier also uses second
PMOS is being worked as the tail current source of PMOS differential pair and using tail current source of second NMOS tube as nmos differential pair
Common mode incoming level VCMWhen increasing to a certain extent, the second PMOS is opened, the benchmark for allowing the second PMOS to be introduced from outside into
Current source IrefExtract electric current and the second NMOS tube is copied under the regulating and controlling effect of current draw duplicate circuit so that PMOS is poor
Point pair and nmos differential to either work independently or simultaneously work, both is tail current and constant so that input
The equivalent transconductance of level is constant, effectively increases the common-mode rejection ratio of operational amplifier.
Brief description of the drawings
Fig. 1 is the structure chart of traditional rail-to-rail operational amplifier.
The curve that Fig. 2 changes for the input stage equivalent transconductance of traditional rail-to-rail operational amplifier with input common mode voltage
Figure.
Fig. 3 is the present invention across the circuit structure diagram for leading full swing operational amplifier.
Fig. 4 is the present invention across the input stage simplified electrical circuit diagram for leading full swing operational amplifier.
Fig. 5 is inputted across leading the mutual conductance constant in full operating range of full swing operational amplifier for the present invention's with common mode
The curve map of voltage change.
Embodiment
In order to deepen the understanding of the present invention and understanding, the invention will be further described below in conjunction with the accompanying drawings and introduces.
As shown in Figures 3 and 4, a kind of Permeate flow full swing operational amplifier, including be sequentially connected connect rail-to-rail input stage,
Gain stage and output stage, the rail-to-rail input stage include complementary PMOS differential pair and nmos differential to, PMOS differential pair and
The tail current source of nmos differential pair, the load circuit of nmos differential pair, the PMOS differential pair are connected using two common sources
PMOS M5 and M6 realize that wherein PMOS M5 grid draws the in-phase input end as operational amplifier, PMOS M6's
Grid draws the inverting input as operational amplifier, and the nmos differential is to the NMOS tube using two common source connections
M12 and M14 realizes that wherein NMOS tube M12 grid draws the in-phase input end as operational amplifier, NMOS tube M14 grid
The inverting input as operational amplifier is drawn in pole, and the tail current source of the PMOS differential pair connects the PMOS of PMOS differential pair
The source electrode and supply voltage VDD of pipe, the nmos differential pair tail current source connection nmos differential pair NMOS tube source electrode and
Ground, the tail current source of the PMOS differential pair is connected with the tail current source passing ratio current mirror of nmos differential pair, described
The drain electrode of the load circuit connection nmos differential pair of nmos differential pair and supply voltage VDD；The gain stage is common including automatic biasing
Source source common-gate current mirror, the drain electrode connection automatic biasing common-source common-gate current mirror of NMOS tube M12, M14 of the nmos differential pair, self-bias
Common-source common-gate current mirror connection supply voltage VDD is put, the output stage includes the first PMOS M29 and first that common source is connected
NMOS tube M30, miller-compensated, the grid connection bias voltage Vb of the first PMOS M29, the first NMOS tube M30 grid
The output of gain stage is connected, the miller-compensated use miller-compensated electric capacity and compensation resistant series are realized, two compensation resistance
The two ends of automatic biasing common-source common-gate current mirror are connected respectively, while two compensation resistance also respectively connected bias voltage Vb and increasing
The output of beneficial level, miller-compensated electric capacity connects the first PMOS M29 and the first NMOS tube M30 drain electrode, first PMOS
The output end as operational amplifier, the first PMOS M29 source electrode connection electricity are drawn in M29 and the first NMOS tube M30 drain electrode
Source voltage VDD, the first NMOS tube M30 source ground.Operational amplifier proposed by the invention is in input stage by complementation
PMOS and nmos differential are to realizing the full swing 0-V of common-mode input rangeDD, automatic biasing cascade is used in intermediate gain level
Current mirror has done more than the working range of the traditional cascade amplifier of duty factor twice of overdrive voltage VON(it is gate source voltage VGS
With threshold voltage VTDifference), and the PMOS and NMOS tube and by miller-compensated electricity connected in output stage using common-source stage
Hold and compensate the miller-compensated realization of resistant series composition, may be such that whole circuit structure reaches good stability and maximum
Output voltage swing has effectively widened the operating voltage range of operational amplifier, it is used close to full power supply voltage scope 0-VDD
In low pressure applications occasion.
It is preferred that, the tail current source of the PMOS differential pair uses the second PMOS M4, the tail electricity of the nmos differential pair
Stream source uses the second NMOS tube M15, and current draw is provided between PMOS differential pair and the tail current source of nmos differential pair and is answered
Circuit processed, the current draw duplicate circuit includes the 3rd PMOS M7, regulation and control resistance R, by the 3rd NMOS tube M8 and the 4th
The current mirror of NMOS tube M9 compositions, the source electrode of the 3rd PMOS M7 connects the second PMOS M4 drain electrode, the 3rd PMOS
M7 drain electrode connection regulation and control resistance R one end, the regulation and control resistance R other end connects the 3rd NMOS tube M8 drain and gate, the
Three NMOS tube M8 source ground, the 4th NMOS tube M9 source ground, the 3rd NMOS tube M8 grid connects the 4th NMOS tube
M9 grid, the source electrode of the PMOS of the drain electrode connection PMOS differential pair of the second PMOS M4, the second PMOS M4 source
Pole connection supply voltage VDD, the second PMOS M4 grid connection bias voltage Vb, the second NMOS tube M15 source ground, the
The source electrode of the NMOS tube of two NMOS tube M15 drain electrode connection nmos differential pair.Therefore, in the rail-to-rail input of this operational amplifier
Level is also used as nmos differential pair using the second PMOS as the tail current source of PMOS differential pair and using the second NMOS tube
Tail current source, as common mode incoming level VCMWhen increasing to a certain extent, the second PMOS is opened, the second PMOS is allowed from outer
The reference current source I that portion is introducedrefExtract electric current and the 2nd NMOS is copied under the regulating and controlling effect of current draw duplicate circuit
Pipe so that PMOS differential pair and nmos differential are to either working independently or working simultaneously, and both is tail current and constant,
So that the equivalent transconductance of input stage is constant, the common-mode rejection ratio of operational amplifier is effectively increased.Wherein, current draw is multiple
Regulation and control resistance R in circuit processed is used to regulate and control to extract the size of electric current, and the 3rd NMOS tube M8 and the 4th NMOS tube M9 compositions
The ratio of current mirror is used for the size for regulating and controlling to copy to the second NMOS tube M15 electric current.
It may further be preferable that the load circuit of the nmos differential pair includes the 4th PMOS M10, the 5th PMOS
M11 and the 6th PMOS M13, the 5th PMOS M11 and the 6th PMOS M13 as nmos differential pair load, it is described
4th PMOS M10 provides biasing, the 4th PMOS M10, the 5th PMOS for the 5th PMOS M11 and the 6th PMOS M13
M11 and the 6th PMOS M13 constitutes current mirror, and the source electrode of the 4th to the 6th PMOS connects supply voltage VDD, the 4th
PMOS M10 grid connects the 5th PMOS M11 grid, and the 5th PMOS M11 grid connects the 6th PMOS M13's
Grid, the 4th PMOS M10 the 4th NMOS tube M9 of grid connection drain electrode, the 5th PMOS M11 and the 6th PMOS M13's
The drain electrode of the NMOS tube of drain electrode connection nmos differential pair.
It is even furthermore preferable that the first bias voltage is connected with the grid of the 3rd PMOS M7 provides circuit,
First bias voltage, which provides circuit, includes the 7th PMOS M1 and the 8th PMOS M2, the source electrode of the 7th PMOS M1
The grid for connecting supply voltage VDD, the 7th PMOS M1 connects the 8th PMOS M2 grid, and the 7th PMOS M1 drain electrode connects
The 8th PMOS M2 source electrode is connect, the 8th PMOS M2 grid connects the 3rd PMOS M7 grid.In figure 3, the 3rd
PMOS M7 bias voltage Vb1There is provided jointly by Fig. 4 M1 and M2.
It is even furthermore preferable that the gain stage also includes automatic biasing cascode current source, the automatic biasing common source
Source common-gate current mirror includes the 9th PMOS M16, the tenth PMOS M17, the 11st PMOS M18, the 9th NMOS tube M19, the tenth
NMOS tube M20, the 12nd PMOS M21, the 13rd PMOS M22, the 14th PMOS M23 and the 15th PMOS M24, institute
Stating automatic biasing cascode current source includes the 5th NMOS tube M25, the 6th NMOS tube M26, the 7th NMOS tube M27, the 8th NMOS
Pipe M28, the 9th PMOS M16, the tenth PMOS M17, the 12nd PMOS M21, the 13rd PMOS M22 source electrode connect
Connect supply voltage VDD, the 9th PMOS M16, the 12nd PMOS M21, the 14th PMOS M23 grid connection bias voltage
Vb, the 9th PMOS M16 the 9th NMOS tube M19 of drain electrode connection drain electrode, the tenth PMOS M17 drain electrode connection the 11st
PMOS M18 source electrode, the 11st PMOS M18 the tenth NMOS tube M20 of drain electrode connection drain electrode, the tenth PMOS M17's
Grid connects the 11st PMOS M18 drain electrode, and the 12nd PMOS M21 drain electrode connects the 13rd PMOS M22 source electrode,
14th PMOS M23 the 15th PMOS M24 of drain electrode connection source electrode, the 11st PMOS M18 grid connection the tenth
Three PMOS M22 and the 15th PMOS M24 grid, the 15th PMOS M24 the first NMOS tube M30 of drain electrode connection grid
Pole, the 5th NMOS tube M25 and the 6th NMOS tube M26 grid are connected, the 7th NMOS tube M27 and the 8th NMOS tube M28 grid
It is connected, the 9th NMOS tube M19 and the tenth NMOS tube M20 grid are connected, the 5th NMOS tube M25 source electrode connects the 7th NMOS tube
M27 drain electrode, the 6th NMOS tube M26 source electrode connects the 8th NMOS tube M28 drain electrode, the 7th NMOS tube M27 and the 8th NMOS
Pipe M28 and the 9th NMOS tube M19 and the tenth NMOS tube M20 source ground；12nd PMOS M21 and the 14th PMOS
M23 drain electrode connects the source electrode of the drain electrode of the NMOS tube of nmos differential pair, the 5th NMOS tube M25 and the 6th NMOS tube M26 respectively
Connect the drain electrode of the PMOS of PMOS differential pair.The 9th NMOS tube M19 and the tenth NMOS tube M20 is first biased electrical
Pressure provides circuit and provides biasing, the 12nd PMOS M21, the 13rd PMOS M22, the 14th PMOS M23 and the tenth
Five PMOS M24 constitute the load current source of gain stage, and the automatic biasing common-source common-gate current mirror provides for the load current source
Biasing.
It is even furthermore preferable that the second bias voltage is connected with the automatic biasing common-source common-gate current mirror provides electricity
Road, described to have the second bias voltage offer circuit to include the 11st NMOS tube M3, the grid of the 11st NMOS tube M3 is connected
9th NMOS tube M19 and the tenth NMOS tube M20 grid, the 11st NMOS tube M3 the 8th PMOS M2 of drain electrode connection leakage
Pole, the 11st NMOS tube M3 source ground.
It is even furthermore preferable that the miller-compensated quantity is 2, including the first miller-compensated electric capacity C1, first
Compensate resistance R1, the second miller-compensated electric capacity C2 and the second compensation resistance R2, the first miller-compensated electric capacity C1 and first is mended
Repay resistance R1 series connection, the compensation resistance R2 series connection of the second miller-compensated electric capacity C2 and second, the first compensation resistance R1 connection electricity
Source voltage VDD, the PMOS M24 of the second compensation resistance R2 connections the 15th drain electrode, the first miller-compensated electric capacity C1 and second meter
Strangle compensating electric capacity C2 connections the first PMOS M29 and the first NMOS tube M30 drain electrode.
As common mode incoming level VCMDuring close to ground, only PMOS differential pair works, and the equivalent transconductance of input stage is
And as common mode incoming level VCMDuring close to supply voltage VDD, only nmos differential to work, input stage it is equivalent
Mutual conductance is
And as common mode incoming level VCMDuring in medium voltage, PMOS, nmos differential pair work simultaneously, input stage it is equivalent
Mutual conductance is
Wherein, CoxIt is the gate oxide capacitance of unit area；For transistor M5, M6, M12, M14 breadth length ratio；μn、μp
The respectively mobility of electronics and hole；In、IpElectric current when respectively only NMOS and PMOS differential pair work independently；And In′
And Ip' it is NMOS and PMOS differential pair while electric current when working.
Because μnHigher than μp, therefore design current mirror replica current is certain proportion (xI8=I9) (x is proportionality coefficient) make
It can obtain mutual conductance constant in full operating range as shown in Figure 5.Wherein, Ip
=Iref, In=xIp, I 'n=x (Iref-Ip)。
In the claims, word "comprising" does not exclude the presence of element not listed in the claims.Word first, second
And third use does not indicate that any order, these words can be construed to title.
Technological means disclosed in the present invention program is not limited only to the technological means disclosed in above-mentioned embodiment, in addition to
Constituted technical scheme is combined by above technical characteristic.It should be pointed out that for those skilled in the art
For, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications are also considered as
Protection scope of the present invention.
Claims (7)
1. a kind of Permeate flow full swing operational amplifier, it is characterised in that：The rail-to-rail input stage that is connect including being sequentially connected, gain
Level and output stage, the rail-to-rail input stage include complementary PMOS differential pair and nmos differential to, PMOS differential pair and NMOS
The tail current source of differential pair, the load circuit of nmos differential pair, the PMOS that the PMOS differential pair is connected using two common sources
Pipe realizes that the grid of one of PMOS draws the in-phase input end as operational amplifier, the grid of another PMOS
The inverting input as operational amplifier is drawn, the nmos differential is realized to the NMOS tube using two common source connections,
The grid of one of NMOS tube draws the in-phase input end as operational amplifier, and the grid of another NMOS tube draws conduct
The inverting input of operational amplifier, the PMOS differential pair tail current source connection PMOS differential pair PMOS source electrode and
Supply voltage VDD, the source electrode and ground of the NMOS tube of the tail current source connection nmos differential pair of the nmos differential pair, the PMOS
The tail current source of differential pair is connected with the tail current source passing ratio current mirror of nmos differential pair, and the nmos differential is to bearing
Carry drain electrode and the supply voltage VDD of circuit connection nmos differential pair；The gain stage includes automatic biasing common-source common-gate current mirror, institute
State the drain electrode connection automatic biasing common-source common-gate current mirror of the NMOS tube of nmos differential pair, automatic biasing common-source common-gate current mirror connection electricity
Source voltage VDD, the output stage includes the first PMOS that common source connects and the first NMOS tube, miller-compensated, and described first
The grid connection bias voltage Vb of PMOS, the grid of the first NMOS tube connects the output of gain stage, the miller-compensated use
Miller-compensated electric capacity and compensation resistant series realize that two compensation resistance connect the two of automatic biasing common-source common-gate current mirror respectively
End, miller-compensated electric capacity connects the drain electrode of the first PMOS and the first NMOS tube, first PMOS and the first NMOS tube
The output end as operational amplifier, the source electrode connection supply voltage VDD of the first PMOS, the source of the first NMOS tube are drawn in drain electrode
Pole is grounded.
2. a kind of Permeate flow full swing operational amplifier as claimed in claim 1, it is characterised in that the PMOS differential pair
Tail current source uses the second PMOS, and the tail current source of the nmos differential pair uses the second NMOS tube, in PMOS differential pair and
Current draw duplicate circuit is provided between the tail current source of nmos differential pair, the current draw duplicate circuit includes the 3rd
PMOS, regulation and control resistance, the current mirror being made up of the 3rd NMOS tube and the 4th NMOS tube, the source electrode connection of the 3rd PMOS
The drain electrode of second PMOS, one end of the drain electrode connection regulation and control resistance of the 3rd PMOS, the other end connection the 3rd of regulation and control resistance
The drain and gate of NMOS tube, the source ground of the 3rd NMOS tube, the source ground of the 4th NMOS tube, the grid of the 3rd NMOS tube
Connect the grid of the 4th NMOS tube, the source electrode of the PMOS of the drain electrode connection PMOS differential pair of second PMOS, second
The source electrode connection supply voltage VDD of PMOS, the grid connection bias voltage Vb of the second PMOS, the source electrode of the second NMOS tube connects
Ground, the source electrode of the NMOS tube of the drain electrode connection nmos differential pair of the second NMOS tube.
3. a kind of Permeate flow full swing operational amplifier as claimed in claim 2, it is characterised in that the 5th PMOS and
6th PMOS is as the load of nmos differential pair, and the 4th PMOS is that the 5th PMOS and the 6th PMOS are provided partially
Put, the source electrode connection supply voltage VDD of the 4th to the 6th PMOS, the grid of the 4th PMOS connects the 5th PMOS
Grid, the grid of the 5th PMOS connects the grid of the 6th PMOS, and the grid of the 4th PMOS connects the leakage of the 4th NMOS tube
The drain electrode of the NMOS tube of the drain electrode connection nmos differential pair of pole, the 5th PMOS and the 6th PMOS.
4. a kind of Permeate flow full swing operational amplifier as claimed in claim 2 or claim 3, it is characterised in that the 3rd PMOS
The first bias voltage is connected with the grid of pipe circuit is provided, first bias voltage provide circuit include the 7th PMOS and
8th PMOS, the source electrode connection supply voltage VDD of the 7th PMOS, the grid of the 7th PMOS connects the 8th PMOS
Grid, the source electrode of drain electrode the 8th PMOS of connection of the 7th PMOS, the grid of the 8th PMOS connects the 3rd PMOS
Grid.
5. a kind of Permeate flow full swing operational amplifier as claimed in claim 4, it is characterised in that the gain stage also includes
Automatic biasing cascode current source, the automatic biasing common-source common-gate current mirror includes the 9th PMOS, the tenth PMOS, the 11st
PMOS, the 9th NMOS tube, the tenth NMOS tube, the 12nd PMOS, the 13rd PMOS, the 14th PMOS and the 15th
PMOS, the automatic biasing cascode current source includes the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS
The source electrode connection supply voltage VDD of pipe, the 9th PMOS, the tenth PMOS, the 12nd PMOS, the 13rd PMOS,
9th PMOS, the 12nd PMOS, the grid connection bias voltage Vb of the 14th PMOS, the drain electrode connection of the 9th PMOS
The drain electrode of 9th NMOS tube, the source electrode of drain electrode the 11st PMOS of connection of the tenth PMOS, the drain electrode of the 11st PMOS connects
The drain electrode of the tenth NMOS tube is connect, the grid of the tenth PMOS connects the drain electrode of the 11st PMOS, the drain electrode of the 12nd PMOS
Connect the source electrode of the 13rd PMOS, the source electrode of drain electrode the 15th PMOS of connection of the 14th PMOS, the 11st PMOS
Grid connect the grid of the 13rd PMOS and the 15th PMOS, drain electrode the first NMOS tube of connection of the 15th PMOS
Grid, the 5th NMOS tube is connected with the grid of the 6th NMOS tube, and the 7th NMOS tube is connected with the grid of the 8th NMOS tube, and the 9th
NMOS tube is connected with the grid of the tenth NMOS tube, and the source electrode of the 5th NMOS tube connects the drain electrode of the 7th NMOS tube, the 6th NMOS tube
Source electrode connect the drain electrode of the 8th NMOS tube, the 7th NMOS tube and the 8th NMOS tube and the 9th NMOS tube and the tenth NMOS tube
Source ground；
The drain electrode of 12nd PMOS and the 14th PMOS connects the drain electrode of the NMOS tube of nmos differential pair, the 5th NMOS respectively
The drain electrode of the PMOS of pipe and the source electrode of the 6th NMOS tube connection PMOS differential pair.
6. a kind of Permeate flow full swing operational amplifier as claimed in claim 5, it is characterised in that the automatic biasing common source is total to
The second bias voltage is connected with cascode current mirror circuit is provided, it is described to there is the second bias voltage offer circuit to include the 11st NMOS
Pipe, the grid of the 11st NMOS tube connects the grid of the 9th NMOS tube and the tenth NMOS tube, the drain electrode of the 11st NMOS tube
Connect the drain electrode of the 8th PMOS, the source ground of the 11st NMOS tube.
7. a kind of Permeate flow full swing operational amplifier as claimed in claim 6, it is characterised in that the miller-compensated number
Measure as 2, including the first miller-compensated electric capacity, the first compensation resistance, the second miller-compensated electric capacity and the second compensation resistance, it is described
First miller-compensated electric capacity and the first compensation resistant series, second miller-compensated electric capacity and the second compensation resistant series, the
One compensation resistance connection supply voltage VDD, the second compensation resistance connects the drain electrode of the 15th PMOS, the first miller-compensated electric capacity
The drain electrode of the first PMOS and the first NMOS tube is connected with the second miller-compensated electric capacity.
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| CN201710699203.8A CN107301308B (en) | 2017-08-15 | 2017-08-15 | Constant transconductance full-swing operational amplifier |
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| CN109167583A (en) * | 2018-10-31 | 2019-01-08 | 上海海栎创微电子有限公司 | Trsanscondutance amplifier |
| CN109361365A (en) * | 2018-12-18 | 2019-02-19 | 天津三源兴泰微电子技术有限公司 | A kind of difference amplifier of high-gain low-noise |
| CN109546975A (en) * | 2019-01-29 | 2019-03-29 | 苏州大学 | Operation transconductance amplifier |
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| CN117498810A (en) * | 2023-11-16 | 2024-02-02 | 湖南进芯电子科技有限公司 | Input-output rail-to-rail constant transconductance constant gain constant noise operational amplifier |
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| CN109167583A (en) * | 2018-10-31 | 2019-01-08 | 上海海栎创微电子有限公司 | Trsanscondutance amplifier |
| CN109361365B (en) * | 2018-12-18 | 2023-10-13 | 天津三源兴泰微电子技术有限公司 | High-gain low-noise differential amplifier |
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| CN110798163A (en) * | 2019-12-02 | 2020-02-14 | 苏州大学 | Wide-swing unit-gain voltage buffer |
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| CN113141160B (en) * | 2021-05-24 | 2023-08-08 | 天津中科新显科技有限公司 | General rail-to-rail input buffer circuit |
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