CN104218904A - Rail-to-rail-input AB-class-output full-differential operational amplifier - Google Patents
Rail-to-rail-input AB-class-output full-differential operational amplifier Download PDFInfo
- Publication number
- CN104218904A CN104218904A CN201310208076.9A CN201310208076A CN104218904A CN 104218904 A CN104218904 A CN 104218904A CN 201310208076 A CN201310208076 A CN 201310208076A CN 104218904 A CN104218904 A CN 104218904A
- Authority
- CN
- China
- Prior art keywords
- pmos
- nmos tube
- grid
- drain electrode
- connects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention discloses a rail-to-rail-input AB-class-output full-differential operational amplifier which comprises a first-level amplification circuit and a second-level amplification circuit. The first-level amplification circuit is formed by four folding type cascade amplification circuits, and the four folding type cascade amplification circuits form a complementary differential pair. The second-level amplification circuit is formed by two symmetric AB-class amplification circuits. According to the rail-to-rail-input AB-class-output full-differential operational amplifier, full input and output swing can be achieved, transconductance is constant, and stable common-mode output and frequency responses are achieved.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, particularly relate to the Full differential operational amplifier that a kind of rail-to-rail input AB class exports.
Background technology
Operational amplifier is one of the most most important module in analog circuit, can construct the circuit of the various functions such as signal amplification, Signal transmissions, signal filtering, be widely used in the fields such as communication, PC, consumption, automobile and industry.Along with CMOS technology channel length constantly reduces, transistor integrated level improves constantly, and its supply voltage that can bear also constantly reduces, and causes the dynamic range of signal constantly to reduce.In order to expand the dynamic range of signal, operational amplifier is needed to have the characteristic of the full amplitude of oscillation (i.e. rail-to-rail) input and output.
As the structure principle chart that Fig. 1 is existing operational amplifier; Comprise the single-stage amplifier be made up of input stage 101, by buffer or level shift 102 and the secondary amplifier that provides the gain stage 103 of high-gain to form, three grades of amplifiers that buffer or level shift 104 and out drive stage 105 form.Wherein input stage 101 is generally made up of differential transconductance level, can effectively suppress common-mode noise and offset error, sometimes also can provide differential-to-single-ended conversion.But existing PMOS Differential Input to or nmos differential input to due to himself characteristic, needing input signal to be less than or be greater than certain value could normal work, thus limits the input signal amplitude of oscillation.Same, although with the addition of out drive stage 105 in a lot of amplifier or differential output stage provides large output voltage swing, cannot accomplish the output of the full amplitude of oscillation, along with the continuous reduction of supply voltage, the drawback that limited output voltage swing brings can grow with each passing day.And the performance of differential output stage is very responsive to the change of output common mode level, and output common mode level cannot be regulated by existing differential feedback.
Summary of the invention
Technical problem to be solved by this invention is to provide the Full differential operational amplifier that a kind of rail-to-rail input AB class exports, and can realize the full amplitude of oscillation of input and output, and mutual conductance is constant, has stable common mode and export and frequency response.
For solving the problems of the technologies described above, the Full differential operational amplifier first order amplifying circuit that rail-to-rail input AB class provided by the invention exports and second level amplifying circuit.
Described first order amplifying circuit is made up of four road Foldable cascade amplifying circuits, four road Foldable cascade amplifying circuit composition complementary differential pair.
First via Foldable cascade amplifying circuit comprises the first NMOS tube and the first PMOS, the grid of described first NMOS tube connects the first differential input signal, the first load is connected between the drain electrode of described first NMOS tube and supply voltage, the drain electrode of described first NMOS tube connects the source electrode of described first PMOS, the grid of described first PMOS connects the first bias voltage, and the drain electrode of described first PMOS is the first output signal end.
Second road Foldable cascade amplifying circuit comprises the second NMOS tube and the second PMOS, the grid of described second NMOS tube connects the second differential input signal, the second load is connected between the drain electrode of described second NMOS tube and supply voltage, the drain electrode of described second NMOS tube connects the source electrode of described second PMOS, the grid of described second PMOS connects the first bias voltage, and the drain electrode of described second PMOS is the second output signal end; Described first NMOS tube is all connected the first current source with the source electrode of described second NMOS tube, and described first differential input signal and described second differential input signal partner differential input signal.
3rd road Foldable cascade amplifying circuit comprises the 3rd NMOS tube and the 3rd PMOS, the grid of described 3rd PMOS connects the first differential input signal, the 3rd load is connected between the drain electrode of described 3rd PMOS and ground, the drain electrode of described 3rd PMOS connects the source electrode of described 3rd NMOS tube, the grid of described 3rd NMOS tube connects the second bias voltage, and the drain electrode of described 3rd NMOS tube is the 3rd output signal end.
4th road Foldable cascade amplifying circuit comprises the 4th NMOS tube and the 4th PMOS, the grid of described 4th PMOS connects the second differential input signal, the 4th load is connected between the drain electrode of described 4th PMOS and ground, the drain electrode of described 4th PMOS connects the source electrode of described 4th NMOS tube, the grid of described 4th NMOS tube connects the second bias voltage, and the drain electrode of described 4th NMOS tube is the 4th output signal end; Described 3rd PMOS is all connected the second current source with the source electrode of described 4th PMOS.
Described second level amplifying circuit is made up of the AB class amplification circuit of two-way symmetry.
First via AB class amplification circuit comprises the 5th NMOS tube and the 5th PMOS, the grid of described 5th PMOS connects described first output signal end, source electrode connects supply voltage, the grid of described 5th NMOS tube connects described 3rd output signal end, source ground, and described 5th NMOS tube is connected with the drain electrode of described 5th PMOS also as the first difference output end exporting the first differential output signal.
Second road AB class amplification circuit comprises the 6th NMOS tube and the 6th PMOS, the grid of described 6th PMOS connects described second output signal end, source electrode connects supply voltage, the grid of described 6th NMOS tube connects described 4th output signal end, source ground, and described 6th NMOS tube is connected with the drain electrode of described 6th PMOS also as the second difference output end exporting the second differential output signal.
Further improvement is, described first load is made up of the 7th PMOS, described second load is made up of the 8th PMOS, the drain electrode that source electrode connects supply voltage, drain electrode connects described first NMOS tube of described 7th PMOS, the drain electrode that source electrode connects supply voltage, drain electrode connects described second NMOS tube of described 8th PMOS, described 7th PMOS is all connected same biased formation current source load with the grid of described 8th PMOS.
Described first current source is connected to form by the 7th NMOS tube and the 8th NMOS tube, the drain electrode of described 7th NMOS tube connects the source electrode of described first NMOS tube and described second NMOS tube, the source electrode of described 7th NMOS tube connects the drain electrode of described 8th NMOS tube, the source ground of described 8th NMOS tube, the grid of described 7th NMOS tube connects described second bias voltage, and the grid of described 8th NMOS tube connects the 3rd bias voltage.
Described 3rd load is made up of the 9th NMOS tube, described 4th load is made up of the tenth NMOS tube, the source ground of described 9th NMOS tube, drain electrode connect the drain electrode of described 3rd PMOS, the source ground of described tenth NMOS tube, drain electrode connect the drain electrode of described 4th PMOS, and described 9th NMOS tube is all connected same biased formation current source load with the grid of described tenth NMOS tube.
Described second current source is connected to form by the 9th PMOS and the tenth PMOS, the drain electrode of described 9th PMOS connects the source electrode of described 3rd PMOS and described 4th PMOS, the source electrode of described 9th PMOS connects the drain electrode of described tenth PMOS, the source electrode of described tenth PMOS connects supply voltage, the grid of described 9th PMOS connects described first bias voltage, and the grid of described tenth PMOS connects the 4th bias voltage.
Further improvement is, the current source load that described 7th PMOS and described 8th PMOS are formed is all the mirror current source of the 3rd current source, described 3rd current source comprises the 11 PMOS, 11 NMOS tube and the 12 NMOS tube, the source electrode of described 11 PMOS connects supply voltage, the grid of described 7th PMOS and described 8th PMOS all with grid and the drain electrode of described 11 PMOS, described 11 NMOS tube is connected with the drain electrode of described 12 NMOS tube, described 11 NMOS tube is connected the drain electrode of described 7th NMOS tube with the source electrode of described 12 NMOS tube, the grid of described 11 NMOS tube connects described first differential input signal, the grid of described 12 NMOS tube connects described second differential input signal.
The current source load that described 9th NMOS tube and described tenth NMOS tube are formed is all the mirror current source of the 4th current source, described 4th current source comprises the 13 NMOS tube, 12 PMOS and the 13 PMOS, the source ground of described 13 NMOS tube, the grid of described 9th NMOS tube and described tenth NMOS tube all with grid and the drain electrode of described 13 NMOS tube, described 12 PMOS is connected with the drain electrode of described 13 PMOS, described 12 PMOS is connected the drain electrode of described 9th PMOS with the source electrode of described 13 PMOS, the grid of described 12 PMOS connects described first differential input signal, the grid of described 13 PMOS connects described second differential input signal.
Further improvement is, is in series with the first electric capacity and the first resistance that supplement for Miller between described first difference output end and the first output signal end.
The second electric capacity and the second resistance that supplement for Miller is in series with between described first difference output end and the 3rd output signal end.
The 3rd electric capacity and the 3rd resistance that supplement for Miller is in series with between described second difference output end and the second output signal end.
The 4th electric capacity and the 4th resistance that supplement for Miller is in series with between described second difference output end and the 4th output signal end.
Further improvement is, described first via AB class amplification circuit also comprises the 14 NMOS tube and the 14 PMOS, the drain electrode of described 14 NMOS tube, the source electrode of described 14 PMOS all connect the grid of described 5th PMOS, the source electrode of described 14 NMOS tube, the drain electrode of described 14 PMOS all connect the grid of described 5th NMOS tube, the grid of described 14 NMOS tube connects the 5th bias voltage, and the grid of described 14 PMOS connects the 6th bias voltage; Described 14 NMOS tube and described 14 PMOS parallel connection form a floating current source to be made produce a stable bias voltage between the grid of described 5th NMOS tube and described 5th PMOS and make described 5th NMOS tube and described 5th PMOS be biased in saturation region.
Described second road AB class amplification circuit also comprises the 15 NMOS tube and the 15 PMOS, the drain electrode of described 15 NMOS tube, the source electrode of described 15 PMOS all connect the grid of described 6th PMOS, the source electrode of described 15 NMOS tube, the drain electrode of described 15 PMOS all connect the grid of described 6th NMOS tube, the grid of described 15 NMOS tube connects described 5th bias voltage, and the grid of described 15 PMOS connects described 6th bias voltage; Described 15 NMOS tube and described 15 PMOS parallel connection form a floating current source to be made produce a stable bias voltage between the grid of described 6th NMOS tube and described 6th PMOS and make described 6th NMOS tube and described 6th PMOS be biased in saturation region.
Further improvement is, described first via Foldable cascade amplifying circuit also comprises the 16 PMOS, the drain electrode that described 16 PMOS source electrode connects supply voltage, drain electrode connects described first NMOS tube.
Described second road Foldable cascade amplifying circuit also comprises the 17 PMOS, the drain electrode that described 17 PMOS source electrode connects supply voltage, drain electrode connects described second NMOS tube.
Described 16 PMOS is all connected common mode feedback voltage with the grid of described 17 PMOS; Described common mode feedback voltage is provided by common mode feedback circuit, and described common mode feedback circuit comprises:
The differential amplifier circuit be made up of the 16 NMOS tube and the 17 NMOS tube, the source electrode of described 16 NMOS tube and described 17 NMOS tube links together and a current source, the grid of described 16 NMOS tube connects output common mode voltage, and the grid of described 17 NMOS tube connects benchmark common-mode voltage; The drain electrode of described 16 NMOS tube exports described common mode feedback voltage; Described common mode feedback voltage makes described output common mode voltage stabilization at described benchmark common-mode voltage after feeding back to the grid of described 16 PMOS and described 17 PMOS.
5th resistance and the 6th resistant series are between the first differential output signal and the second differential output signal, and the junction of described 5th resistance and described 6th resistance exports described output common mode voltage.
Between the drain electrode that 18 PMOS and the 19 PMOS are connected on described 16 NMOS tube and supply voltage, between the drain electrode that the 20 PMOS and the 21 PMOS are connected on described 17 NMOS tube and supply voltage; The drain electrode of described 18 PMOS, the drain electrode of described 16 NMOS tube are connected with the grid of described 19 PMOS, and the source electrode of described 18 PMOS connects the drain electrode of described 19 PMOS, and the source electrode of described 19 PMOS connects supply voltage; The drain and gate of described 20 PMOS, the drain electrode of described 17 NMOS tube, the grid of described 18 PMOS, the grid of described 21 PMOS are connected and connect the 7th bias voltage, the source electrode of described 20 PMOS is connected with the drain electrode of described 21 PMOS, and the source electrode of described 21 PMOS connects supply voltage.
The present invention can realize the full amplitude of oscillation of input and output, and mutual conductance is constant, has stable common mode and exports and frequency response.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structure principle chart of existing operational amplifier;
Fig. 2 is the circuit diagram of the Full differential operational amplifier that embodiment of the present invention rail-to-rail input AB class exports;
Fig. 3 is the common mode feedback circuit figure in embodiment of the present invention Full differential operational amplifier;
Fig. 4 is the biasing circuit figure in embodiment of the present invention Full differential operational amplifier;
Fig. 5 is the open-loop gain of embodiment of the present invention Full differential operational amplifier and the simulation curve of frequency response;
Fig. 6 is the simulation curve that the mutual conductance of embodiment of the present invention Full differential operational amplifier changes with common mode incoming level.
Embodiment
As shown in Figure 2, be the circuit diagram that embodiment of the present invention rail-to-rail inputs the Full differential operational amplifier that AB class exports; The Full differential operational amplifier first order amplifying circuit that embodiment of the present invention rail-to-rail input AB class exports and second level amplifying circuit.
Described first order amplifying circuit is made up of four road Foldable cascade amplifying circuits, four road Foldable cascade amplifying circuit composition complementary differential pair.
First via Foldable cascade amplifying circuit comprises the first NMOS tube MN1 and the first PMOS MP1, the grid of described first NMOS tube MN1 connects the first differential input signal Vinp, the first load is connected between the drain electrode of described first NMOS tube MN1 and supply voltage avd, the drain electrode of described first NMOS tube MN1 connects the source electrode of described first PMOS MP1, the grid of described first PMOS MP1 meets the first bias voltage Vpcas, and the drain electrode of described first PMOS MP1 is the first output signal end.The 22 PMOS MP22 is also serially connected with between the source electrode of described first PMOS MP1 and supply voltage avd, the source electrode that source electrode connects supply voltage, drain electrode meets described first PMOS MP1 of described 22 PMOS MP22, grid the 8th bias voltage b of described 22 PMOS MP22.
Second road Foldable cascade amplifying circuit comprises the second NMOS tube MN2 and the second PMOS MP2, the grid of described second NMOS tube MN2 connects the second differential input signal Vinn, the second load is connected between the drain electrode of described second NMOS tube MN2 and supply voltage avd, the drain electrode of described second NMOS tube MN2 connects the source electrode of described second PMOS MP2, the grid of described second PMOS MP2 meets the first bias voltage Vpcas, and the drain electrode of described second PMOS MP2 is the second output signal end; Described first NMOS tube MN1 is connected the first current source with the source electrode of described second NMOS tube MN2, and described first differential input signal Vinp and described second differential input signal Vinn partners differential input signal.The 23 PMOS MP23 is also serially connected with between the source electrode of described second PMOS MP2 and supply voltage avd, the source electrode that source electrode connects supply voltage, drain electrode meets described second PMOS MP2 of described 23 PMOS MP23, grid the 8th bias voltage b of described 23 PMOS MP23.
3rd road Foldable cascade amplifying circuit comprises the 3rd NMOS tube MN3 and the 3rd PMOS MP3, the grid of described 3rd PMOS MP3 connects the first differential input signal Vinp, the 3rd load is connected between the drain electrode of described 3rd PMOS MP3 and ground avs, the drain electrode of described 3rd PMOS MP3 connects the source electrode of described 3rd NMOS tube MN3, the grid of described 3rd NMOS tube MN3 meets the second bias voltage Vncas, and the drain electrode of described 3rd NMOS tube MN3 is the 3rd output signal end.The 18 NMOS tube MN18 is also serially connected with between the source electrode of described 3rd NMOS tube MN3 and ground avs, the source ground avs of described 18 NMOS tube MN18, drain electrode connect the source electrode of described 3rd NMOS tube MN3, grid the 9th bias voltage a of described 18 NMOS tube MN18.
4th road Foldable cascade amplifying circuit comprises the 4th NMOS tube MN4 and the 4th PMOS MP4, the grid of described 4th PMOS MP4 connects the second differential input signal Vinn, the 4th load is connected between the drain electrode of described 4th PMOS MP4 and ground avs, the drain electrode of described 4th PMOS MP4 connects the source electrode of described 4th NMOS tube MN4, the grid of described 4th NMOS tube MN4 meets the second bias voltage Vncas, and the drain electrode of described 4th NMOS tube MN4 is the 4th output signal end; Described 3rd PMOS MP3 is connected the second current source with the source electrode of described 4th PMOS MP4.The 19 NMOS tube MN19 is also serially connected with between the source electrode of described 4th NMOS tube MN4 and ground avs, the source ground avs of described 19 NMOS tube MN19, drain electrode connect the source electrode of described 4th NMOS tube MN4, grid the 9th bias voltage a of described 19 NMOS tube MN19.
Described first load is made up of the 7th PMOS MP7, described second load is made up of the 8th PMOS MP8, the drain electrode that source electrode meets supply voltage avd, drain electrode meets described first NMOS tube MN1 of described 7th PMOS MP7, the drain electrode that source electrode meets supply voltage avd, drain electrode meets described second NMOS tube MN2 of described 8th PMOS MP8, described 7th PMOS MP7 is connected same biased formation current source load with the grid of described 8th PMOS MP8.
Described first current source is connected to form by the 7th NMOS tube MN7 and the 8th NMOS tube MN8, the drain electrode of described 7th NMOS tube MN7 connects the source electrode of described first NMOS tube MN1 and described second NMOS tube MN2, the source electrode of described 7th NMOS tube MN7 connects the drain electrode of described 8th NMOS tube MN8, the source ground avs of described 8th NMOS tube MN8, the grid of described 7th NMOS tube MN7 connects grid connection the 3rd bias voltage Vn1 of described second bias voltage Vncas, described 8th NMOS tube MN8.
Described 3rd load is made up of the 9th NMOS tube MN9, described 4th load is made up of the tenth NMOS tube MN10, the source ground avs of described 9th NMOS tube MN9, drain electrode connect the drain electrode of described 3rd PMOS MP3, the source ground avs of described tenth NMOS tube MN10, drain electrode connect the drain electrode of described 4th PMOS MP4, and described 9th NMOS tube MN9 is connected same biased formation current source load with the grid of described tenth NMOS tube MN10.
Described second current source is connected to form by the 9th PMOS MP9 and the tenth PMOS MP10, the drain electrode of described 9th PMOS MP9 connects the source electrode of described 3rd PMOS MP3 and described 4th PMOS MP4, the source electrode of described 9th PMOS MP9 connects the drain electrode of described tenth PMOS MP10, the source electrode of described tenth PMOS MP10 meets supply voltage avd, the grid of described 9th PMOS MP9 connects grid connection the 4th bias voltage Vp1 of described first bias voltage Vpcas, described tenth PMOS MP10.
The current source load that described 7th PMOS MP7 and described 8th PMOS MP8 is formed is all the mirror current source of the 3rd current source, described 3rd current source comprises the 11 PMOS MP11, 11 NMOS tube MN11 and the 12 NMOS tube MN12, the source electrode of described 11 PMOS MP11 meets supply voltage avd, the grid of described 7th PMOS MP7 and described 8th PMOS MP8 all with grid and the drain electrode of described 11 PMOS MP11, described 11 NMOS tube MN11 is connected with the drain electrode of described 12 NMOS tube MN12, described 11 NMOS tube MN11 is connected the drain electrode of described 7th NMOS tube MN7 with the source electrode of described 12 NMOS tube MN12, the grid of described 11 NMOS tube MN11 connects described first differential input signal Vinp, the grid of described 12 NMOS tube MN12 connects described second differential input signal Vinn.
The current source load that described 9th NMOS tube MN9 and described tenth NMOS tube MN10 is formed is all the mirror current source of the 4th current source, described 4th current source comprises the 13 NMOS tube MN13, 12 PMOS MP12 and the 13 PMOS MP13, the source ground avs of described 13 NMOS tube MN13, the grid of described 9th NMOS tube MN9 and described tenth NMOS tube MN10 all with grid and the drain electrode of described 13 NMOS tube MN13, described 12 PMOS MP12 is connected with the drain electrode of described 13 PMOS MP13, described 12 PMOS MP12 is connected the drain electrode of described 9th PMOS MP9 with the source electrode of described 13 PMOS MP13, the grid of described 12 PMOS MP12 connects described first differential input signal Vinp, the grid of described 13 PMOS MP13 connects described second differential input signal Vinn.
It is more than the structure description of the first order amplifying circuit of the embodiment of the present invention, the input stage of embodiment of the present invention first order amplifying circuit is that the NMOS input be made up of the first NMOS tube MN1 and the second NMOS tube MN2 inputs the complementary differential be formed in parallel structure with the PMOS be made up of the 3rd PMOS MP3 and the 4th PMOS MP4, so the common-mode input range of embodiment of the present invention amplifier and operational amplifier can be divided into three parts: when input common mode voltage close to negative supply namely avs time, only PMOS input to conducting; When input common mode voltage is close to positive supply and supply voltage avd, only NMOS input is to conducting; When input common mode voltage mediates current potential, PMOS input to NMOS input to while conducting, so no matter which interval common mode incoming level is in, always have input to conducting, thus realizes rail-to-rail input.Described first via Foldable cascade amplifying circuit branch road is the specific works process that example illustrates first order amplifying circuit below: described 7th PMOS MP7 is that PMOS current source is also as the drain terminal load of the common-source amplifier being input pipe with described first NMOS tube MN1; Add the cascodes that is made up of the 7th NMOS tube MN7 and the 8th NMOS tube MN8 as source degeneration in the source of described first NMOS tube MN1, make leakage current be approximately the linear function of input voltage, thus effectively improve the linearity of amplifier.
Described second level amplifying circuit is made up of the AB class amplification circuit of two-way symmetry.
First via AB class amplification circuit comprises the 5th NMOS tube MN5 and the 5th PMOS MP5, the grid of described 5th PMOS MP5 connects described first output signal end, source electrode connects supply voltage avd, the grid of described 5th NMOS tube MN5 connects described 3rd output signal end, source ground avs, and described 5th NMOS tube MN5 is connected with the drain electrode of described 5th PMOS MP5 also as the first difference output end exporting the first differential output signal Voutp.
Second road AB class amplification circuit comprises the 6th NMOS tube MN6 and the 6th PMOS MP6, the grid of described 6th PMOS MP6 connects described second output signal end, source electrode connects supply voltage avd, the grid of described 6th NMOS tube MN6 connects described 4th output signal end, source ground avs, and described 6th NMOS tube MN6 is connected with the drain electrode of described 6th PMOS MP6 also as the second difference output end exporting the second differential output signal Voutn.
Described first via AB class amplification circuit also comprises the 14 NMOS tube MN14 and the 14 PMOS MP14, the drain electrode of described 14 NMOS tube MN14, the source electrode of described 14 PMOS MP14 all connect the grid of described 5th PMOS MP5, the source electrode of described 14 NMOS tube MN14, the drain electrode of described 14 PMOS MP14 all connect the grid of described 5th NMOS tube MN5, the grid of described 14 NMOS tube MN14 connects grid connection the 6th bias voltage Vp2 of the 5th bias voltage Vn2, described 14 PMOS MP14; Described 14 NMOS tube MN14 and described 14 PMOS MP14 parallel connection form a floating current source to be made produce a stable bias voltage between the grid of described 5th NMOS tube MN5 and described 5th PMOS MP5 and make described 5th NMOS tube MN5 and described 5th PMOS MP5 be biased in saturation region.
Described second road AB class amplification circuit also comprises the 15 NMOS tube MN15 and the 15 PMOS MP15, the drain electrode of described 15 NMOS tube MN15, the source electrode of described 15 PMOS MP15 all connect the grid of described 6th PMOS MP6, the source electrode of described 15 NMOS tube MN15, the drain electrode of described 15 PMOS MP15 all connect the grid of described 6th NMOS tube MN6, the grid of described 15 NMOS tube MN15 connects the described 6th bias voltage Vp2 of grid connection of described 5th bias voltage Vn2, described 15 PMOS MP15; Described 15 NMOS tube MN15 and described 15 PMOS MP15 parallel connection form a floating current source to be made produce a stable bias voltage between the grid of described 6th NMOS tube MN6 and described 6th PMOS MP6 and make described 6th NMOS tube MN6 and described 6th PMOS MP6 be biased in saturation region.
As from the foregoing, the two-way AB class amplification circuit of the second level amplifying circuit of the embodiment of the present invention is all adopt the grid of floating current source degree of the coming efferent duct be made up of NMOS tube and PMOS to be biased, bias voltage can be realized stablize, make each efferent duct be in saturation region all the time, thus realize the output of AB class.In addition, adopt NMOS tube and PMOS two transistors as the circuit of voltage between fixing efferent duct grid, more save circuit area than the method for traditional use resistance.
Be in series with between described first difference output end and the first output signal end for the first miller-compensated electric capacity C1 and the first resistance R1.Be in series with between described first difference output end and the 3rd output signal end for the second miller-compensated electric capacity C2 and the second resistance R2.Be in series with between described second difference output end and the second output signal end for the 3rd miller-compensated electric capacity C3 and the 3rd resistance R3.Be in series with between described second difference output end and the 4th output signal end for the 4th miller-compensated electric capacity C4 and the 4th resistance R4.Because described second level amplifying circuit can introduce a low-frequency pole, the frequency characteristic of overall amplifier can be caused to be deteriorated.Therefore between each output and the input of correspondence of second level amplifying circuit, use miller capacitance C1 to C4 to carry out frequency compensation, use series resistance R1 to R4 to eliminate the extra zero point produced owing to adding miller capacitance simultaneously.
Described first via Foldable cascade amplifying circuit also comprises the 16 PMOS MP16, the drain electrode that described 16 PMOS MP16 source electrode meets supply voltage avd, drain electrode connects described first NMOS tube MN1.
Described second road Foldable cascade amplifying circuit also comprises the 17 PMOS MP17, the drain electrode that described 17 PMOS MP17 source electrode meets supply voltage avd, drain electrode connects described second NMOS tube MN2.
Described 16 PMOS MP16 is connected common mode feedback voltage cmfb1 with the grid of described 17 PMOS MP17; Described common mode feedback voltage cmfb1 is provided by common mode feedback circuit, and described common mode feedback circuit comprises:
The differential amplifier circuit be made up of the 16 NMOS tube MN16 and the 17 NMOS tube MN17, the source electrode of described 16 NMOS tube MN16 and described 17 NMOS tube MN17 links together and a current source, this current source is made up of the 20 NMOS tube MN20, and the grid of described 20 NMOS tube MN20 connects described 3rd bias voltage.The grid of described 16 NMOS tube MN16 connects output common mode voltage, and the grid of described 17 NMOS tube MN17 connects benchmark common-mode voltage refcm; The drain electrode of described 16 NMOS tube MN16 exports described common mode feedback voltage cmfb1; Described common mode feedback voltage cmfb1 makes described output common mode voltage stabilization at described benchmark common-mode voltage refcm after feeding back to the grid of described 16 PMOS MP16 and described 17 PMOS MP17.
5th resistance R5 and the 6th resistance R6 is connected between the first differential output signal Voutp and the second differential output signal Voutn, and the junction of described 5th resistance R5 and described 6th resistance R6 exports described output common mode voltage.
Between the drain electrode that 18 PMOS MP18 and the 19 PMOS MP19 is connected on described 16 NMOS tube MN16 and supply voltage avd, between the drain electrode that the 20 PMOS MP20 and the 21 PMOS MP21 is connected on described 17 NMOS tube MN17 and supply voltage avd; The drain electrode of described 18 PMOS MP18, the drain electrode of described 16 NMOS tube MN16 are connected with the grid of described 19 PMOS MP19, the source electrode of described 18 PMOS MP18 connects the drain electrode of described 19 PMOS MP19, and the source electrode of described 19 PMOS MP19 meets supply voltage avd; The drain and gate of described 20 PMOS MP20, the drain electrode of described 17 NMOS tube MN17, the grid of described 18 PMOS MP18, the grid of described 21 PMOS MP21 are connected and meet the 7th bias voltage Vbias7, the source electrode of described 20 PMOS MP20 is connected with the drain electrode of described 21 PMOS MP21, and the source electrode of described 21 PMOS MP21 meets supply voltage avd.
As shown in Figure 4, be biasing circuit figure in embodiment of the present invention Full differential operational amplifier; Whole biasing circuit is made up of PMOS M1 to M15 and NMOS tube M16 to M29, and wherein current source Ibias is external current source, in the mirror path of the current source Ibias be made up of each transistor, draws nine bias voltages needed for the embodiment of the present invention.
As shown in Figure 5, be the open-loop gain of embodiment of the present invention Full differential operational amplifier and the simulation curve of frequency response; Can find out that open loop DC gain is 89.87dB, phase margin is 75.8degs(degree), system is stable.Fig. 6 is the simulation curve that the mutual conductance of embodiment of the present invention Full differential operational amplifier changes with common mode incoming level, can find out in full amplitude of oscillation input range, amplifier mutual conductance substantially constant.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (6)
1. a Full differential operational amplifier for rail-to-rail input AB class output, is characterized in that, comprising: first order amplifying circuit and second level amplifying circuit;
Described first order amplifying circuit is made up of four road Foldable cascade amplifying circuits, four road Foldable cascade amplifying circuit composition complementary differential pair;
First via Foldable cascade amplifying circuit comprises the first NMOS tube and the first PMOS, the grid of described first NMOS tube connects the first differential input signal, the first load is connected between the drain electrode of described first NMOS tube and supply voltage, the drain electrode of described first NMOS tube connects the source electrode of described first PMOS, the grid of described first PMOS connects the first bias voltage, and the drain electrode of described first PMOS is the first output signal end;
Second road Foldable cascade amplifying circuit comprises the second NMOS tube and the second PMOS, the grid of described second NMOS tube connects the second differential input signal, the second load is connected between the drain electrode of described second NMOS tube and supply voltage, the drain electrode of described second NMOS tube connects the source electrode of described second PMOS, the grid of described second PMOS connects the first bias voltage, and the drain electrode of described second PMOS is the second output signal end; Described first NMOS tube is all connected the first current source with the source electrode of described second NMOS tube, and described first differential input signal and described second differential input signal partner differential input signal;
3rd road Foldable cascade amplifying circuit comprises the 3rd NMOS tube and the 3rd PMOS, the grid of described 3rd PMOS connects the first differential input signal, the 3rd load is connected between the drain electrode of described 3rd PMOS and ground, the drain electrode of described 3rd PMOS connects the source electrode of described 3rd NMOS tube, the grid of described 3rd NMOS tube connects the second bias voltage, and the drain electrode of described 3rd NMOS tube is the 3rd output signal end;
4th road Foldable cascade amplifying circuit comprises the 4th NMOS tube and the 4th PMOS, the grid of described 4th PMOS connects the second differential input signal, the 4th load is connected between the drain electrode of described 4th PMOS and ground, the drain electrode of described 4th PMOS connects the source electrode of described 4th NMOS tube, the grid of described 4th NMOS tube connects the second bias voltage, and the drain electrode of described 4th NMOS tube is the 4th output signal end; Described 3rd PMOS is all connected the second current source with the source electrode of described 4th PMOS;
Described second level amplifying circuit is made up of the AB class amplification circuit of two-way symmetry;
First via AB class amplification circuit comprises the 5th NMOS tube and the 5th PMOS, the grid of described 5th PMOS connects described first output signal end, source electrode connects supply voltage, the grid of described 5th NMOS tube connects described 3rd output signal end, source ground, and described 5th NMOS tube is connected also as the first difference output end exporting the first differential output signal with the drain electrode of described 5th PMOS;
Second road AB class amplification circuit comprises the 6th NMOS tube and the 6th PMOS, the grid of described 6th PMOS connects described second output signal end, source electrode connects supply voltage, the grid of described 6th NMOS tube connects described 4th output signal end, source ground, and described 6th NMOS tube is connected with the drain electrode of described 6th PMOS also as the second difference output end exporting the second differential output signal.
2. the Full differential operational amplifier of rail-to-rail input AB class as claimed in claim 1 output, is characterized in that:
Described first load is made up of the 7th PMOS, described second load is made up of the 8th PMOS, the drain electrode that source electrode connects supply voltage, drain electrode connects described first NMOS tube of described 7th PMOS, the drain electrode that source electrode connects supply voltage, drain electrode connects described second NMOS tube of described 8th PMOS, described 7th PMOS is all connected same biased formation current source load with the grid of described 8th PMOS;
Described first current source is connected to form by the 7th NMOS tube and the 8th NMOS tube, the drain electrode of described 7th NMOS tube connects the source electrode of described first NMOS tube and described second NMOS tube, the source electrode of described 7th NMOS tube connects the drain electrode of described 8th NMOS tube, the source ground of described 8th NMOS tube, the grid of described 7th NMOS tube connects described second bias voltage, and the grid of described 8th NMOS tube connects the 3rd bias voltage;
Described 3rd load is made up of the 9th NMOS tube, described 4th load is made up of the tenth NMOS tube, the source ground of described 9th NMOS tube, drain electrode connect the drain electrode of described 3rd PMOS, the source ground of described tenth NMOS tube, drain electrode connect the drain electrode of described 4th PMOS, and described 9th NMOS tube is all connected same biased formation current source load with the grid of described tenth NMOS tube;
Described second current source is connected to form by the 9th PMOS and the tenth PMOS, the drain electrode of described 9th PMOS connects the source electrode of described 3rd PMOS and described 4th PMOS, the source electrode of described 9th PMOS connects the drain electrode of described tenth PMOS, the source electrode of described tenth PMOS connects supply voltage, the grid of described 9th PMOS connects described first bias voltage, and the grid of described tenth PMOS connects the 4th bias voltage.
3. the Full differential operational amplifier of rail-to-rail input AB class as claimed in claim 3 output, is characterized in that:
The current source load that described 7th PMOS and described 8th PMOS are formed is all the mirror current source of the 3rd current source, described 3rd current source comprises the 11 PMOS, 11 NMOS tube and the 12 NMOS tube, the source electrode of described 11 PMOS connects supply voltage, the grid of described 7th PMOS and described 8th PMOS all with grid and the drain electrode of described 11 PMOS, described 11 NMOS tube is connected with the drain electrode of described 12 NMOS tube, described 11 NMOS tube is connected the drain electrode of described 7th NMOS tube with the source electrode of described 12 NMOS tube, the grid of described 11 NMOS tube connects described first differential input signal, the grid of described 12 NMOS tube connects described second differential input signal,
The current source load that described 9th NMOS tube and described tenth NMOS tube are formed is all the mirror current source of the 4th current source, described 4th current source comprises the 13 NMOS tube, 12 PMOS and the 13 PMOS, the source ground of described 13 NMOS tube, the grid of described 9th NMOS tube and described tenth NMOS tube all with grid and the drain electrode of described 13 NMOS tube, described 12 PMOS is connected with the drain electrode of described 13 PMOS, described 12 PMOS is connected the drain electrode of described 9th PMOS with the source electrode of described 13 PMOS, the grid of described 12 PMOS connects described first differential input signal, the grid of described 13 PMOS connects described second differential input signal.
4. the Full differential operational amplifier of rail-to-rail input AB class as claimed in claim 1 output, is characterized in that:
The first electric capacity and the first resistance that supplement for Miller is in series with between described first difference output end and the first output signal end;
The second electric capacity and the second resistance that supplement for Miller is in series with between described first difference output end and the 3rd output signal end;
The 3rd electric capacity and the 3rd resistance that supplement for Miller is in series with between described second difference output end and the second output signal end;
The 4th electric capacity and the 4th resistance that supplement for Miller is in series with between described second difference output end and the 4th output signal end.
5. the Full differential operational amplifier of rail-to-rail input AB class as claimed in claim 1 output, is characterized in that:
Described first via AB class amplification circuit also comprises the 14 NMOS tube and the 14 PMOS, the drain electrode of described 14 NMOS tube, the source electrode of described 14 PMOS all connect the grid of described 5th PMOS, the source electrode of described 14 NMOS tube, the drain electrode of described 14 PMOS all connect the grid of described 5th NMOS tube, the grid of described 14 NMOS tube connects the 5th bias voltage, and the grid of described 14 PMOS connects the 6th bias voltage; Described 14 NMOS tube and described 14 PMOS parallel connection form a floating current source to be made produce a stable bias voltage between the grid of described 5th NMOS tube and described 5th PMOS and make described 5th NMOS tube and described 5th PMOS be biased in saturation region;
Described second road AB class amplification circuit also comprises the 15 NMOS tube and the 15 PMOS, the drain electrode of described 15 NMOS tube, the source electrode of described 15 PMOS all connect the grid of described 6th PMOS, the source electrode of described 15 NMOS tube, the drain electrode of described 15 PMOS all connect the grid of described 6th NMOS tube, the grid of described 15 NMOS tube connects described 5th bias voltage, and the grid of described 15 PMOS connects described 6th bias voltage; Described 15 NMOS tube and described 15 PMOS parallel connection form a floating current source to be made produce a stable bias voltage between the grid of described 6th NMOS tube and described 6th PMOS and make described 6th NMOS tube and described 6th PMOS be biased in saturation region.
6. the Full differential operational amplifier of rail-to-rail input AB class as claimed in claim 1 or 2 output, is characterized in that:
Described first via Foldable cascade amplifying circuit also comprises the 16 PMOS, the drain electrode that described 16 PMOS source electrode connects supply voltage, drain electrode connects described first NMOS tube;
Described second road Foldable cascade amplifying circuit also comprises the 17 PMOS, the drain electrode that described 17 PMOS source electrode connects supply voltage, drain electrode connects described second NMOS tube;
Described 16 PMOS is all connected common mode feedback voltage with the grid of described 17 PMOS; Described common mode feedback voltage is provided by common mode feedback circuit, and described common mode feedback circuit comprises:
The differential amplifier circuit be made up of the 16 NMOS tube and the 17 NMOS tube, the source electrode of described 16 NMOS tube and described 17 NMOS tube links together and a current source, the grid of described 16 NMOS tube connects output common mode voltage, and the grid of described 17 NMOS tube connects benchmark common-mode voltage; The drain electrode of described 16 NMOS tube exports described common mode feedback voltage; Described common mode feedback voltage makes described output common mode voltage stabilization at described benchmark common-mode voltage after feeding back to the grid of described 16 PMOS and described 17 PMOS;
5th resistance and the 6th resistant series are between the first differential output signal and the second differential output signal, and the junction of described 5th resistance and described 6th resistance exports described output common mode voltage;
Between the drain electrode that 18 PMOS and the 19 PMOS are connected on described 16 NMOS tube and supply voltage, between the drain electrode that the 20 PMOS and the 21 PMOS are connected on described 17 NMOS tube and supply voltage; The drain electrode of described 18 PMOS, the drain electrode of described 16 NMOS tube are connected with the grid of described 19 PMOS, and the source electrode of described 18 PMOS connects the drain electrode of described 19 PMOS, and the source electrode of described 19 PMOS connects supply voltage; The drain and gate of described 20 PMOS, the drain electrode of described 17 NMOS tube, the grid of described 18 PMOS, the grid of described 21 PMOS are connected and connect the 7th bias voltage, the source electrode of described 20 PMOS is connected with the drain electrode of described 21 PMOS, and the source electrode of described 21 PMOS connects supply voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310208076.9A CN104218904B (en) | 2013-05-29 | 2013-05-29 | The Full differential operational amplifier of rail-to-rail input AB class outputs |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310208076.9A CN104218904B (en) | 2013-05-29 | 2013-05-29 | The Full differential operational amplifier of rail-to-rail input AB class outputs |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104218904A true CN104218904A (en) | 2014-12-17 |
| CN104218904B CN104218904B (en) | 2017-06-06 |
Family
ID=52100101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310208076.9A Active CN104218904B (en) | 2013-05-29 | 2013-05-29 | The Full differential operational amplifier of rail-to-rail input AB class outputs |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104218904B (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104660195A (en) * | 2015-03-16 | 2015-05-27 | 西安电子科技大学 | Fully differential rail-to-rail operational amplifier |
| CN104779930A (en) * | 2015-04-03 | 2015-07-15 | 成都振芯科技股份有限公司 | High gain common mode feedback loop applied to high impedance current source load differential mode amplification circuit |
| CN106059516A (en) * | 2016-06-03 | 2016-10-26 | 西安电子科技大学 | Rail-to-rail operational amplifier circuit, ADC converter, DCDC converter and power amplifier |
| CN106160683A (en) * | 2016-06-24 | 2016-11-23 | 上海华虹宏力半导体制造有限公司 | Operational amplifier |
| CN107154786A (en) * | 2017-04-11 | 2017-09-12 | 东南大学 | A kind of rail-to-rail operation transconductance amplifier of low-voltage |
| CN107301308A (en) * | 2017-08-15 | 2017-10-27 | 苏州锴威特半导体有限公司 | A kind of Permeate flow full swing operational amplifier |
| CN107508567A (en) * | 2017-08-29 | 2017-12-22 | 南京邮电大学南通研究院有限公司 | A kind of constant rail-to-rail difference amplifier of low-voltage mutual conductance |
| CN109167583A (en) * | 2018-10-31 | 2019-01-08 | 上海海栎创微电子有限公司 | Trsanscondutance amplifier |
| CN109951160A (en) * | 2019-02-27 | 2019-06-28 | 上海华虹宏力半导体制造有限公司 | Doherty power amplifier based on transformer |
| CN113328711A (en) * | 2021-06-21 | 2021-08-31 | 浙江大学 | Constant cross-rail-to-rail input differential output high-speed programmable gain amplifier |
| CN114389553A (en) * | 2021-08-16 | 2022-04-22 | 美垦半导体技术有限公司 | Amplifier circuit, chip and household appliance |
| CN115664356A (en) * | 2022-12-08 | 2023-01-31 | 江苏润石科技有限公司 | High-voltage input stage differential pair transistor protection circuit |
| CN115955221A (en) * | 2023-03-14 | 2023-04-11 | 昂赛微电子（上海）有限公司 | High-side voltage comparison circuit and control method thereof |
| CN116526833A (en) * | 2023-06-29 | 2023-08-01 | 江苏润石科技有限公司 | Charge pump with stable output voltage and rail-to-rail input operational amplifier |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005341149A (en) * | 2004-05-26 | 2005-12-08 | Sony Corp | Differential amplifier circuit |
| CN201813350U (en) * | 2010-10-19 | 2011-04-27 | 杭州电子科技大学 | Low-voltage rail-to-rail operation amplifying circuit |
-
2013
- 2013-05-29 CN CN201310208076.9A patent/CN104218904B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005341149A (en) * | 2004-05-26 | 2005-12-08 | Sony Corp | Differential amplifier circuit |
| CN201813350U (en) * | 2010-10-19 | 2011-04-27 | 杭州电子科技大学 | Low-voltage rail-to-rail operation amplifying circuit |
Non-Patent Citations (2)
| Title |
|---|
| 陶园林: "1.3W+CMOS全差分音频功率放大器设计", 《万方学位论文》 * |
| 马晓龙: "新型Rail-to-Rail运算放大器的研究与设计", 《中国优秀博硕士学位论文全文数据库 (硕士) 信息科技辑》 * |
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104660195A (en) * | 2015-03-16 | 2015-05-27 | 西安电子科技大学 | Fully differential rail-to-rail operational amplifier |
| CN104660195B (en) * | 2015-03-16 | 2018-05-15 | 西安电子科技大学 | A kind of fully differential rail-to-rail operation amplifier |
| CN104779930A (en) * | 2015-04-03 | 2015-07-15 | 成都振芯科技股份有限公司 | High gain common mode feedback loop applied to high impedance current source load differential mode amplification circuit |
| CN106059516B (en) * | 2016-06-03 | 2019-02-01 | 西安电子科技大学 | Track to track operational amplification circuit and ADC converter, dcdc converter and power amplifier |
| CN106059516A (en) * | 2016-06-03 | 2016-10-26 | 西安电子科技大学 | Rail-to-rail operational amplifier circuit, ADC converter, DCDC converter and power amplifier |
| CN106160683A (en) * | 2016-06-24 | 2016-11-23 | 上海华虹宏力半导体制造有限公司 | Operational amplifier |
| CN106160683B (en) * | 2016-06-24 | 2019-04-09 | 上海华虹宏力半导体制造有限公司 | Operational amplifier |
| CN107154786A (en) * | 2017-04-11 | 2017-09-12 | 东南大学 | A kind of rail-to-rail operation transconductance amplifier of low-voltage |
| CN107301308A (en) * | 2017-08-15 | 2017-10-27 | 苏州锴威特半导体有限公司 | A kind of Permeate flow full swing operational amplifier |
| CN107301308B (en) * | 2017-08-15 | 2023-08-15 | 苏州锴威特半导体股份有限公司 | Constant transconductance full-swing operational amplifier |
| CN107508567A (en) * | 2017-08-29 | 2017-12-22 | 南京邮电大学南通研究院有限公司 | A kind of constant rail-to-rail difference amplifier of low-voltage mutual conductance |
| CN107508567B (en) * | 2017-08-29 | 2019-06-04 | 南京邮电大学南通研究院有限公司 | A kind of constant rail-to-rail difference amplifier of low-voltage mutual conductance |
| CN109167583A (en) * | 2018-10-31 | 2019-01-08 | 上海海栎创微电子有限公司 | Trsanscondutance amplifier |
| CN109951160B (en) * | 2019-02-27 | 2023-07-04 | 上海华虹宏力半导体制造有限公司 | Doherty power amplifier based on transformer |
| CN109951160A (en) * | 2019-02-27 | 2019-06-28 | 上海华虹宏力半导体制造有限公司 | Doherty power amplifier based on transformer |
| CN113328711A (en) * | 2021-06-21 | 2021-08-31 | 浙江大学 | Constant cross-rail-to-rail input differential output high-speed programmable gain amplifier |
| CN114389553A (en) * | 2021-08-16 | 2022-04-22 | 美垦半导体技术有限公司 | Amplifier circuit, chip and household appliance |
| CN114389553B (en) * | 2021-08-16 | 2023-01-24 | 美垦半导体技术有限公司 | Amplifier circuit, chip and household appliance |
| CN115664356A (en) * | 2022-12-08 | 2023-01-31 | 江苏润石科技有限公司 | High-voltage input stage differential pair transistor protection circuit |
| CN115955221A (en) * | 2023-03-14 | 2023-04-11 | 昂赛微电子（上海）有限公司 | High-side voltage comparison circuit and control method thereof |
| CN116526833A (en) * | 2023-06-29 | 2023-08-01 | 江苏润石科技有限公司 | Charge pump with stable output voltage and rail-to-rail input operational amplifier |
| CN116526833B (en) * | 2023-06-29 | 2023-09-05 | 江苏润石科技有限公司 | Charge pump with stable output voltage and rail-to-rail input operational amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104218904B (en) | 2017-06-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104218904B (en) | The Full differential operational amplifier of rail-to-rail input AB class outputs | |
| US9236841B2 (en) | Current-feedback operational amplifier | |
| US4958133A (en) | CMOS complementary self-biased differential amplifier with rail-to-rail common-mode input-voltage range | |
| US7639078B2 (en) | Class AB folded-cascode amplifier having cascode compensation | |
| CN103825565A (en) | Operational amplifier | |
| CN106817099B (en) | Amplifier for physiological potential signal detection | |
| US7859338B2 (en) | Compact low-power class AB amplifier | |
| CN104113295A (en) | Low-voltage fully-differential operation amplifier circuit | |
| KR20100021938A (en) | Folded cascode operational amplifier having improved phase margin | |
| CN101123418A (en) | Rail-to-rail class AB amplifier | |
| CN103825557A (en) | Transconductance amplifier with low power consumption and high linearity | |
| CN103780213A (en) | Multistage operational amplifier | |
| CN202503479U (en) | A class AB operational amplifier with high gain and a high power supply rejection ration | |
| CN104393846A (en) | Operational amplifier | |
| CN101951236A (en) | Digital variable gain amplifier | |
| US7414473B1 (en) | Class AB folded-cascode amplifier having cascode compensation | |
| CN201846315U (en) | Digital variable gain amplifier | |
| CN103219952A (en) | Broadband low noise amplifier adopting noise cancellation technology | |
| WO2016062429A1 (en) | Amplifier circuit and amplifier arrangement | |
| Centurelli et al. | High‐gain, high‐CMRR class AB operational transconductance amplifier based on the flipped voltage follower | |
| CN114900139B (en) | Common-mode feedback circuit of fully differential operational amplifier | |
| CN107834986B (en) | Single-stage AB class operational transconductance amplifier and analog circuit | |
| CN114253341B (en) | Output circuit and voltage buffer | |
| CN105515536A (en) | Rail-to-rail amplifier | |
| CN111697935B (en) | Low-voltage rail-to-rail input and output operational amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |