CN114389553A - Amplifier circuit, chip and household appliance - Google Patents
Amplifier circuit, chip and household appliance Download PDFInfo
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- CN114389553A CN114389553A CN202110935357.9A CN202110935357A CN114389553A CN 114389553 A CN114389553 A CN 114389553A CN 202110935357 A CN202110935357 A CN 202110935357A CN 114389553 A CN114389553 A CN 114389553A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
Abstract
The invention discloses an amplifier circuit, a chip and household electrical appliances, wherein the amplifier circuit comprises a primary amplification module, a secondary amplification module and a power supply module, the power supply module can provide constant current sources for a first differential input tube and a second differential input tube in the primary amplification module, and can also provide bias voltage and a constant current source for a first PMOS tube and a second PMOS tube in the secondary amplification module, so that the primary amplification module can perform primary amplification on an input differential signal, and then the secondary amplification module performs secondary amplification. Thus, the amplifier circuit in the present embodiment can increase the circuit gain and simultaneously achieve the common mode rejection range of the circuit.
Description
Technical Field
The invention relates to the technical field of circuit design, in particular to an amplifier circuit, a chip and household electrical appliance equipment.
Background
The differential amplifier circuit is a circuit structure commonly used in a chip and is also an important component of an operational amplifier, and in the related art, reference is made to fig. 1 and fig. 2, where fig. 1 is a conventional differential amplifier circuit, the gain of which is small, and therefore, the differential amplifier circuit cannot be used in a circuit requiring a high gain. Fig. 2 shows a high-gain differential amplifier circuit in the related art, but in the related art, when the gain of the differential amplifier circuit is increased, the gain of the circuit is generally increased by using a Cascode structure, but the gain can be increased by using the Cascode structure, but the common mode rejection range of the circuit is also narrowed, so that the circuit cannot better reject the common mode signal.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, an object of the present invention is to provide an amplifier circuit that can increase a circuit gain and simultaneously achieve a common mode rejection range of the circuit.
A second objective of the present invention is to provide a chip.
A third object of the present invention is to provide a home appliance.
In order to achieve the above object, an embodiment of a first aspect of the present invention provides an amplifier circuit, which includes a first-stage amplification module, a second-stage amplification module, and a power supply module, where the first-stage amplification module includes a first differential input tube and a second differential input tube; the second-stage amplification module comprises a first PMOS (P-channel Metal Oxide Semiconductor) tube and a second PMOS tube; the power supply module is used for providing a constant current source for the first differential input tube and the second differential input tube and providing a bias voltage and a constant current source for the first PMOS tube and the second PMOS tube, so that the first-stage amplification module performs first-stage amplification on an input differential signal and then performs second-stage amplification by the second-stage amplification module.
The amplifier circuit of the embodiment of the invention comprises a first-stage amplification module, a second-stage amplification module and a power supply module, wherein the power supply module can provide constant current sources for a first differential input tube and a second differential input tube in the first-stage amplification module, and can also provide bias voltage and a constant current source for a first PMOS tube and a second PMOS tube in the second-stage amplification module, so that the first-stage amplification module can perform first-stage amplification on an input differential signal, and then the second-stage amplification module performs second-stage amplification. Thus, the amplifier circuit in the present embodiment can increase the circuit gain and simultaneously achieve the common mode rejection range of the circuit.
In one embodiment of the present invention, the power supply module includes: the asymmetric current mirror unit is used for generating a constant voltage source to provide a first bias voltage for the first PMOS tube and the second PMOS tube; a first constant current source unit for generating a first constant current source according to a second bias voltage supplied from the asymmetric current mirror unit to supply to the first differential input tube and the second differential input tube; the first load unit is used for respectively providing a second constant current source for the first differential input tube and the first PMOS tube and respectively providing a third constant current source for the second differential input tube and the second PMOS tube; and the second load unit is used for providing a fourth constant current source for the first PMOS tube and providing a fifth constant current source for the second PMOS tube.
In an embodiment of the present invention, the first differential input tube and the second differential input tube are a first NMOS (N-channel Metal Oxide Semiconductor) tube and a second NMOS tube, respectively, a differential signal is input to a gate of the first NMOS tube and a gate of the second NMOS tube, a source of the first NMOS tube is connected to a source of the second NMOS tube and then connected to the first constant current source, a drain of the first NMOS tube is connected to the second constant current source, and a drain of the second NMOS tube is connected to the third constant current source.
In an embodiment of the present invention, a gate of the first POMS transistor is connected to a gate of the second PMOS transistor and then connected to the first bias voltage, a source of the first PMOS transistor is connected to the second constant current source, a drain of the first PMOS transistor is connected to the fourth constant current source, a source of the second PMOS transistor is connected to the third constant current source, and a drain of the second PMOS transistor is connected to the fifth constant current source.
In one embodiment of the present invention, the first load unit includes: the grid electrode of the third PMOS tube is connected with the drain electrode of the third PMOS tube, then the second constant current source is output, and the source electrode of the third PMOS tube is connected to the VCC power supply; and the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, the fourth PMOS tube outputs the third constant current source, and the source electrode of the fourth PMOS tube is connected to the VCC power supply.
In one embodiment of the present invention, the second load unit includes: the grid electrode of the third NMOS tube is connected with the drain electrode of the third NMOS tube, and then the fourth constant current source is output; a grid electrode of the fourth NMOS tube is connected with a grid electrode of the third NMOS tube, and a drain electrode of the fourth NMOS tube outputs the fifth constant current source; a fifth NMOS tube, wherein a grid electrode of the fifth NMOS tube is connected with a drain electrode of the fifth NMOS tube and then is connected to a source electrode of the third NMOS tube, and the source electrode of the fifth NMOS tube is grounded; and the grid electrode of the sixth NMOS tube is connected with the grid electrode of the fifth NMOS tube, the drain electrode of the sixth NMOS tube is connected with the source electrode of the fourth NMOS tube, and the source electrode of the sixth NMOS tube is grounded.
In an embodiment of the present invention, the first constant current source unit includes a seventh NMOS transistor, a gate of the seventh NMOS transistor is connected to the second bias voltage, a source of the seventh NMOS transistor is grounded, and a drain of the seventh NMOS transistor outputs the first constant current source.
In an embodiment of the present invention, the first differential input tube, the second differential input tube, and the seventh NMOS tube all operate in a saturation constant current source region.
To achieve the above object, a second embodiment of the present invention provides a chip, which includes the amplifier circuit in the above embodiments.
The chip of the embodiment of the invention can increase the circuit gain and simultaneously give consideration to the common mode rejection range of the circuit through the amplifier circuit in the embodiment.
In order to achieve the above object, a third aspect of the present invention provides a home appliance, which includes the amplifier circuit in the above embodiments.
The household appliance of the embodiment of the invention can increase the circuit gain and simultaneously give consideration to the common mode rejection range of the circuit through the amplifier circuit in the embodiment.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a schematic diagram of a conventional differential amplifier circuit in the related art;
FIG. 2 is a schematic diagram of a high gain differential amplifier circuit in the related art;
FIG. 3 is a schematic diagram of an amplifier circuit according to one embodiment of the invention;
FIG. 4 is a diagram of an example amplifier circuit in accordance with one embodiment of the present invention;
fig. 5 is a diagram showing an example of an amplifier circuit in the related art;
FIG. 6 is a block diagram of a chip according to an embodiment of the invention;
fig. 7 is a block diagram of a home appliance according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
An amplifier circuit, a chip, and a home appliance according to an embodiment of the present invention are described below with reference to the drawings.
Fig. 3 is a schematic diagram of an amplifier circuit according to one embodiment of the invention.
As shown in fig. 3, the present invention provides an amplifier circuit, and the amplifier circuit 10 includes a first-stage amplification module 11, a second-stage amplification module 12, and a power supply module.
The amplifying module 11 includes a first differential input tube Q1 and a second differential input tube Q2, the amplifying module 12 includes a first PMOS tube QP1 and a second PMOS tube QP2, the power supply module can be used to provide a constant current source to the first differential input tube Q1 and the second differential input tube Q2 in the amplifying module 11, and can also provide a bias voltage Vbi and a constant current source to the first PMOS tube QP1 and the second PMOS tube QP2, so that the amplifying module 11 can amplify the differential signal input thereto at one stage, and the amplifying module 12 can amplify the differential signal amplified at one stage at two stages.
Specifically, referring to fig. 3, it should be noted that, first, the providing module of the power supply in fig. 3 may be represented by a plurality of constant current sources in the figure, and it can be seen that the providing module of the power supply may supply power to the two-stage amplifying modules, that is, the amplifying module 11 of the first stage and the amplifying module 12 of the second stage provide respective constant current sources or bias voltages.
More specifically, the amplifying module 11 of the first stage may include a first differential input tube Q1 and a second differential input tube Q2, wherein the power supply module may provide a constant current source to the first differential input tube Q1 and the second differential input tube Q2, so that the differential input tube Q1 and the differential input tube Q2 can work normally. As shown in fig. 3, the gates of the first PMOS transistor QP1 and the second PMOS transistor QP2 in the secondary amplification module 12 are connected and connected to a bias voltage Vbi, which is also provided by the power supply module, and the power supply module can also provide a constant current source for the first PMOS transistor QP1 and the second PMOS transistor QP2, so as to ensure that the first PMOS transistor QP1 and the second PMOS transistor QP2 can work normally.
It can be understood that, after the power supply module provides the bias voltage Vbi and the constant current source to the first-stage amplification module 11 and the second-stage amplification module 12, the amplification circuit 10 may perform first-stage amplification on the input differential signal by using the first-stage amplification module 11, and after the first-stage amplification, amplify the signal after the first-stage amplification by using the second-stage amplification module 12 to perform second-stage amplification, so as to obtain an amplified signal after the second-stage amplification of the differential signal input to the amplifier circuit 10. It can be understood that, since the amplification module 12 provided with the second stage in this embodiment is composed of the first PMOS transistor QP1 and the second PMOS transistor QP2, and the connection manner thereof can refer to the connection manner shown in fig. 3, the amplifier circuit 10 shown in this embodiment can increase the circuit gain and simultaneously take into account the common mode rejection range of the circuit.
In one embodiment of the present invention, as shown in fig. 4, the power supply module may include an asymmetric current mirror unit 131, a first constant current source unit 132, a first load unit 133, and a second load unit 134.
The asymmetric current mirror unit 131 can be used to generate a constant voltage source, and supply the generated constant voltage source to the first PMOS transistor QP1 and the second PMOS transistor QP2 with the first bias voltage Vbi; the first constant current source unit 132 may process the second bias voltage provided by the asymmetric current mirror unit 131, generate a first constant current source, and provide the first constant current source to the first differential input tube Q1 and the second differential input tube Q2 in the amplification module 11 of the first stage; the first load unit 133 may provide a second constant current source to the first differential input transistor Q1 and the first PMOS transistor QP1, and may also provide a third constant current source to the second differential input transistor Q2 and the second PMOS transistor QP 1; the second load unit 134 may provide a fourth constant current to the first PMOS transistor QP1, and may also provide a fifth constant current source to the second PMOS transistor QP1
Specifically, referring to fig. 4, the power supply module in this embodiment may include an asymmetric current mirror unit 131, a first constant current source unit 132, a first load unit 133, and a second load unit 134. Further, referring to fig. 3 and 4, a specific power supply method for supplying power to the first-stage amplification module 11 and the second-stage amplification module 12 by the power supply module is as follows, wherein the first differential input tube Q1 and the second differential input tube Q2 in the first-stage amplification module 11 may be respectively provided by the first load unit 133 and the asymmetric current mirror unit 131 in cooperation with the first constant current source unit 132, as can be seen from fig. 3, the second constant current source and the third constant current source are provided at one end of the first-stage amplification module 11 connected to the second-stage amplification module 12, and the first constant current source, the fourth constant current source and the fifth constant current source may be provided at the other end of the first-stage amplification module 11 connected to the second-stage amplification module 12.
More specifically, referring to fig. 4, the asymmetric current mirror unit 131 may be formed by connecting a plurality of MOS transistors, and when the asymmetric current mirror unit 131 provides a bias voltage to the outside, different bias voltages may be extracted from the output terminals of different cascaded MOS transistors, for example, a first bias voltage Vbi may be provided to the first PMOS transistor QP1 and the second PMOS transistor QP2, and a second bias voltage may be provided to the first constant current source unit 132. The first constant current source unit 132, after receiving the second bias voltage, may process the second bias voltage to obtain a first constant current source, which may be provided to the amplification module 11 of the first stage, and specifically, may be provided to the sources of the first differential input tube Q1 and the second differential input tube Q2 in the amplification module 11 of the first stage.
The first load unit 133 may provide a second constant current source to the first differential input transistor Q1, and at the same time, the second constant current source may also be provided to the first PMOS transistor QP1, that is, the first differential input transistor Q1 and the first PMOS transistor QP1 may be simultaneously provided with power by the second constant current source, so as to ensure that the first differential input transistor Q1 and the first PMOS transistor QP1 can work normally. More specifically, the second constant current source may be connected to the drain of the first differential input transistor Q1, and the second constant current source may be connected to the source of the first PMOS transistor QP 1. The first load unit 133 may further provide a third constant current source to the second differential input transistor Q2, and the third constant current source may also be provided to the second PMOS transistor QP2, that is, the second differential input transistor Q2 and the second PMOS transistor QP2 may be simultaneously provided with power by the third constant current source, so as to ensure that the second differential input transistor Q2 and the second PMOS transistor QP2 can work normally. More specifically, the third constant current source may be connected to the drain of the second differential input transistor Q2, and the third constant current source may be connected to the source of the second PMOS transistor QP 2.
The second load unit 134 may provide a fourth constant current source to the first PMOS transistor QP1 to ensure that the first PMOS transistor QP1 can work normally. More specifically, the fourth constant current source may be connected to the drain of the first PMOS transistor QP 1. The second load unit 134 may also provide a fifth constant current source to the second PMOS transistor QP2 to ensure that the second PMOS transistor QP2 can work normally. More specifically, the fifth constant current source may be connected to the drain of the second PMOS transistor QP 2.
In this embodiment, the first differential input transistor Q1 and the second differential input transistor Q2 are a first NMOS transistor and a second NMOS transistor, respectively, wherein the gate of the first NMOS transistor and the gate of the second NMOS transistor can input external differential signals, the source of the first NMOS transistor and the source of the second NMOS transistor can be connected to the first constant current source after being connected to each other, the drain of the first NMOS transistor can be connected to the second constant current source, and the drain of the second NMOS transistor can be connected to the third constant current source. The gate of the first POMS transistor QP1 may be connected to the gate of the second PMOS transistor QP2, and after connection, may be connected to a first bias voltage, the source of the first PMOS transistor QP1 may be connected to a second constant current source, the drain of the first PMOS transistor QP1 may be connected to a fourth constant current source, the source of the second PMOS transistor QP2 may be connected to a third constant current source, and the drain of the second PMOS transistor QP2 may be connected to a fifth constant current source.
Specifically, as shown in fig. 4, in the first-stage amplification module 11 in this embodiment, the first differential input tube Q1 and the second differential input tube Q2 may be configured as NMOS tubes, where the first differential input tube Q1 is a first NMOS tube, and the second differential input tube Q2 is a second NMOS tube, where a gate of the first NMOS tube may be used as a positive terminal of an externally input differential signal, and a gate of the second NMOS tube may be used as a negative terminal of the externally input differential signal. In this embodiment, the source electrode in the first NMOS transistor may be further connected to the source electrode in the second NMOS transistor, and then connected to the first constant current source unit 132, so that the first constant current source unit 132 may generate a first constant current source according to a second bias voltage provided by the asymmetric current mirror unit 131 after obtaining the second bias voltage, and further connect the first constant current source to the source electrodes in the first NMOS transistor and the second NMOS transistor.
The drain electrode in the first NMOS transistor can be further connected with a second constant current source and the source electrode of the first PMOS transistor QP1, that is, the second constant current source is connected with the drain electrode in the first NMOS transistor and the source electrode of the first PMOS transistor QP 1; the drain of the second NMOS transistor may be further connected to a third constant current source and the source of the second PMOS transistor QP2, that is, the third constant current source is connected to the sources of the second NMOS transistor and the second PMOS transistor QP 2.
The gate of the first PMOS transistor QP1 may be connected to the gate of the second PMOS transistor QP2 and to a first bias voltage, which may be provided by the asymmetric current mirror unit 131. The drain of the first PMOS transistor QP1 is connected to the second load unit 134, and the second load unit 134 can generate a fourth constant current source under the action of the asymmetric current mirror unit 131, and provide the fourth constant current source to the drain of the first PMOS transistor QP1, so as to ensure that the first PMOS transistor QP1 can work normally; the drain of the second PMOS transistor QP2 is connected to the second load unit 134, and the second load unit 134 may generate a fifth constant current source under the action of the asymmetric current mirror unit 131, and provide the fifth constant current source to the drain of the second PMOS transistor QP2, so as to ensure that the second PMOS transistor QP2 can operate normally.
In this embodiment, the first load unit 133 includes a third PMOS transistor QP3 and a fourth PMOS transistor QP 4.
The gate of the third PMOS transistor QP3 may be connected to the drain, and after connection, may output a second constant current source, and the source of the third PMOS transistor QP3 may be connected to the power VCC; the gate of the fourth PMOS transistor QP4 may be connected to the gate of the third PMOS transistor QP3, and a third constant current source may be output from the fourth PMOS transistor QP4, while the source of the fourth PMOS transistor QP4 is also connected to the power source VCC.
Specifically, referring to fig. 4, the load unit 133 includes a third PMOS transistor QP3 and a fourth PMOS transistor QP4, a gate of the third PMOS transistor QP3 is connected to a gate of the fourth PMOS transistor QP4, a gate of the third PMOS transistor QP3 is further connected to a drain of the third PMOS transistor QP3, and after the third PMOS transistor QP3 is connected, a second constant current source may be output to a drain of the first NMOS transistor and a source of the first PMOS transistor QP1, and a source of the third PMOS transistor QP3 may be connected to the power source VCC. The drain of the fourth PMOS transistor QP4 may output a third constant current source, that is, the fourth PMOS transistor QP4 may output the third constant current source to the drain of the second NMOS transistor Q1 and the source of the second PMOS transistor QP2, and the source of the fourth PMOS transistor QP4 is also connected to the power source VCC.
In this embodiment, the second load unit 134 includes a third NMOS transistor Q3, a fourth NMOS transistor Q4, a fifth NMOS transistor Q5, and a sixth NMOS transistor Q6.
The gate of the third NMOS transistor Q3 may be connected to the drain, and after being connected, the gate may output a fourth constant current source; the gate of the fourth NMOS transistor Q4 may be connected to the gate of the third NMOS transistor Q3, and the drain of the fourth NMOS transistor Q4 may output a fifth constant current source; the gate of the fifth NMOS transistor Q5 may be connected to the drain, and after being connected, may be connected to the source of the third NMOS transistor Q3, and the source of the fifth NMOS transistor Q5 may be grounded; a gate of the sixth NMOS transistor Q6 may be connected to a gate of the fifth NMOS transistor Q5, a drain of the sixth NMOS transistor Q6 may be connected to a source of the fourth NMOS transistor Q4, and a source of the sixth NMOS transistor Q6 is grounded.
Specifically, as shown in fig. 4, the second load unit 134 may include four NMOS transistors, including a third NMOS transistor Q3, a fourth NMOS transistor Q4, a fifth NMOS transistor Q5, and a sixth NMOS transistor Q6, respectively. The source electrode of the third NMOS transistor Q3 may be connected to the gate electrode, and output a fourth constant current source, which is further provided to the connected first PMOS transistor QP1 and input from the drain electrode of the first PMOS transistor QP 1; the source of the fourth NMOS transistor Q4 may be used as the output of the fifth constant current source, and further input to the drain of the second PMOS transistor QP 2. Through the connection between the NMOS transistors in the second load unit 134, the fourth constant current source and the fifth constant current source can be provided to the second-stage amplification module 12, so as to ensure that the second-stage amplification module 12 can work normally.
In an embodiment of the present invention, the first constant current source unit 132 may include a seventh NMOS transistor Q7, wherein a gate of the seventh NMOS transistor Q7 may be connected to the second bias voltage, a drain of the seventh NMOS transistor Q7 may be grounded, and a drain of the seventh NMOS transistor Q7 may serve as an output terminal of the first constant current source to output the first constant current source.
Specifically, referring to fig. 7, wherein a first constant current source unit 132 may be used to provide a first constant current source for the amplification module 11 of the first stage. More specifically, the gate of the seventh NMOS transistor Q7 may be connected to the asymmetric current mirror unit 131 for receiving a second bias voltage outputted by the asymmetric current mirror unit 131, and after the bias voltage is inputted from the seventh NMOS transistor Q7, the seventh NMOS transistor Q7 may process the second bias voltage, so that the drain of the seventh NMOS transistor Q7 may output the first constant current source, and the source of the seventh NMOS transistor Q7 in this embodiment may be grounded.
It should be noted that the amplifying module 11 and the first constant current source unit 132 in the first stage in this embodiment may operate in a saturated constant current source region, that is, the first differential input transistor Q2, the second differential input transistor Q1, and the seventh NMOS transistor in this embodiment all operate in a saturated constant current source region.
In summary, with the connection structure of the components of the amplifier circuit in the above embodiment, the first differential input terminal Q1 and the second differential input terminal Q2 can be used for the input amplification of the first stage; the first and second PMOS transistors QP1 and QP2 are the input amplification of the second stage. Meanwhile, in the second stage of the amplifying circuit 12, the types of the MOS transistors are all P-type, so the first bias voltage Vbi has no limiting effect on the source input. It should be noted that the common mode range in this embodiment may be Vth +2 Δ -VCC, and it is only necessary to ensure that the first differential input tube Q2, the second differential input tube Q1, and the seventh NMOS all operate in a saturated constant current source region. Where Vth is a threshold voltage of the differential input tube and Δ is an overdrive voltage.
The common mode range and the gain in the embodiment of the present invention are described with reference to fig. 5, where fig. 5 is a common source amplifier circuit, where Vin is an input signal, Rout is an output impedance, and the NMOS transistor is an amplifying transistor, which is essentially a voltage-controlled current source, and the amplification factor of the circuit can be defined as transconductance gm, i.e., gm ═ Δ I/Δ V, where the input voltage is Vin, so that the generated current I ═ gm ═ Vin, and the generated current acts on the output impedance Rout, so that the generated voltage Vout ═ I ═ Rout ═ gm ═ Rout, Vin, so that the gain of the circuit is Av ═ Vout/Vin. It will be appreciated that for a two-stage amplification circuit, the overall gain of the circuit may be Av gm Rout gm1 Rout 1. Where gm1 is the amplification factor of the amplification circuit of the second stage and Rout1 is the output impedance of the amplification circuit of the second stage. The first differential input tube Q1 needs to work in a saturated constant current source region to have gain, and then Va-Vb is larger than or equal to delta, wherein Va is the drain voltage of the differential input tube Q1, Vb is the source voltage of the differential input tube Q2, and Vgs is the conducting voltage of the grid electrode and the source electrode of the differential input tube Q1; the MOS tube in the amplifier circuit of the second stage also needs to work in a saturated constant current source region to have gain, if the MOS tube in the amplifier of the second stage is of an N type, as shown in figure 2, Vc-Va is more than or equal to Vgs, wherein Vc is the grid voltage of MN3, and Va is the source voltage of MN 3. Therefore, Vb is less than or equal to Vc-Vgs-delta, and the output signals Vin + and Vin-in the saturated constant current source region should be higher than the voltage at the point b by Vgs, namely, Vin-Vb is Vgs. Therefore, Vin is less than or equal to Vc-delta, namely Vin is less than or equal to Vbi-delta. The constant current source CC works in a saturated constant current source region, therefore Vb is larger than or equal to delta, and in combination with Vin-Vb being Vgs, Vin is larger than or equal to delta + Vgs, and since Vgs being Vth + delta, Vin is larger than or equal to Vth +2 delta. Therefore, if the MOS transistor in the amplifier of the second stage is of the N type, the common mode range is from Vth +2 delta to Vbi-delta, and obviously, the range is obviously reduced compared with a circuit with single-stage amplification.
Since the amplifier module of the second stage in this embodiment is a P-type MOS transistor, as shown in FIG. 3, it needs to satisfy Vs-Vbi ≧ Vgs, which is different from Vc-Va ≧ Vgs of the above-mentioned N-type MOS transistor, where Vs is the source voltage of the first PMOS transistor QP1, and Vs has no maximum value. After calculation by the method, the common mode range of the P-type MOS tube can be obtained to be Vth +2 delta-VCC.
It should be noted that, the process of the amplifier circuit in this embodiment may also be selected from 0.18um to 0.35um, and a CMOS process or a BJT (Bipolar Junction Transistor) process may also be adopted for preparation
In summary, the amplifier circuit according to the embodiment of the present invention can increase the circuit gain and simultaneously consider the common mode rejection range of the circuit.
Fig. 6 is a block diagram of a chip according to an embodiment of the invention.
As shown in fig. 6, further, the present invention proposes a chip 100, which includes the amplifier circuit 10 in the above embodiment.
The chip in the embodiment of the invention can increase the circuit gain and simultaneously give consideration to the common mode rejection range of the circuit through the amplifier circuit in the embodiment.
Fig. 7 is a block diagram of a home appliance according to an embodiment of the present invention.
As shown in fig. 7, the present invention further provides a home device 200, where the home device 200 includes the amplifier circuit in the above embodiment.
The household appliance of the embodiment of the invention can increase the circuit gain and simultaneously give consideration to the common mode rejection range of the circuit through the amplifier circuit in the embodiment.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
Furthermore, the terms "first", "second", and the like used in the embodiments of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated in the embodiments. Thus, a feature of an embodiment of the present invention that is defined by the terms "first," "second," etc. may explicitly or implicitly indicate that at least one of the feature is included in the embodiment. In the description of the present invention, the word "plurality" means at least two or two and more, such as two, three, four, etc., unless specifically limited otherwise in the examples.
In the present invention, unless otherwise explicitly stated or limited by the relevant description or limitation, the terms "mounted," "connected," and "fixed" in the embodiments are to be understood in a broad sense, for example, the connection may be a fixed connection, a detachable connection, or an integrated connection, and it may be understood that the connection may also be a mechanical connection, an electrical connection, etc.; of course, they may be directly connected or indirectly connected through intervening media, or they may be interconnected within one another or in an interactive relationship. Those of ordinary skill in the art will understand the specific meaning of the above terms in the present invention according to their specific implementation.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (10)
1. An amplifier circuit, comprising:
the primary amplification module comprises a first differential input tube and a second differential input tube;
the second-stage amplification module comprises a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube;
and the power supply providing module is used for providing a constant current source for the first differential input tube and the second differential input tube and providing a bias voltage and a constant current source for the first PMOS tube and the second PMOS tube, so that the first-stage amplification module performs first-stage amplification on the input differential signal and then performs second-stage amplification by the second-stage amplification module.
2. The amplifier circuit of claim 1, wherein the power supply module comprises:
the asymmetric current mirror unit is used for generating a constant voltage source to provide a first bias voltage for the first PMOS tube and the second PMOS tube;
a first constant current source unit for generating a first constant current source according to a second bias voltage supplied from the asymmetric current mirror unit to supply to the first differential input tube and the second differential input tube;
the first load unit is used for respectively providing a second constant current source for the first differential input tube and the first PMOS tube and respectively providing a third constant current source for the second differential input tube and the second PMOS tube;
and the second load unit is used for providing a fourth constant current source for the first PMOS tube and providing a fifth constant current source for the second PMOS tube.
3. The amplifier circuit according to claim 2, wherein the first differential input transistor and the second differential input transistor are a first NMOS transistor and a second NMOS transistor, respectively, a gate of the first NMOS transistor and a gate of the second NMOS transistor input a differential signal, a source of the first NMOS transistor is connected to a source of the second NMOS transistor and then connected to the first constant current source, a drain of the first NMOS transistor is connected to the second constant current source, and a drain of the second NMOS transistor is connected to the third constant current source.
4. The amplifier circuit of claim 2, wherein a gate of the first POMS transistor is connected to a gate of the second PMOS transistor and then connected to the first bias voltage, a source of the first PMOS transistor is connected to the second constant current source, a drain of the first PMOS transistor is connected to the fourth constant current source, a source of the second PMOS transistor is connected to the third constant current source, and a drain of the second PMOS transistor is connected to the fifth constant current source.
5. The amplifier circuit of claim 2, wherein the first load unit comprises:
the grid electrode of the third PMOS tube is connected with the drain electrode of the third PMOS tube, then the second constant current source is output, and the source electrode of the third PMOS tube is connected to the VCC power supply;
and the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, the fourth PMOS tube outputs the third constant current source, and the source electrode of the fourth PMOS tube is connected to the VCC power supply.
6. The amplifier circuit of claim 2, wherein the second load unit comprises:
the grid electrode of the third NMOS tube is connected with the drain electrode of the third NMOS tube, and then the fourth constant current source is output;
a grid electrode of the fourth NMOS tube is connected with a grid electrode of the third NMOS tube, and a drain electrode of the fourth NMOS tube outputs the fifth constant current source;
a fifth NMOS tube, wherein a grid electrode of the fifth NMOS tube is connected with a drain electrode of the fifth NMOS tube and then is connected to a source electrode of the third NMOS tube, and the source electrode of the fifth NMOS tube is grounded;
and the grid electrode of the sixth NMOS tube is connected with the grid electrode of the fifth NMOS tube, the drain electrode of the sixth NMOS tube is connected with the source electrode of the fourth NMOS tube, and the source electrode of the sixth NMOS tube is grounded.
7. The amplifier circuit according to claim 2, wherein the first constant current source unit includes a seventh NMOS transistor, a gate of the seventh NMOS transistor is connected to the second bias voltage, a source of the seventh NMOS transistor is grounded, and a drain of the seventh NMOS transistor outputs the first constant current source.
8. The amplifier circuit of claim 7, wherein the first and second differential input transistors and the seventh NMOS transistor operate in a saturated constant current source region.
9. A chip comprising an amplifier circuit as claimed in any one of claims 1 to 8.
10. An electrical household appliance comprising an amplifier circuit as claimed in any one of claims 1 to 8.
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| CN202110935357.9A CN114389553B (en) | 2021-08-16 | 2021-08-16 | Amplifier circuit, chip and household appliance |
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| CN202110935357.9A CN114389553B (en) | 2021-08-16 | 2021-08-16 | Amplifier circuit, chip and household appliance |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030095003A1 (en) * | 2001-11-19 | 2003-05-22 | Broadcom Corporation | Wide common mode differential input amplifier and method |
| US20060049873A1 (en) * | 2004-09-07 | 2006-03-09 | Britton Charles L Jr | Rail-to-rail differential input amplification stage with main and surrogate differential pairs |
| CN104218904A (en) * | 2013-05-29 | 2014-12-17 | 上海华虹宏力半导体制造有限公司 | Rail-to-rail-input AB-class-output full-differential operational amplifier |
| CN110649903A (en) * | 2019-10-28 | 2020-01-03 | 苏州英嘉通半导体有限公司 | Differential amplifier with high common-mode dynamic range and constant PVT |
| CN111464139A (en) * | 2020-04-24 | 2020-07-28 | 电子科技大学 | Common-mode feedback circuit suitable for wide-swing fully-differential operational amplifier |
-
2021
- 2021-08-16 CN CN202110935357.9A patent/CN114389553B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030095003A1 (en) * | 2001-11-19 | 2003-05-22 | Broadcom Corporation | Wide common mode differential input amplifier and method |
| US20060049873A1 (en) * | 2004-09-07 | 2006-03-09 | Britton Charles L Jr | Rail-to-rail differential input amplification stage with main and surrogate differential pairs |
| CN104218904A (en) * | 2013-05-29 | 2014-12-17 | 上海华虹宏力半导体制造有限公司 | Rail-to-rail-input AB-class-output full-differential operational amplifier |
| CN110649903A (en) * | 2019-10-28 | 2020-01-03 | 苏州英嘉通半导体有限公司 | Differential amplifier with high common-mode dynamic range and constant PVT |
| CN111464139A (en) * | 2020-04-24 | 2020-07-28 | 电子科技大学 | Common-mode feedback circuit suitable for wide-swing fully-differential operational amplifier |
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| CN114389553B (en) | 2023-01-24 |
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