CN107301308B - Constant transconductance full-swing operational amplifier - Google Patents
Constant transconductance full-swing operational amplifier Download PDFInfo
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- CN107301308B CN107301308B CN201710699203.8A CN201710699203A CN107301308B CN 107301308 B CN107301308 B CN 107301308B CN 201710699203 A CN201710699203 A CN 201710699203A CN 107301308 B CN107301308 B CN 107301308B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45376—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using junction FET transistors as the active amplifying circuit
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention relates to a constant transconductance full-swing operational amplifier, which comprises a rail-to-rail input stage, a gain stage and an output stage which are sequentially connected, wherein the rail-to-rail input stage comprises a complementary PMOS differential pair and NMOS differential pair, a tail current source of the PMOS differential pair and the NMOS differential pair, and a load circuit of the NMOS differential pair; the gain stage comprises a self-bias common-source common-gate current mirror, the source electrodes of the PMOS tube and the NMOS tube of the PMOS differential pair and the NMOS differential pair are connected with the self-bias common-source common-gate current mirror, the output stage comprises a first PMOS tube and a first NMOS tube which are connected with the common source electrodes, and a Miller compensation, the grid electrodes of the first PMOS tube and the first NMOS tube are connected with the self-bias common-source common-gate current mirror, and the Miller compensation is realized by adopting a Miller compensation capacitor and a compensation resistor which are connected in series. The operational amplifier can effectively ensure the constancy of the transconductance of the input stage in the full-voltage working range, has good stability of the whole circuit structure, widens the working voltage range of the operational amplifier, can be used for low-voltage application, and simultaneously improves the common-mode rejection ratio of the operational amplifier.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to an operational amplifier, and especially relates to a rail-to-rail folded cascode transconductor full-swing operational amplifier.
Background
The conventional rail-to-rail operational amplifier uses complementary PMOS and NMOS differential pairs as input stages, and the structure is shown in fig. 1, where M2 and M3 are PMOS differential input pairs, and M1 and M4 are NMOS differential input pairs. Thus, in a lower input voltage range, the PMOS differential input pair works and the NMOS differential pair is turned off; in a higher input voltage range, the NMOS differential input pair works, and the PMOS differential pair is turned off; only in the middle input voltage range, the NMOS and PMOS differential pairs work simultaneously. Thereby, the total common-mode input range is obtained as full swing V SS ＜V CM ＜V DD 。
However, there are three operating states for the input stage of the rail-to-rail operational amplifier due to this structure: PMOS or NMOS operate separately and simultaneously, and therefore, there is a problem in that transconductance is not constant. This makes frequency compensation difficult when the unity gain bandwidth varies significantly. As shown in fig. 2, which shows the curve of the input stage equivalent transconductance with the common-mode input voltage, it can be seen that the transconductance varies by a factor of 2 at maximum in the whole range, and this has a considerable influence on the common-mode rejection ratio and stability.
Disclosure of Invention
The invention aims to provide a constant transconductance full-swing operational amplifier, which has ingenious overall structural design, ensures the constant transconductance of the input stage of the full-swing operational amplifier in a full-power voltage working range by improving the input stage circuit structure of the operational amplifier, has good stability of the overall circuit structure, and has the maximum output swing close to the full-power voltage range of 0-V DD 。
In order to achieve the above purpose, the technical scheme adopted by the invention is that the constant transconductance full swing operational amplifier comprises a rail-to-rail input stage, a gain stage and an output stage which are sequentially connected, wherein the rail-to-rail input stage comprises a complementary PMOS differential pair, an NMOS differential pair, a tail current source of the PMOS differential pair, a load circuit of the NMOS differential pair, wherein the PMOS differential pair is realized by adopting two PMOS tubes connected with common sources, the grid of one PMOS tube is led out to serve as a non-inverting input end of the operational amplifier, the grid of the other PMOS tube is led out to serve as an inverting input end of the operational amplifier, the grid of one NMOS tube is led out to serve as an inverting input end of the operational amplifier, the tail current source of the PMOS differential pair is connected with the source of the PMOS differential pair and the power supply voltage VDD, the tail current source of the NMOS differential pair is connected with the source of the NMOS differential pair and the ground, the tail current source of the NMOS differential pair is connected with the tail current source of the NMOS differential pair through a proportion, and the drain of the differential pair is connected with the load circuit of the differential pair; the gain stage comprises a self-bias cascode current mirror, the drain electrode of an NMOS tube of the NMOS differential pair is connected with the self-bias cascode current mirror, the self-bias cascode current mirror is connected with a power supply voltage VDD, the output stage comprises a first PMOS tube, a first NMOS tube and a Miller compensation, the common source electrode of the first PMOS tube is connected with a bias voltage Vb, the grid electrode of the first NMOS tube is connected with the output of the gain stage, the Miller compensation is realized by adopting a Miller compensation capacitor and a compensation resistor which are connected in series, the two compensation resistors are respectively connected with the two ends of the self-bias cascode current mirror, the Miller compensation capacitor is connected with the drain electrodes of the first PMOS tube and the first NMOS tube, the drain electrodes of the first PMOS tube and the first NMOS tube are led out to serve as the output end of the operational amplifier, the source electrode of the first PMOS tube is connected with the power supply voltage VDD, and the source electrode of the first NMOS tube is grounded.
As an improvement of the invention, the tail current source of the PMOS differential pair adopts a second PMOS tube, the tail current source of the NMOS differential pair adopts a second NMOS tube, a current extraction and replication circuit is arranged between the PMOS differential pair and the tail current source of the NMOS differential pair, the current extraction and replication circuit comprises a third PMOS tube, a regulating resistor and a current mirror formed by the third NMOS tube and a fourth NMOS tube, the source electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube, the drain electrode of the third PMOS tube is connected with one end of the regulating resistor, the other end of the regulating resistor is connected with the drain electrode and the grid electrode of the third NMOS tube, the source electrode of the fourth NMOS tube is grounded, the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth PMOS tube, the drain electrode of the second PMOS tube is connected with the source electrode of the PMOS differential pair, the source electrode of the second PMOS tube is connected with a power supply voltage VDD, the grid electrode of the second PMOS tube is connected with a bias voltage Vb, the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is connected with the source electrode of the NMOS differential pair.
As an improvement of the invention, the load circuit of the NMOS differential pair comprises a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube, wherein the fifth PMOS tube and the sixth PMOS tube are used as loads of the NMOS differential pair, the fourth PMOS tube provides bias for the fifth PMOS tube and the sixth PMOS tube, the sources of the fourth PMOS tube to the sixth PMOS tube are connected with a power supply voltage VDD, the grid of the fourth PMOS tube is connected with the grid of the fifth PMOS tube, the grid of the fifth PMOS tube is connected with the grid of the sixth PMOS tube, the grid of the fourth PMOS tube is connected with the drain of the fourth NMOS tube, and the drains of the fifth PMOS tube and the sixth PMOS tube are connected with the drain of the NMOS tube of the NMOS differential pair.
As an improvement of the invention, a first bias voltage providing circuit is connected to the grid electrode of the third PMOS tube, the first bias voltage providing circuit comprises a seventh PMOS tube and an eighth PMOS tube, the source electrode of the seventh PMOS tube is connected with the power supply voltage VDD, the grid electrode of the seventh PMOS tube is connected with the grid electrode of the eighth PMOS tube, the drain electrode of the seventh PMOS tube is connected with the source electrode of the eighth PMOS tube, and the grid electrode of the eighth PMOS tube is connected with the grid electrode of the third PMOS tube.
As an improvement of the invention, the gain stage further comprises a self-bias cascode current source, the self-bias cascode current mirror comprises a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a ninth NMOS tube, a tenth NMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube and a fifteenth PMOS tube, the self-bias cascode current source comprises a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, the ninth PMOS tube, the tenth PMOS tube, the twelfth PMOS tube and the thirteenth PMOS tube, the source electrode of the ninth PMOS tube is connected with a power supply voltage VDD, the grid electrode of the ninth PMOS tube, the twelfth PMOS tube and the fourteenth PMOS tube is connected with a bias voltage Vb, the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube, the drain electrode of the tenth PMOS tube is connected with the source electrode of the eleventh PMOS tube, the drain electrode of the eleventh PMOS tube is connected with the drain electrode of the tenth NMOS tube, the grid electrode of the tenth PMOS tube is connected with the drain electrode of the eleventh PMOS tube, the drain electrode of the twelfth PMOS tube is connected with the source electrode of the thirteenth PMOS tube, the grid electrode of the eleventh PMOS tube is connected with the grid electrodes of the thirteenth PMOS tube and the fifteenth PMOS tube, the drain electrode of the fifteenth PMOS tube is connected with the grid electrode of the first NMOS tube, the fifth NMOS tube is connected with the grid electrode of the sixth NMOS tube, the seventh NMOS tube is connected with the grid electrode of the eighth NMOS tube, the grid electrode of the ninth NMOS tube is connected with the grid electrode of the tenth NMOS tube, the source electrode of the fifth NMOS tube is connected with the drain electrode of the seventh NMOS tube, the source electrodes of the sixth NMOS tube are connected with the drain electrode of the eighth NMOS tube, and the seventh NMOS tube and the source electrodes of the ninth NMOS tube and the tenth NMOS tube are grounded; the drain electrodes of the twelfth PMOS tube and the fourteenth PMOS tube are respectively connected with the drain electrodes of the NMOS tubes of the NMOS differential pair, and the source electrodes of the fifth NMOS tube and the sixth NMOS tube are connected with the drain electrodes of the PMOS tubes of the PMOS differential pair.
As an improvement of the invention, the self-bias cascode current mirror is connected with a second bias voltage supply circuit, the second bias voltage supply circuit comprises an eleventh NMOS tube, the grid electrode of the eleventh NMOS tube is connected with the grid electrodes of the ninth NMOS tube and the tenth NMOS tube, the drain electrode of the eleventh NMOS tube is connected with the drain electrode of the eighth PMOS tube, and the source electrode of the eleventh NMOS tube is grounded.
As an improvement of the invention, the number of the Miller compensation is 2, and the Miller compensation comprises a first Miller compensation capacitor, a first compensation resistor, a second Miller compensation capacitor and a second compensation resistor, wherein the first Miller compensation capacitor is connected with the first compensation resistor in series, the second Miller compensation capacitor is connected with the second compensation resistor in series, the first compensation resistor is connected with the power supply voltage VDD, the second compensation resistor is connected with the drain electrode of the fifteenth PMOS tube, and the first Miller compensation capacitor and the second Miller compensation capacitor are connected with the drain electrodes of the first PMOS tube and the first NMOS tube.
Compared with the prior art, the circuit structure of the constant transconductance full-swing operational amplifier provided by the invention consists of a rail-to-rail input stage, a gain stage and an output stage, wherein the full swing of 0-VDD in a common-mode input range is realized by means of complementary PMOS and NMOS differential pairs in the rail-to-rail input stage, and a self-bias common-source common-gate current mirror is adopted as a load for an intermediate gain stage, so that the working range of the constant transconductance full-swing operational amplifier is twice more than that of the traditional common-source common-gate operational amplifier ON (the overdrive voltage is the gate-source voltage V GS And threshold voltage V T The difference value of the voltage range is equal to the maximum output swing of the full power supply voltage range, the working voltage range of the operational amplifier is effectively widened, and the operational amplifier can be used for low-voltage application occasions. In addition, the rail-to-rail input stage of the operational amplifier also adopts a second PMOS tube as a tail current source of the PMOS differential pair and adopts a second NMOS tube as a tail current source of the NMOS differential pair, and the common mode input level V is that CM When the temperature is increased to a certain degree, the second PMOS tube is opened to lead the second PMOS tube to be introduced from the outsideQuasi-current source I ref And extracting current and copying the current to the second NMOS tube under the regulation and control action of the current extraction and copying circuit, so that the sum of tail currents of the PMOS differential pair and the NMOS differential pair is constant no matter the PMOS differential pair and the NMOS differential pair work independently or work simultaneously, the equivalent transconductance of the input stage is constant, and the common mode rejection ratio of the operational amplifier is effectively improved.
Drawings
Fig. 1 is a block diagram of a conventional rail-to-rail operational amplifier.
Fig. 2 is a graph of the input stage equivalent transconductance of a conventional rail-to-rail operational amplifier as a function of common-mode input voltage.
Fig. 3 is a circuit configuration diagram of the transconductor full-swing operational amplifier of the present invention.
Fig. 4 is a simplified circuit diagram of an input stage of a transconductor full-swing operational amplifier according to the present invention.
Fig. 5 is a graph of constant transconductance versus common-mode input voltage for a full-swing operational amplifier of the present invention across a full operating range.
Detailed Description
The present invention is further described and illustrated below in conjunction with the accompanying drawings in order to enhance the understanding and appreciation of the invention.
As shown in fig. 3 and 4, a constant transconductance full swing operational amplifier comprises a rail-to-rail input stage, a gain stage and an output stage which are sequentially connected, wherein the rail-to-rail input stage comprises a complementary PMOS differential pair and an NMOS differential pair, a PMOS differential pair and a NMOS differential pair tail current source and an NMOS differential pair load circuit, the PMOS differential pair is realized by adopting two PMOS transistors M5 and M6 connected with common sources, wherein the gate lead of the PMOS transistor M5 is used as the non-inverting input end of the operational amplifier, the gate lead of the PMOS transistor M6 is used as the inverting input end of the operational amplifier, the NMOS differential pair is realized by adopting two NMOS transistors M12 and M14 connected with common sources, the gate lead of the NMOS transistor M12 is used as the non-inverting input end of the operational amplifier, the PMOS differential pair tail current source is connected with the PMOS transistor source and the power supply voltage VDD of the PMOS differential pair, and the NMOS differential pair tail current source is connected withThe source electrode of the NMOS tube of the NMOS differential pair is connected with the ground, the tail current source of the PMOS differential pair is connected with the tail current source of the NMOS differential pair through a proportional current mirror, and the load circuit of the NMOS differential pair is connected with the drain electrode of the NMOS differential pair and the power supply voltage VDD; the gain stage comprises a self-bias cascode current mirror, drain electrodes of NMOS tubes M12 and M14 of the NMOS differential pair are connected with the self-bias cascode current mirror, the self-bias cascode current mirror is connected with a power supply voltage VDD, the output stage comprises a first PMOS tube M29 and a first NMOS tube M30 which are connected with a common source electrode, a Miller compensation is carried out, a grid electrode of the first PMOS tube M29 is connected with a bias voltage Vb, a grid electrode of the first NMOS tube M30 is connected with an output of the gain stage, the Miller compensation is realized by adopting Miller compensation capacitors and compensation resistors in series, the two compensation resistors are respectively connected with two ends of the self-bias cascode current mirror, meanwhile, the two compensation resistors are also respectively connected with the bias voltage Vb and an output of the gain stage, the Miller compensation capacitors are connected with the drain electrodes of the first PMOS tube M29 and the first NMOS tube M30, the drain electrodes of the first PMOS tube M29 are led out to serve as output ends of an operational amplifier, the source electrode of the first PMOS tube M29 is connected with the power supply voltage, and the source electrode of the first NMOS tube M30 is grounded to VDD. The operational amplifier provided by the invention realizes the full swing of 0-V in the common-mode input range by means of complementary PMOS and NMOS differential pairs in the input stage DD The self-bias common-source common-gate current mirror is adopted as load in the intermediate gain stage, and the overdrive voltage V is twice more than the working range of the traditional common-source common-gate operational amplifier ON (is the gate-source voltage V GS And threshold voltage V T The difference value of the voltage range is equal to the maximum output swing range, the common source stage is connected with the PMOS tube and the NMOS tube, and the miller compensation is realized by serially connecting the miller compensation capacitor and the compensation resistor, so that the whole circuit structure achieves good stability, the maximum output swing is close to the full power supply voltage range of 0-VDD, the working voltage range of the operational amplifier is effectively widened, and the operational amplifier can be used for low-voltage application occasions.
Preferably, the tail current source of the PMOS differential pair adopts a second PMOS transistor M4, the tail current source of the NMOS differential pair adopts a second NMOS transistor M15, and a current extraction and replication circuit is arranged between the tail current sources of the PMOS differential pair and the NMOS differential pair, and the power supply is provided with a power supply circuitThe current extraction and replication circuit comprises a third PMOS tube M7, a regulating resistor R and a current mirror formed by a third NMOS tube M8 and a fourth NMOS tube M9, wherein the source electrode of the third PMOS tube M7 is connected with the drain electrode of the second PMOS tube M4, the drain electrode of the third PMOS tube M7 is connected with one end of the regulating resistor R, the other end of the regulating resistor R is connected with the drain electrode and the grid electrode of the third NMOS tube M8, the source electrode of the third NMOS tube M8 is grounded, the source electrode of the fourth NMOS tube M9 is grounded, the grid electrode of the third NMOS tube M8 is connected with the grid electrode of the fourth NMOS tube M9, the drain electrode of the second PMOS tube M4 is connected with the source electrode of the PMOS tube of the PMOS differential pair, the source electrode of the second PMOS tube M4 is connected with the power supply voltage VDD, the grid electrode of the second PMOS tube M4 is connected with the bias voltage Vb, the source electrode of the second NMOS tube M15 is grounded, and the drain electrode of the second NMOS tube M15 is connected with the source electrode of the NMOS tube of the NMOS differential pair. Therefore, the rail-to-rail input stage of the operational amplifier also adopts the second PMOS tube as the tail current source of the PMOS differential pair and adopts the second NMOS tube as the tail current source of the NMOS differential pair, and the common mode input level V CM When the current is increased to a certain degree, the second PMOS tube is opened to lead the second PMOS tube to introduce the reference current source I from the outside ref And extracting current and copying the current to the second NMOS tube under the regulation and control action of the current extraction and copying circuit, so that the sum of tail currents of the PMOS differential pair and the NMOS differential pair is constant no matter the PMOS differential pair and the NMOS differential pair work independently or work simultaneously, the equivalent transconductance of the input stage is constant, and the common mode rejection ratio of the operational amplifier is effectively improved. The regulation resistor R in the current extraction and replication circuit is used for regulating the magnitude of extraction current, and the proportion of the current mirror formed by the third NMOS tube M8 and the fourth NMOS tube M9 is used for regulating the magnitude of current replicated to the second NMOS tube M15.
It is further preferred that the load circuit of the NMOS differential pair includes a fourth PMOS transistor M10, a fifth PMOS transistor M11, and a sixth PMOS transistor M13, where the fifth PMOS transistor M11 and the sixth PMOS transistor M13 are used as loads of the NMOS differential pair, the fourth PMOS transistor M10 provides a bias for the fifth PMOS transistor M11 and the sixth PMOS transistor M13, the fourth PMOS transistor M10, the fifth PMOS transistor M11, and the sixth PMOS transistor M13 form a current mirror, sources of the fourth to sixth PMOS transistors are connected to a power supply voltage VDD, a gate of the fourth PMOS transistor M10 is connected to a gate of the fifth PMOS transistor M11, a gate of the fifth PMOS transistor M11 is connected to a gate of the sixth PMOS transistor M13, a gate of the fourth PMOS transistor M10 is connected to a drain of the fourth NMOS transistor M9, and drains of the fifth PMOS transistor M11 and the sixth PMOS transistor M13 are connected to drains of the NMOS differential pair.
Still further preferably, the gate of the third PMOS transistor M7 is connected with a first bias voltage supply circuit, where the first bias voltage supply circuit includes a seventh PMOS transistor M1 and an eighth PMOS transistor M2, the source of the seventh PMOS transistor M1 is connected to the power supply voltage VDD, the gate of the seventh PMOS transistor M1 is connected to the gate of the eighth PMOS transistor M2, the drain of the seventh PMOS transistor M1 is connected to the source of the eighth PMOS transistor M2, and the gate of the eighth PMOS transistor M2 is connected to the gate of the third PMOS transistor M7. In FIG. 3, the bias voltage V of the third PMOS transistor M7 b1 Provided collectively by M1 and M2 of fig. 4.
Still further preferably, the gain stage further includes a self-bias cascode current source including a ninth PMOS transistor M16, a tenth PMOS transistor M17, an eleventh PMOS transistor M18, a ninth NMOS transistor M19, a tenth NMOS transistor M20, a twelfth PMOS transistor M21, a thirteenth PMOS transistor M22, a fourteenth PMOS transistor M23, and a fifteenth PMOS transistor M24, the self-bias cascode current source including a fifth NMOS transistor M25, a sixth NMOS transistor M26, a seventh NMOS transistor M27, an eighth NMOS transistor M28, a source of the ninth PMOS transistor M16, a tenth PMOS transistor M17, a twelfth PMOS transistor M21, a thirteenth PMOS transistor M22 being connected to the power supply voltage VDD, a gate of the ninth PMOS transistor M16, a twelfth PMOS transistor M21, a fourteenth PMOS transistor M23 being connected to the bias voltage Vb, a drain of the ninth PMOS transistor M16 being connected to a drain of the ninth NMOS transistor M19, a drain of the tenth PMOS transistor M17 being connected to a source of the eleventh PMOS transistor M18, the drain electrode of the eleventh PMOS tube M18 is connected with the drain electrode of the tenth NMOS tube M20, the grid electrode of the tenth PMOS tube M17 is connected with the drain electrode of the eleventh PMOS tube M18, the drain electrode of the twelfth PMOS tube M21 is connected with the source electrode of the thirteenth PMOS tube M22, the drain electrode of the fourteenth PMOS tube M23 is connected with the source electrode of the fifteenth PMOS tube M24, the grid electrode of the eleventh PMOS tube M18 is connected with the grid electrodes of the thirteenth PMOS tube M22 and the fifteenth PMOS tube M24, the drain electrode of the fifteenth PMOS tube M24 is connected with the grid electrode of the first NMOS tube M30, the grid electrodes of the fifth NMOS tube M25 and the sixth NMOS tube M26 are connected, the grid electrodes of the seventh NMOS tube M27 and the eighth NMOS tube M28 are connected, the source electrode of the fifth NMOS tube M25 is connected with the drain electrode of the seventh NMOS tube M27, the source electrode of the sixth NMOS tube M26 is connected with the drain electrode of the eighth NMOS tube M28, and the source electrodes of the eighth NMOS tube M19 and the tenth NMOS tube M20 are grounded; the drains of the twelfth PMOS tube M21 and the fourteenth PMOS tube M23 are respectively connected with the drains of the NMOS tubes of the NMOS differential pair, and the sources of the fifth NMOS tube M25 and the sixth NMOS tube M26 are connected with the drains of the PMOS tubes of the PMOS differential pair. The ninth NMOS transistor M19 and the tenth NMOS transistor M20 provide a bias for the first bias voltage providing circuit, the twelfth PMOS transistor M21, the thirteenth PMOS transistor M22, the fourteenth PMOS transistor M23 and the fifteenth PMOS transistor M24 form a load current source of the gain stage, and the self-bias cascode current mirror provides a bias for the load current source.
Still further preferably, the self-bias cascode current mirror is connected with a second bias voltage supply circuit, where the second bias voltage supply circuit includes an eleventh NMOS transistor M3, a gate of the eleventh NMOS transistor M3 is connected to gates of the ninth NMOS transistor M19 and the tenth NMOS transistor M20, a drain of the eleventh NMOS transistor M3 is connected to a drain of the eighth PMOS transistor M2, and a source of the eleventh NMOS transistor M3 is grounded.
Still further preferably, the number of the miller compensation is 2, and the miller compensation includes a first miller compensation capacitor C1, a first compensation resistor R1, a second miller compensation capacitor C2, and a second compensation resistor R2, where the first miller compensation capacitor C1 is connected in series with the first compensation resistor R1, the second miller compensation capacitor C2 is connected in series with the second compensation resistor R2, the first compensation resistor R1 is connected to the power supply voltage VDD, the second compensation resistor R2 is connected to the drain electrode of the fifteenth PMOS transistor M24, and the first miller compensation capacitor C1 and the second miller compensation capacitor C2 are connected to the drains of the first PMOS transistor M29 and the first NMOS transistor M30.
When the common mode input level V CM When the input stage is close to the ground, only the PMOS differential pair works, and the equivalent transconductance of the input stage is
While when the common mode input level V CM Close to the power supplyWhen the voltage VDD is applied, only the NMOS differential pair works, and the equivalent transconductance of the input stage is that
While when the common mode input level V CM When the input stage is in the middle voltage, the PMOS differential pair and the NMOS differential pair work simultaneously, and the equivalent transconductance of the input stage is that
Wherein C is ox Is the gate oxide capacitance per unit area;the width-to-length ratio of the transistors M5, M6, M12 and M14; mu (mu) n 、μ p Mobility of electrons and holes, respectively; i n 、I p The currents when only the NMOS and PMOS differential pairs work independently; and I n ' and I p ' is the current when the NMOS and PMOS differential pairs are operating simultaneously.
Because of mu n Above mu p Thus, the current mirror replica current is designed to be a certain proportion (xI 8 ＝I 9 ) (x is a scaling factor) such thatA constant transconductance over the full operating range is obtained as shown in fig. 5. Wherein I is p ＝I ref ，I n ＝xI p ，I′ n ＝x(I ref -I p )。
In the claims, the word "comprising" does not exclude the presence of elements not listed in a claim. The use of the words first, second, third, etc. do not denote any order, and the words may be interpreted as names.
The technical means disclosed by the scheme of the invention is not limited to the technical means disclosed by the embodiment, and also comprises the technical scheme formed by any combination of the technical features. It should be noted that modifications and adaptations to the invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.
Claims (5)
1. A constant transconductance full-swing operational amplifier, characterized by: the rail-to-rail input stage comprises a rail-to-rail input stage, a gain stage and an output stage which are sequentially connected, wherein the rail-to-rail input stage comprises a complementary PMOS differential pair, an NMOS differential pair, a tail current source of the PMOS differential pair and a load circuit of the NMOS differential pair, the PMOS differential pair is realized by adopting two PMOS tubes connected with common sources, the grid lead of one PMOS tube is used as a non-inverting input end of an operational amplifier, the grid lead of the other PMOS tube is used as an inverting input end of the operational amplifier, the grid lead of one NMOS tube is used as a non-inverting input end of the operational amplifier, the grid lead of the other NMOS tube is used as an inverting input end of the operational amplifier, the tail current source of the PMOS differential pair is connected with the source of the NMOS tube of the NMOS differential pair and the ground, the tail current source of the NMOS differential pair is connected with the drain of the NMOS differential pair through a proportional current mirror, and the load circuit of the NMOS differential pair is connected with the drain of the NMOS differential pair and the power supply voltage VDD; the gain stage comprises a self-bias cascode current mirror, the drain electrode of an NMOS tube of the NMOS differential pair is connected with the self-bias cascode current mirror, the self-bias cascode current mirror is connected with a power supply voltage VDD, the output stage comprises a first PMOS tube, a first NMOS tube and a Miller compensation, the common source electrode of the first PMOS tube is connected with a bias voltage Vb, the gate electrode of the first NMOS tube is connected with the output of the gain stage, the Miller compensation is realized by connecting a Miller compensation capacitor and a compensation resistor in series, the two compensation resistors are respectively connected with the two ends of the self-bias cascode current mirror, the Miller compensation capacitor is connected with the drain electrodes of the first PMOS tube and the first NMOS tube, the drain electrodes of the first PMOS tube and the first NMOS tube are led out to serve as the output end of the operational amplifier, the source electrode of the first PMOS tube is connected with the power supply voltage VDD, and the source electrode of the first NMOS tube is grounded;
the tail current source of the PMOS differential pair adopts a second PMOS tube, the tail current source of the NMOS differential pair adopts a second NMOS tube, a current extraction and replication circuit is arranged between the PMOS differential pair and the tail current source of the NMOS differential pair, the current extraction and replication circuit comprises a third PMOS tube, a regulating resistor and a current mirror formed by the third NMOS tube and a fourth NMOS tube, the source electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube, the drain electrode of the third PMOS tube is connected with one end of the regulating resistor, the other end of the regulating resistor is connected with the drain electrode and the grid electrode of the third NMOS tube, the source electrode of the fourth NMOS tube is grounded, the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube, the drain electrode of the second PMOS tube is connected with the source electrode of the PMOS differential pair, the source electrode of the second PMOS tube is connected with the power supply voltage, the grid electrode of the second PMOS tube is connected with the bias voltage Vb, the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is connected with the source electrode of the NMOS differential pair;
the gain stage further comprises a self-bias common-source common-gate current source, the self-bias common-gate current source comprises a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a ninth NMOS tube, a tenth NMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube and a fifteenth PMOS tube, the self-bias common-source common-gate current source comprises a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, the ninth PMOS tube, the tenth PMOS tube, the twelfth PMOS tube and the thirteenth PMOS tube, the source electrode of the ninth PMOS tube is connected with a power supply voltage VDD, the drain electrode of the ninth PMOS tube, the twelfth PMOS tube and the gate electrode of the fourteenth PMOS tube are connected with a bias voltage Vb, the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube, the drain electrode of the tenth PMOS tube is connected with the source electrode of the eleventh PMOS tube, the drain electrode of the thirteenth PMOS tube is connected with the drain electrode of the thirteenth PMOS tube, the drain electrode of the thirteenth PMOS tube is connected with the NMOS of the thirteenth PMOS tube, the drain electrode of the thirteenth PMOS tube is connected with the drain electrode of the eighth PMOS tube, the drain electrode of the eighth PMOS tube is connected with the eighth NMOS tube, the drain electrode of the eighth PMOS tube is connected with the drain electrode of the eighth PMOS tube, the eighth PMOS tube is connected with the drain electrode of the eighth PMOS tube; the drain electrodes of the twelfth PMOS tube and the fourteenth PMOS tube are respectively connected with the drain electrodes of the NMOS tubes of the NMOS differential pair, and the source electrodes of the fifth NMOS tube and the sixth NMOS tube are connected with the drain electrodes of the PMOS tubes of the PMOS differential pair.
2. The constant transconductance full-swing operational amplifier of claim 1, wherein a fifth PMOS transistor and a sixth PMOS transistor are used as loads of the NMOS differential pair, a fourth PMOS transistor provides bias for the fifth PMOS transistor and the sixth PMOS transistor, sources of the fourth to sixth PMOS transistors are connected with a power supply voltage VDD, gates of the fourth PMOS transistor are connected with gates of the fifth PMOS transistor, gates of the fifth PMOS transistor are connected with gates of the sixth PMOS transistor, gates of the fourth PMOS transistor are connected with drains of the fourth NMOS transistor, and drains of the fifth PMOS transistor and the sixth PMOS transistor are connected with drains of the NMOS differential pair.
3. The constant transconductance full-swing operational amplifier of claim 2, wherein a gate of the third PMOS tube is connected with a first bias voltage supply circuit, the first bias voltage supply circuit includes a seventh PMOS tube and an eighth PMOS tube, a source of the seventh PMOS tube is connected with the power supply voltage VDD, a gate of the seventh PMOS tube is connected with a gate of the eighth PMOS tube, a drain of the seventh PMOS tube is connected with a source of the eighth PMOS tube, and a gate of the eighth PMOS tube is connected with a gate of the third PMOS tube.
4. The constant transconductance full-swing operational amplifier of claim 3, wherein the self-bias cascode current source is connected with a second bias voltage supply circuit, the second bias voltage supply circuit comprises an eleventh NMOS transistor, the gate of the eleventh NMOS transistor is connected to the gates of the ninth NMOS transistor and the tenth NMOS transistor, the drain of the eleventh NMOS transistor is connected to the drain of the eighth PMOS transistor, and the source of the eleventh NMOS transistor is grounded.
5. The constant transconductance full-swing operational amplifier of claim 4, wherein the number of miller compensation is 2, and the constant transconductance full-swing operational amplifier comprises a first miller compensation capacitor, a first compensation resistor, a second miller compensation capacitor and a second compensation resistor, wherein the first miller compensation capacitor is connected in series with the first compensation resistor, the second miller compensation capacitor is connected in series with the second compensation resistor, the first compensation resistor is connected with the power supply voltage VDD, the second compensation resistor is connected with the drain electrode of the fifteenth PMOS transistor, and the first miller compensation capacitor and the second miller compensation capacitor are connected with the drains of the first PMOS transistor and the first NMOS transistor.
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