CN110263468B - On-chip CMOS capacitor and chip - Google Patents
On-chip CMOS capacitor and chip Download PDFInfo
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- CN110263468B CN110263468B CN201910561793.7A CN201910561793A CN110263468B CN 110263468 B CN110263468 B CN 110263468B CN 201910561793 A CN201910561793 A CN 201910561793A CN 110263468 B CN110263468 B CN 110263468B
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Abstract
The application discloses an on-chip CMOS capacitor and a chip, which comprise a main module, a slave module and an equivalent MOS (metal oxide semiconductor) transistor, wherein the main module comprises a main MOS transistor and a main resistor unit which are connected in series between a preset power supply and a grounding end, and the slave module comprises a slave MOS transistor and a matching MOS transistor which are connected in series between the preset power supply and the grounding end; the master MOS tube is connected with the slave MOS tube to form a current mirror structure; the source electrode and the grid electrode of the matched MOS tube are respectively connected with the source electrode and the grid electrode of the equivalent MOS tube in sequence; the grid electrode of the equivalent MOS tube is used as a first polar plate of the equivalent capacitor, and the source electrode is connected with the drain electrode to be used as a second polar plate. Because the master MOS tube and the slave MOS tube form a current mirror structure in the application, when the current passing through the master module is constant, the grid-source voltage of the matched MOS tube is constant, the grid-source voltage of the equivalent MOS tube is ensured to be constant, the capacitance value of the equivalent capacitor is stable, and the negative influence on an external application circuit is avoided.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to an on-chip CMOS capacitor and a chip.
Background
In a CMOS integrated circuit process, in order to reduce the cost, a MOS transistor is usually directly selected as a capacitor. As shown in fig. 1, the source and drain of the NMOS transistor are directly grounded to form the second plate of the capacitor, and the gate of the NMOS transistor is used as a signal input/output to form the first plate of the capacitor. When the size of the capacitor is Cm, cm satisfies: cm = Cgs + Cgd + Cgb, where Cgs represents the gate-to-source capacitance, cgd represents the gate-to-drain capacitance, and Cgb represents the gate-to-substrate capacitance.
In the application of an integrated circuit, the MOS capacitor has the advantages of higher capacitance value per unit area, lower cost, no need of additional photoetching mask plate, and the like. However, the capacitance value of the MOS capacitor is greatly affected by the gate-source voltage Vgs thereof. When Vgs is larger than or equal to Vth (Vth is the threshold voltage of the NMOS tube), a channel is formed between the drain electrode and the source electrode of the NMOS tube, the gate oxide capacitance Cgb = W L Cox, W and L are the width and the length of the gate respectively, and Cox is the capacitance per unit area of the gate oxide. When Vgs < Vth, no channel is formed between the drain and the source of the NMOS transistor, and the gate-oxide capacitance Cgb is connected in series with the substrate depletion region capacitance (a smaller capacitance, the specific value is determined by the process characteristics), and the value is smaller than W × L × Cox. Therefore, when the magnitude of the input signal Vin of the capacitor fluctuates above and below Vth, the capacitance of the MOS capacitor shown in fig. 1 fluctuates to a large extent, and the fluctuation of the capacitance of the MOS capacitor has a large negative effect on the linearity of the circuit in which the MOS capacitor is located, thereby affecting the overall performance of the circuit.
Therefore, how to provide a solution to the above technical problems is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides an on-chip CMOS capacitor with stable capacitance without affecting the linearity of the application circuit, and a chip. The specific scheme is as follows:
an on-chip CMOS capacitor comprises a main module, a slave module and an equivalent MOS transistor, wherein the main module comprises a main MOS transistor and a main resistor unit which are connected in series between a preset power supply and a grounding terminal, and the slave module comprises a slave MOS transistor and a matching MOS transistor which are connected in series between the preset power supply and the grounding terminal;
the master MOS tube is connected with the slave MOS tube to form a current mirror structure;
the source electrode and the grid electrode of the matching MOS tube are respectively connected with the source electrode and the grid electrode of the equivalent MOS tube in sequence;
and the grid electrode of the equivalent MOS tube is used as a first polar plate of the equivalent capacitor, and the source electrode and the drain electrode are connected and used as a second polar plate of the equivalent capacitor.
Preferably, the gate and the drain of the master MOS transistor are connected to the gate of the slave MOS transistor to form a current mirror structure.
Preferably, the equivalent MOS transistor and the matching MOS transistor are both PMOS transistors, and the master MOS transistor and the slave MOS transistor are both NMOS transistors;
the first end and the second end of the main resistance unit are respectively connected with the preset power supply and the drain electrode of the main MOS tube in sequence, and the source electrode of the main MOS tube is connected with the grounding terminal;
the preset power supply is connected with the source electrode of the matched MOS tube, and the drain electrode and the source electrode of the slave MOS tube are respectively connected with the drain electrode of the matched MOS tube and the grounding end in sequence.
Preferably, the main module further includes: and the source electrode is connected with the preset power supply, the grid electrode and the drain electrode are connected with the first end of the main resistance unit, and the auxiliary MOS tube is a PMOS tube.
Preferably, the equivalent MOS transistor and the matching MOS transistor are both NMOS transistors, and the master MOS transistor and the slave MOS transistor are both PMOS transistors;
the source electrode and the drain electrode of the main MOS tube are respectively connected with the preset power supply and the first end of the main resistance unit in sequence, and the second end of the main resistance unit is connected with the grounding end;
and the source electrode and the drain electrode of the slave MOS tube are respectively connected with the preset power supply and the drain electrode of the matched MOS tube in sequence, and the source electrode of the matched MOS tube is connected with the grounding end.
Preferably, the main module further includes: and the source electrode is connected with the grounding end, the grid electrode and the drain electrode are both connected with the second end of the main resistance unit, and the auxiliary MOS tube is an NMOS tube.
Preferably, the on-chip CMOS capacitor includes a first equivalent MOS transistor and a second equivalent MOS transistor, and the main module specifically includes: the first main MOS tube, the main resistance unit and the second main MOS tube are sequentially connected in series between the preset power supply and the grounding terminal;
correspondingly, the slave module specifically comprises:
the first slave MOS tube and the first matching MOS tube are sequentially connected in series between the preset power supply and the grounding end;
the second matching MOS tube and the second slave MOS tube are sequentially connected in series between the preset power supply and the grounding end;
the grid electrode and the drain electrode of the first master MOS tube are connected with the grid electrode of the first slave MOS tube;
the source electrode and the grid electrode of the first matching MOS tube are respectively connected with the source electrode and the grid electrode of the first equivalent MOS tube in sequence;
the grid and the drain of the second master MOS tube are connected with the grid of the second slave MOS tube;
the source electrode and the grid electrode of the second matching MOS tube are respectively connected with the source electrode and the grid electrode of the second equivalent MOS tube in sequence;
the grid electrode of the first equivalent MOS tube and the grid electrode of the second equivalent MOS tube are connected and then serve as a first polar plate of the equivalent capacitor;
and the source electrode and the drain electrode of the first equivalent MOS tube and the source electrode and the grid electrode of the second equivalent MOS tube are connected and then are used as the second polar plate of the equivalent capacitor.
Preferably, the first master MOS transistor, the first slave MOS transistor, the second matching MOS transistor, and the second equivalent MOS transistor are PMOS transistors;
the second master MOS tube, the second slave MOS tube, the first matching MOS tube and the first equivalent MOS tube are NMOS tubes.
Preferably, the on-chip CMOS capacitor further includes: the first end of the matching MOS tube is connected with the source electrode of the matching MOS tube, and the second end of the matching MOS tube is connected with the corresponding preset unit or the corresponding slave resistance unit of the grounding terminal.
Correspondingly, the invention also discloses a chip comprising the on-chip CMOS capacitor as described in any one of the above.
The application discloses an on-chip CMOS capacitor, which comprises a main module, a slave module and an equivalent MOS (metal oxide semiconductor) transistor, wherein the main module comprises a main MOS transistor and a main resistor unit which are connected in series between a preset power supply and a grounding end, and the slave module comprises a slave MOS transistor and a matching MOS transistor which are connected in series between the preset power supply and the grounding end; the master MOS tube is connected with the slave MOS tube to form a current mirror structure; the source electrode and the grid electrode of the matching MOS tube are respectively connected with the source electrode and the grid electrode of the equivalent MOS tube in sequence; and the grid electrode of the equivalent MOS tube is used as a first polar plate of the equivalent capacitor, and the source electrode and the drain electrode are connected and used as a second polar plate of the equivalent capacitor. Because the main MOS tube and the auxiliary MOS tube form a current mirror structure in the application, when the current passing through the main module is constant, the grid-source voltage of the auxiliary MOS tube is constant, so that the grid-source voltage of the equivalent MOS tube is constant, the capacitance value of the equivalent capacitor in the equivalent MOS tube is stable, the capacitance value of the equivalent capacitor cannot fluctuate with the input signal of the first polar plate, and the negative influence on an external application circuit is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic circuit diagram of a prior art MOS transistor used as a capacitor;
FIG. 2 is a diagram illustrating a structure distribution of an on-chip CMOS capacitor according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a structure distribution of an on-chip CMOS capacitor according to an embodiment of the present invention;
fig. 4 is a structural distribution diagram of an on-chip CMOS capacitor according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the prior art, the capacitance value of the MOS capacitor fluctuates to a greater degree along with fluctuation of an input signal Vin up and down Vth, so that the linearity of a circuit in which the MOS capacitor is arranged is greatly influenced; the MOS capacitor capacitance stabilizing circuit has the advantages that through the specific circuit, the stability of the capacitance value of the MOS capacitor is guaranteed, and therefore the negative influence on an external application circuit is avoided.
The embodiment of the invention discloses an on-chip CMOS capacitor, which comprises a main module 1, a slave module 2 and an equivalent MOS tube Mc, wherein the main module 1 comprises a main MOS tube M1 and a main resistor unit R1 which are connected in series between a preset power supply VDD and a ground end GND, and the slave module 2 comprises a slave MOS tube M2 and a matching MOS tube M3 which are connected in series between the preset power supply VDD and the ground end GND;
the master MOS tube M1 is connected with the slave MOS tube M2 to form a current mirror structure;
the source electrode and the grid electrode of the matched MOS tube M3 are respectively connected with the source electrode and the grid electrode of the equivalent MOS tube Mc in sequence;
the grid electrode of the equivalent MOS tube Mc is used as a first polar plate of the equivalent capacitance, and the source electrode is connected with the drain electrode to be used as a second polar plate of the equivalent capacitance.
Specifically, the gate and the drain of the master MOS transistor M1 are connected to the gate of the slave MOS transistor M2 to form a current mirror structure. Theoretically, the preset power supply VDD is stable, and the stability of the capacitance value of the equivalent MOS tube Mc cannot be influenced; if the preset power supply VDD may fluctuate, in order to avoid a stable capacitance value of the equivalent MOS transistor Mc, the slave module 2 may further include a slave resistance unit R2 having a first end connected to the source of the matching MOS transistor and a second end connected to the corresponding preset unit or the ground end, so as to reduce an influence of fluctuation of the preset power supply VDD on the equivalent MOS transistor Mc.
It is understood that the main resistance unit R1 in this embodiment includes one or more resistors, the plurality of resistors are connected in series, parallel or series-parallel, and the whole main resistance unit R1 constitutes a resistance equivalent to R 1 The equivalent resistor is connected into an on-chip CMOS capacitor, and the resistance value formed by the resistor unit R2 is equivalent to R 2 The equivalent resistance of (c).
It can be understood that, in the present embodiment, the series connection of the MOS transistors refers to connecting the source and the gate of the MOS transistor to the current path from the predetermined power supply VDD to the ground GND, and when the MOS transistor is turned on, the current can flow from the predetermined power supply VDD to the ground GND through the MOS transistor.
It can be understood that in the present embodiment, the main MOS transistor M1 and the main resistor unit R1 in the main module 1 constitute a bias current generating unit, and generate the bias current I required by the on-chip CMOS capacitor 1 The size of the composite material satisfies the following conditions:
V sg1 is the gate-source voltage of the main MOS transistor M1.
Further, the MOS transistor M3 is matched to work in a saturation region, so that V is required to be satisfied sd3 -V sg3 ≥V th3 In which V is sd3 To match the actual voltage difference between the source and drain of MOS transistor M3, V sg3 To match the actual voltage difference between the source and the gate of MOS transistor M3, V th3 To match the threshold voltage of the MOS transistor M3.
Specifically, in this embodiment, the connection relationship between the master MOS transistor M1 and the slave MOS transistor M2 actually forms a current mirror structure, and the master MOS transistor M1 and the slave MOS transistor M2 should have the same size when designed; through the main MOS tube M1 and the main resistor in the main module 1Current I of cell R1 1 Current I passing through slave MOS transistor M2, slave resistor unit R2, and matching MOS transistor M3 2 Are equal, i.e. I 1 ＝I 2 (ii) a Since the MOS transistor M3 is operated in the saturation region, the current I is generated 2 Also satisfies:
wherein μ is the mobility of the matching MOS transistor M3, so that it can be derived:
from this relationship, it can be seen that when the current I is 1 When not changed, the grid source voltage V of the MOS transistor M3 is matched sg3 Is always constantly greater than its threshold voltage V th3 And because the source and the grid of the matching MOS tube M3 are respectively connected with the source and the grid of the equivalent MOS tube Mc in sequence, the grid-source voltage V of the equivalent MOS tube Mc sgc And the voltage is stably and invariably larger than the threshold voltage, so that the equivalent MOS tube Mc works in an open state, and the capacitance value of the equivalent capacitor is ensured to be invariable.
Specifically, in order to make the equivalent MOS transistor reach the voltage condition, the parameters of the internal circuit elements of the on-chip CMOS capacitor need to be set accordingly, and the equivalent resistance value R of the main resistance unit R1 is generally selected 1 The condition is realized, that is, the main resistance unit R1 is specifically a resistance unit which makes the matching MOS transistor M3 operate in a saturation state, and besides, the condition can be completed by adjusting parameters of other elements.
Specifically, according to the connection relationship of the elements of the on-chip CMOS capacitor in this embodiment, it may be determined that the master MOS transistor M1 and the slave MOS transistor M2 are the same type of MOS transistor, and the matching MOS transistor M3 and the equivalent MOS transistor Mc are another type of MOS transistor with the type opposite to that of the master MOS transistor M1, where the types of MOS transistors mentioned herein include an NMOS transistor and a PMOS transistor.
It is understood that all devices in this embodiment are compatible with CMOS process, and have low production cost.
Furthermore, the sequence of the elements connected in series to the series circuit between the preset power supply and the ground terminal needs to be selected according to the type of the MOS transistor involved, the sequence of the main MOS transistor M1 and the main resistor unit R1 needs to be considered in the main module 1 to achieve the effect of generating the bias current, and the sequence of the auxiliary resistor unit R2, the auxiliary MOS transistor M2, and the matching MOS transistor M3 needs to be considered in the auxiliary module 2 to ensure the isolation between the second plate of the equivalent MOS transistor Mc and the preset power supply VDD and the ground terminal GND, so that even if the voltage fluctuation occurs in the preset power supply VDD or the ground terminal GND, the capacitance of the equivalent MOS transistor Mc is not affected.
It can be understood that, in the present embodiment, the gate of the equivalent MOS transistor Mc serves as the first plate of the equivalent capacitor, and the source is connected to the drain to serve as the second plate of the equivalent capacitor, because the gate-source voltage of the equivalent MOS transistor Mc is not changed, the equivalent MOS transistor Mc keeps the on state, the capacitance value between the first plate and the second plate does not change, and even if the voltage of the input signal Vin of the first plate changes, the equivalent MOS transistor Mc serving as the equivalent capacitor does not fluctuate.
The embodiment of the invention discloses an on-chip CMOS capacitor, which comprises a main module, a slave module and an equivalent MOS (metal oxide semiconductor) transistor, wherein the main module comprises a main MOS transistor and a main resistor unit which are connected in series between a preset power supply and a grounding end, and the slave module comprises a slave MOS transistor and a matching MOS transistor which are connected in series between the preset power supply and the grounding end; the master MOS tube is connected with the slave MOS tube to form a current mirror structure; the source electrode and the grid electrode of the matching MOS tube are respectively connected with the source electrode and the grid electrode of the equivalent MOS tube in sequence; and the grid electrode of the equivalent MOS tube is used as a first polar plate of the equivalent capacitor, and the source electrode and the drain electrode are connected and used as a second polar plate of the equivalent capacitor. Because the main MOS tube and the auxiliary MOS tube form a current mirror structure in the application, when the current passing through the main module is constant, the grid-source voltage of the auxiliary MOS tube is constant, so that the grid-source voltage of the equivalent MOS tube is constant, the capacitance value of the equivalent capacitor in the equivalent MOS tube is stable, the capacitance value of the equivalent capacitor cannot fluctuate with the input signal of the first polar plate, and the negative influence on an external application circuit is avoided.
The embodiment of the invention discloses a specific on-chip CMOS capacitor, and compared with the previous embodiment, the technical scheme is further explained and optimized in the embodiment. Specifically, the equivalent MOS transistor Mc and the matching MOS transistor M3 are both PMOS transistors, and the master MOS transistor M1 and the slave MOS transistor M2 are both NMOS transistors;
referring to fig. 2, a first end and a second end of the main resistance unit R1 are respectively connected to a preset power VDD and a drain of the main MOS transistor M1 in sequence, and a source of the main MOS transistor M1 is connected to a ground GND;
the preset power supply VDD is connected with a source electrode of the matching MOS tube M3, and a drain electrode and a source electrode of the slave MOS tube M2 are respectively connected with a drain electrode of the matching MOS tube M3 and a ground end GND in sequence.
If the slave resistance unit R2 is added in this embodiment, the first end and the second end of the slave resistance unit R2 are respectively connected to the preset power VDD and the source of the matching MOS transistor M3 in sequence.
It is understood that the present embodiment determines the sequence of specific circuit elements in the master module 1 and the slave module 2, which is determined by the MOS transistor type. Wherein, cooperation MOS pipe M3 still satisfies the relational expression:
at this time μ = μ p And the mobility of the PMOS tube.
Further, the main module 1 may further include: and the source electrode is connected with a preset power supply VDD, the grid electrode and the drain electrode are both connected with the first end of the main resistance unit R1, and the auxiliary MOS transistor M4 is a PMOS transistor.
It can be understood that after the auxiliary MOS transistor M4 is added to the main module 1, the bias current I 1 Satisfies the following conditions:
wherein V sg4 To assist the gate-source voltage of MOS transistor M4, if for the bias current I 1 The size requirement of the MOS transistor is not changed, and the existence of the auxiliary MOS transistor M4 can remarkably share the original mainVoltage across resistance unit R1, equivalent resistance value R of main resistance unit R1 1 The reduction, and thus the physical size requirement of the main resistor unit R1, allows the size of the on-chip CMOS capacitors to be smaller.
Of course, the type of the auxiliary MOS transistor M4 may be an NMOS transistor, besides a PMOS transistor, and may also be another type of switching transistor to realize the voltage sharing function, and at this time, the connection relationship of each element in the main module 1 needs to be adaptively adjusted.
The embodiment of the invention discloses a specific on-chip CMOS capacitor, and compared with the previous embodiment, the technical scheme is further explained and optimized in the embodiment. Specifically, the equivalent MOS transistor Mc and the matching MOS transistor M3 are both NMOS transistors, and the master MOS transistor M1 and the slave MOS transistor M2 are both PMOS transistors;
referring to fig. 3, a source and a drain of the main MOS transistor M1 are respectively connected to a preset power VDD and a first end of the main resistance unit R1 in sequence, and a second end of the main resistance unit R1 is connected to a ground GND;
the source electrode and the drain electrode of the slave MOS tube M2 are respectively connected with a preset power supply VDD and the drain electrode of the matched MOS tube M3 in sequence, and the source electrode of the matched MOS tube M3 is connected with a ground end GND.
Further, if the slave module 2 further includes the slave resistor unit R2 in this embodiment, the first end and the second end of the slave resistor unit R2 are respectively connected to the source of the matching MOS transistor M3 and the ground GND in sequence.
It is understood that the present embodiment determines the sequence of specific circuit elements in the master module 1 and the slave module 2, which is determined by the MOS transistor type. Wherein, cooperation MOS pipe M3 still satisfies the relational expression:
at this time, mu = mu n The mobility of the NMOS transistor is shown.
Further, the main module 1 may further include: and the source electrode is connected with a grounding end GND, the grid electrode and the drain electrode are both connected with the second end of the main resistance unit R1, and the auxiliary MOS transistor M4 is an NMOS transistor.
It can be understood that after the auxiliary MOS transistor M4 is added to the main module 1, the bias current I 1 Satisfies the following conditions:
wherein V sg4 To assist the gate-source voltage of MOS transistor M4, if for the bias current I 1 The size requirement of the auxiliary MOS tube M4 is not changed, the voltage of the original main resistance unit R1 can be remarkably shared by the auxiliary MOS tube M4, and the equivalent resistance value R of the main resistance unit R1 1 The reduction, and thus the physical size requirement of the main resistor unit R1, allows the size of the on-chip CMOS capacitors to be smaller.
Of course, the type of the auxiliary MOS transistor M4 may be a PMOS transistor, besides an NMOS transistor, or another type of switching transistor to realize the voltage sharing function, and at this time, the connection relationship of each element in the main module 1 needs to be adaptively adjusted.
The embodiment of the invention discloses a specific on-chip CMOS capacitor, and compared with the previous embodiment, the technical scheme is further explained and optimized in the embodiment.
Specifically, referring to fig. 4, the on-chip CMOS capacitor includes a first equivalent MOS transistor Mc1 and a second equivalent MOS transistor Mc2, and the main module 1 specifically includes: the first main MOS tube M11, the main resistor unit R1 and the second main MOS tube M12 are sequentially connected in series between a preset power supply VDD and a ground end GND;
correspondingly, the slave module 2 specifically includes:
the first slave MOS transistor M21 and the first matching MOS transistor M31 are sequentially connected in series between a preset power supply VDD and a ground end GND;
the second matching MOS transistor M32 and the second slave MOS transistor M22 are sequentially connected in series between a preset power supply VDD and a ground end GND;
the grid and the drain of the first master MOS transistor M11 are connected with the grid of the first slave MOS transistor M21;
the source electrode and the grid electrode of the first matching MOS tube M31 are respectively connected with the source electrode and the grid electrode of the first equivalent MOS tube Mc1 in sequence;
the grid and the drain of the second master MOS transistor M12 are connected with the grid of the second slave MOS transistor M22;
the source electrode and the grid electrode of the second matching MOS tube M32 are respectively connected with the source electrode and the grid electrode of the second equivalent MOS tube Mc2 in sequence;
the grid electrode of the first equivalent MOS tube Mc1 and the grid electrode of the second equivalent MOS tube Mc2 are connected and then serve as a first polar plate of the equivalent capacitor;
the source and the drain of the first equivalent MOS transistor Mc1 and the source and the gate of the second equivalent MOS transistor Mc2 are connected to each other and then serve as a second plate of the equivalent capacitor.
Specifically, the first master MOS transistor M11, the first slave MOS transistor M21, the second matching MOS transistor M32, and the second equivalent MOS transistor Mc2 are all PMOS transistors;
the second master MOS transistor M12, the second slave MOS transistor M22, the first matching MOS transistor M31 and the first equivalent MOS transistor Mc1 are all NMOS transistors.
Further, the slave module 2 in this embodiment may further include a slave resistance unit, specifically, a first slave resistance unit R21 and a second slave resistance unit R22, where the first slave resistance unit R21 is connected between the first matching MOS transistor M31 and the ground GND, and the second slave resistance unit R22 is connected between the second matching MOS transistor M32 and the preset power supply VDD.
It can be understood that, in the present embodiment, the series connection of the MOS transistors refers to connecting the source and the gate of the MOS transistor to the current path from the predetermined power supply VDD to the ground GND, and when the MOS transistor is turned on, the current can flow from the predetermined power supply VDD to the ground GND through the MOS transistor, and the specific connection manner can be shown in fig. 4.
It is understood that the present embodiment is a combination of the two embodiments, and the bias current I is generated in the main module 1 1 Satisfies the following conditions:
V sg11 is the gate-source voltage, V, of the first main MOS transistor M11 sg12 Is the gate-source voltage of the second main MOS transistor M12.
The first matching MOS transistor M31 works in a saturation region and satisfies V sd31 -V sg31 ≥V th31 In which V is sd31 Is the actual voltage difference between the source and drain of the first matching MOS transistor M31, V sg31 Is the actual voltage difference between the source and the gate of the first matching MOS transistor M31, V th31 Is the threshold voltage of the first matching MOS transistor M31; similarly, the second matching MOS transistor M32 also works in the saturation region, and needs to satisfy the similar condition as the first matching MOS transistor M31. Conveniently, the first matching MOS transistor M31 and the second matching MOS transistor M32 both reach a saturation region by selecting appropriate parameters for the main resistance unit R1.
It can be understood that the first master MOS transistor M11 and the first slave MOS transistor M21 form a current mirror structure, the second master MOS transistor M12 and the second slave MOS transistor M22 form a current mirror structure, and two MOS transistors in the current mirror structure are selected to have the same size; due to the presence of these two current mirror structures, the bias current I of the main module 1 is enabled 1 With the current I passing through the first slave MOS transistor M21, the first matching MOS transistor M31 and the first slave resistance unit R21 21 And a current I passing through the second slave resistance unit R22, the second matching MOS transistor M32 and the second slave MOS transistor M22 22 And are equal.
Furthermore, since the first matching MOS transistor M31 and the second matching MOS transistor M32 both work in the saturation region, they can respectively obtain:
from these two relationships, it can be seen that when the bias current I is applied 1 When the voltage is not changed, the grid source voltage V of the first matching MOS tube M31 sg31 Is always constantly greater than its threshold voltage V th3` The gate source voltage V of the second matching MOS transistor M32 sg32 Is always constantly greater than the threshold voltage V th32 And according to the circuit connection relationship, the first equivalent MOS tube Mc1 and the second equivalent MOS tube Mc2 work in an open state, so that the capacitance value of the equivalent capacitor is ensured to be unchanged.
In this embodiment, the input signal Vin is simultaneously connected to the gates of the first equivalent MOS transistor Mc1 and the second equivalent MOS transistor Mc2, the equivalent capacitance is actually obtained by connecting the equivalent capacitance of the first equivalent MOS transistor Mc1 and the equivalent capacitance of the second equivalent MOS transistor Mc2 in parallel, that is, the equivalent capacitance value of this embodiment is the sum of the equivalent capacitance values of the first equivalent MOS transistor Mc1 and the second equivalent MOS transistor Mc 2. Because the first equivalent MOS tube Mc1 and the second equivalent MOS tube Mc2 are an NMOS tube and a PMOS tube respectively, the two types of MOS tubes form complementation, and the influence of process deviation on the capacitance value of the on-chip CMOS capacitor is eliminated to a certain extent.
It is understood that all devices in this embodiment are compatible with CMOS process, and have low production cost.
Correspondingly, the embodiment of the invention also discloses a chip comprising the on-chip CMOS capacitor as any one of the above embodiments.
In particular, reference may be made to the description of the above embodiments regarding the contents of the on-chip CMOS capacitor.
It can be understood that the chip in this embodiment integrates the circuit of the on-chip CMOS capacitor of the above embodiment, and thus has the same beneficial effects as the on-chip CMOS capacitor of the above embodiment.
Finally, it should also be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
The on-chip CMOS capacitor and the chip provided by the present invention are described in detail above, and the principle and the implementation of the present invention are explained herein by using specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. An on-chip CMOS capacitor is characterized by comprising a main module, a slave module and an equivalent MOS tube, wherein the main module comprises a main MOS tube and a main resistance unit which are connected in series between a preset power supply and a grounding end, and the slave module comprises a slave MOS tube and a matching MOS tube which are connected in series between the preset power supply and the grounding end;
the master MOS tube is connected with the slave MOS tube to form a current mirror structure;
the source electrode and the grid electrode of the matching MOS tube are respectively connected with the source electrode and the grid electrode of the equivalent MOS tube in sequence;
and the grid electrode of the equivalent MOS tube is used as a first polar plate of the equivalent capacitor, and the source electrode is connected with the drain electrode and is used as a second polar plate of the equivalent capacitor.
2. The on-chip CMOS capacitor as claimed in claim 1, wherein the gate and drain of said master MOS transistor are connected to the gate of said slave MOS transistor to form a current mirror structure.
3. The on-chip CMOS capacitor of claim 2, wherein said equivalent MOS transistor and said matching MOS transistor are both PMOS transistors, and said master MOS transistor and said slave MOS transistor are both NMOS transistors;
the first end and the second end of the main resistance unit are respectively connected with the preset power supply and the drain electrode of the main MOS tube in sequence, and the source electrode of the main MOS tube is connected with the grounding end;
the preset power supply is connected with the source electrode of the matched MOS tube, and the drain electrode and the source electrode of the slave MOS tube are respectively connected with the drain electrode of the matched MOS tube and the grounding end in sequence.
4. The on-chip CMOS capacitor of claim 3, wherein the main module further comprises: and the source electrode is connected with the preset power supply, the grid electrode and the drain electrode are connected with the first end of the main resistance unit, and the auxiliary MOS tube is a PMOS tube.
5. The on-chip CMOS capacitor of claim 2, wherein said equivalent MOS transistor and said matching MOS transistor are both NMOS transistors, and said master MOS transistor and said slave MOS transistor are both PMOS transistors;
the source electrode and the drain electrode of the main MOS tube are respectively connected with the preset power supply and the first end of the main resistance unit in sequence, and the second end of the main resistance unit is connected with the grounding end;
and the source electrode and the drain electrode of the slave MOS tube are respectively connected with the preset power supply and the drain electrode of the matching MOS tube in sequence, and the source electrode of the matching MOS tube is connected with the grounding terminal.
6. The on-chip CMOS capacitor of claim 5, wherein said main module further comprises: and the source electrode is connected with the grounding end, the grid electrode and the drain electrode are both connected with the second end of the main resistance unit, and the auxiliary MOS tube is an NMOS tube.
7. The on-chip CMOS capacitor of claim 2, wherein the on-chip CMOS capacitor comprises a first equivalent MOS transistor and a second equivalent MOS transistor, and the main module specifically comprises: the first main MOS tube, the main resistor unit and the second main MOS tube are sequentially connected in series between the preset power supply and the grounding end;
correspondingly, the slave module specifically includes:
the first slave MOS tube and the first matching MOS tube are sequentially connected in series between the preset power supply and the grounding end;
the second matching MOS tube and the second slave MOS tube are sequentially connected in series between the preset power supply and the grounding end;
the grid electrode and the drain electrode of the first master MOS tube are connected with the grid electrode of the first slave MOS tube;
the source electrode and the grid electrode of the first matching MOS tube are respectively connected with the source electrode and the grid electrode of the first equivalent MOS tube in sequence;
the grid electrode and the drain electrode of the second master MOS tube are connected with the grid electrode of the second slave MOS tube;
the source electrode and the grid electrode of the second matching MOS tube are respectively connected with the source electrode and the grid electrode of the second equivalent MOS tube in sequence;
the grid electrode of the first equivalent MOS tube and the grid electrode of the second equivalent MOS tube are connected and then serve as a first polar plate of the equivalent capacitor;
and the source electrode and the drain electrode of the first equivalent MOS tube and the source electrode and the grid electrode of the second equivalent MOS tube are connected and then are used as second polar plates of the equivalent capacitors.
8. The on-chip CMOS capacitor of claim 7,
the first master MOS tube, the first slave MOS tube, the second matching MOS tube and the second equivalent MOS tube are PMOS tubes;
the second master MOS tube, the second slave MOS tube, the first matching MOS tube and the first equivalent MOS tube are NMOS tubes.
9. The on-chip CMOS capacitor of any one of claims 1-8, further comprising:
the first end of the matching MOS tube is connected with the source electrode of the matching MOS tube, and the second end of the matching MOS tube is connected with the corresponding preset unit or the slave resistance unit of the grounding end.
10. A chip comprising an on-chip CMOS capacitor according to any one of claims 1 to 9.
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