WO2021088628A1 - Gpio multiplexing circuit based on high-voltage input and esd protection - Google Patents

Gpio multiplexing circuit based on high-voltage input and esd protection Download PDF

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WO2021088628A1
WO2021088628A1 PCT/CN2020/121865 CN2020121865W WO2021088628A1 WO 2021088628 A1 WO2021088628 A1 WO 2021088628A1 CN 2020121865 W CN2020121865 W CN 2020121865W WO 2021088628 A1 WO2021088628 A1 WO 2021088628A1
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mos tube
port
drain
mos
gate
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PCT/CN2020/121865
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French (fr)
Chinese (zh)
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韩红娟
江猛
范佳敏
雷红军
杭晓伟
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苏州华芯微电子股份有限公司
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Publication of WO2021088628A1 publication Critical patent/WO2021088628A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Definitions

  • the invention belongs to the technical field of integrated circuits, and specifically relates to a GPIO multiplexing circuit based on high voltage input and ESD protection.
  • GPIO functions are becoming more and more complex.
  • the pin is a high-voltage input pin with switch control, the ordinary IO port structure is not suitable for this, and ordinary ESD protection is not suitable for this pin.
  • the purpose of the present invention is to provide a GPIO multiplexing circuit based on high-voltage input and ESD protection, so as to realize the multiplexing of the high-voltage input pin with switch control and the GPIO port, and has reliable ESD protection.
  • the GPIO multiplexing circuit includes a high voltage input module connected to an IO port, an IO port function module, and an ESD protection module.
  • the high voltage input module is a switch controlled
  • the high-voltage transmission structure includes a number of MOS tubes and resistors
  • the IO port function module includes a number of MOS tubes and resistors
  • the ESD protection module includes a number of MOS tubes and resistors.
  • the high-voltage input module includes MOS transistors M1 to M11 and resistors R1 to R3, wherein:
  • MOS tube M1 and MOS tube M2 are connected to the IO port, MOS tube M3 is connected to MOS tube M1, MOS tube M4 is connected to MOS tube M2, MOS tube M1 is connected to MOS tube M4, MOS tube M2 is connected to MOS tube M3, MOS Tube M5 and MOS tube M6 are respectively connected to MOS tube M3 and MOS tube M4, MOS tube M7 and MOS tube M8 are respectively connected to enable port VEN and MOS tube M3, and MOS tube M5 and MOS tube M7 are respectively connected to power supply voltage VCC , The MOS tube M3, the MOS tube M4, the MOS tube M6, and the MOS tube M8 are respectively connected to the common voltage VSS;
  • the MOS tube M9 is connected between the IO port and the common voltage VSS;
  • the MOS tube M10 is connected between the IO port and the output port VOUT;
  • the MOS tube M11 is connected between the enable port VEN and the output port VOUT, and the MOS tube M11 is connected with the common voltage VSS;
  • the resistor R1 is connected between the MOS tube M1, the MOS tube M2 and the IO port;
  • the resistor R2 is connected between the MOS tube M10 and the MOS tube M2;
  • the resistor R3 is connected between the MOS tube M11 and the output port VOUT.
  • the MOS tube M1, MOS tube M2, MOS tube M5, MOS tube M7, and MOS tube M10 are PMOS tubes, and MOS tube M3, MOS tube M4, MOS tube M6, MOS tube M8, MOS tube M9,
  • the MOS tube M11 is an NMOS tube.
  • the source of the MOS tube M1 is connected to the resistor R1, the drain is connected to the drain of the MOS tube M3 and the gate of the MOS tube M2, and the gate is connected to the drain of the MOS tube M2 and the drain of the MOS tube M4;
  • the source of the MOS tube M2 is connected to the resistor R1, the drain is connected to the gate of the MOS tube M1 and the drain of the MOS tube M4, and the gate is connected to the MOS tube M1, the drain of the MOS tube M3 and the resistor R2;
  • the gate of the MOS tube M3 is connected to the gate of the MOS tube M5, the gate of the MOS tube M6, the drain of the MOS tube M7, and the MOS tube M8.
  • the source is connected to the common voltage VSS, and the drain is connected to the drain of the MOS tube M1 and the MOS tube.
  • the gate of M2 is connected;
  • the gate of the MOS tube M4 is connected to the drains of the MOS tube M5 and the MOS tube M6, the source is connected to the common voltage VSS, and the drain is connected to the drain of the MOS tube M2 and the gate of the MOS tube M1;
  • the source of the MOS tube M5 is connected to the power supply voltage VCC
  • the drain of the MOS tube M5 is connected to the drain of the MOS tube M6 and the gate of the MOS tube M4
  • the source of the MOS tube M6 is connected to the common voltage VSS.
  • the gate and the gate of the MOS tube M6 are connected with the gate of the MOS tube M3 and the drains of the MOS tube M7 and the MOS tube M8;
  • the source of the MOS tube M7 is connected to the power supply voltage VCC
  • the drain of the MOS tube M7 is connected to the drain of the MOS tube M8
  • the source of the MOS tube M8 is connected to the common voltage VSS
  • the gate of the MOS tube M7 is connected to the MOS tube M8.
  • the gates are respectively connected to the enable port VEN;
  • the drain of the MOS tube M9 is connected to the IO port, the source is connected to the common voltage VSS, and the gate is connected to the source;
  • the source of the MOS tube M10 is connected to the IO port, the drain is connected to the output port VOUT, the gate is connected to the resistor R2, and the substrate is connected to the IO port;
  • the gate of the MOS tube M11 is connected to the enable port VEN, the drain is connected to the resistor R3 and then connected to the output port VOUT, and the source is connected to the common voltage VSS;
  • the resistor R1 is connected between the source of the MOS tube M1, the source of the MOS tube M2 and the IO port;
  • the resistor R2 is connected between the gate of the MOS tube M10 and the gate of the MOS tube M2;
  • the resistor R3 is connected between the drain of the MOS transistor M11 and the output port VOUT.
  • the enable port VEN input is active low, the MOS tube M3 is turned on, the MOS tube M2 is turned on, the MOS tube M1 is turned off, the MOS tube M10 is turned on, and the voltage at the resistor R2 is Low, the voltage at the resistor R1 terminal is consistent with the IO port, and the output port VOUT outputs a voltage close to the IO port.
  • the IO port function module includes MOS transistors M12, M13 and resistor R4, where:
  • the source of the MOS tube M12 is connected to the power supply voltage VCC, the gate is connected to the input port IN1, and the drain is connected to the resistor R4;
  • the drain of the MOS tube M13 is connected to the resistor R4, the source is connected to the common voltage VSS, and the gate is connected to the input port IN2;
  • the resistor R4 is located between the drain of the MOS transistor M12 and the drain of the MOS transistor M13;
  • the drain of the MOS tube M12 is connected to the input port IO_IN, and the drain of the MOS tube M13 is connected to the IO port.
  • the MOS tube M12 is a PMOS tube
  • the MOS tube M13 is an NMOS tube.
  • the IO port when the high voltage transmission is turned off, the IO port is used as a normal input and output.
  • the IO port When the input port IN1 is low and the input port IN2 is low, the IO port outputs a high level.
  • the input port IN1 When the input port IN1 is high level and the input port IN2 is high level, the IO port outputs low level.
  • the input port IN1 is high level and the input port IN2 is low level, the IO port outputs a high impedance state, and the input port IO_IN passes IO port input level.
  • the ESD protection module includes MOS transistors M14 and M15 and resistors R5 to R7, wherein:
  • the source of the MOS tube M14 is connected to the power supply voltage VCC, the gate is connected to the source, and the drain is connected to the resistor R5;
  • the drain of the MOS tube M15 is connected to the resistor R5, the source is connected to the common voltage VSS, and the gate is connected to the source;
  • the resistor R5 is located between the drain of the MOS transistor M14 and the drain of the MOS transistor M15;
  • the resistor R6 is located between the gate and the source of the MOS tube M14;
  • the resistor R7 is located between the gate and the source of the MOS tube M15;
  • the MOS tube M14 is a PMOS tube
  • the MOS tube M15 is an NMOS tube.
  • the MOS tube M14 is a PMOS tube
  • the MOS tube M15 is an NMOS tube.
  • the present invention has the following advantages:
  • the GPIO multiplexing circuit of the present invention can realize the multiplexing of the high-voltage input pin with switch control and the GPIO port through ordinary MOS tubes and resistors under the ordinary CMOS process and no special devices, and has reliable ESD protection.
  • Figure 1 is a schematic diagram of a module of the GPIO multiplexing circuit in the present invention
  • Fig. 2 is a schematic circuit diagram of a high-voltage input module in a specific embodiment of the present invention
  • Fig. 3 is a schematic circuit diagram of an IO port function module in a specific embodiment of the present invention.
  • Fig. 4 is a schematic circuit diagram of an ESD protection module in a specific embodiment of the present invention.
  • the present invention discloses a GPIO multiplexing circuit based on high voltage input and ESD protection.
  • the GPIO multiplexing circuit includes a high voltage input module connected to an IO port, an IO port function module, and an ESD protection module.
  • the module is a high-voltage transmission structure with switch control, which includes a number of MOS tubes and resistors
  • the IO port function module includes a number of MOS tubes and resistors
  • the ESD protection module includes a number of MOS tubes and resistors.
  • the high-voltage input module in this embodiment includes MOS transistors M1 to M11 and resistors R1 to R3.
  • MOS transistors M1, MOS transistors M2, MOS transistors M5, MOS transistors M7, and MOS transistors M10 are PMOS transistors.
  • MOS tube M3, MOS tube M4, MOS tube M6, MOS tube M8, MOS tube M9, MOS tube M11 are NMOS tubes.
  • Tube M3 is connected, MOS tube M5 and MOS tube M6 are connected to MOS tube M3 and MOS tube M4, MOS tube M7 and MOS tube M8 are respectively connected to enable port VEN and MOS tube M3, and MOS tube M5 and MOS tube M7 are respectively connected to The power supply voltage VCC is connected, and the MOS tube M3, the MOS tube M4, the MOS tube M6, and the MOS tube M8 are respectively connected to the common voltage VSS;
  • the MOS tube M9 is connected between the IO port and the common voltage VSS;
  • the MOS tube M10 is connected between the IO port and the output port VOUT;
  • the MOS tube M11 is connected between the enable port VEN and the output port VOUT, and the MOS tube M11 is connected with the common voltage VSS;
  • the resistor R3 is connected between the MOS tube M11 and the output port VOUT.
  • the source of the MOS tube M1 is connected to the resistor R1, the drain is connected to the drain of the MOS tube M3 and the gate of the MOS tube M2, and the gate is connected to the drain of the MOS tube M2 and the drain of the MOS tube M4;
  • the source of the MOS tube M2 is connected to the resistor R1, the drain is connected to the gate of the MOS tube M1 and the drain of the MOS tube M4, and the gate is connected to the MOS tube M1, the drain of the MOS tube M3 and the resistor R2;
  • the gate of the MOS tube M3 is connected to the gate of the MOS tube M5, the gate of the MOS tube M6, the drain of the MOS tube M7, and the MOS tube M8.
  • the source is connected to the common voltage VSS, and the drain is connected to the drain of the MOS tube M1 and the MOS tube.
  • the gate of M2 is connected;
  • the gate of the MOS tube M4 is connected to the drains of the MOS tube M5 and the MOS tube M6, the source is connected to the common voltage VSS, and the drain is connected to the drain of the MOS tube M2 and the gate of the MOS tube M1;
  • the source of the MOS tube M5 is connected to the power supply voltage VCC
  • the drain of the MOS tube M5 is connected to the drain of the MOS tube M6 and the gate of the MOS tube M4
  • the source of the MOS tube M6 is connected to the common voltage VSS.
  • the gate and the gate of the MOS tube M6 are connected with the gate of the MOS tube M3 and the drains of the MOS tube M7 and the MOS tube M8;
  • the source of the MOS tube M7 is connected to the power supply voltage VCC
  • the drain of the MOS tube M7 is connected to the drain of the MOS tube M8
  • the source of the MOS tube M8 is connected to the common voltage VSS
  • the gate of the MOS tube M7 is connected to the MOS tube M8.
  • the gates are respectively connected to the enable port VEN;
  • the drain of the MOS tube M9 is connected to the IO port, the source is connected to the common voltage VSS, and the gate is connected to the source;
  • the source of the MOS tube M10 is connected to the IO port, the drain is connected to the output port VOUT, the gate is connected to the resistor R2, and the substrate is connected to the IO port;
  • the gate of the MOS tube M11 is connected to the enable port VEN, the drain is connected to the resistor R3 and then connected to the output port VOUT, and the source is connected to the common voltage VSS;
  • the resistor R1 is connected between the source of the MOS tube M1, the source of the MOS tube M2 and the IO port;
  • the resistor R2 is connected between the gate of the MOS tube M10 and the gate of the MOS tube M2;
  • the resistor R3 is connected between the drain of the MOS transistor M11 and the output port VOUT.
  • the IO port function module in this embodiment includes MOS transistors M12, M13, and a resistor R4.
  • the MOS transistor M12 is a PMOS transistor
  • the MOS transistor M13 is an NMOS transistor.
  • the source of the MOS tube M12 is connected to the power supply voltage VCC, the gate is connected to the input port IN1, and the drain is connected to the resistor R4;
  • the drain of the MOS tube M13 is connected to the resistor R4, the source is connected to the common voltage VSS, and the gate is connected to the input port IN2;
  • the drain of the MOS tube M12 is connected to the input port IO_IN, and the drain of the MOS tube M13 is connected to the IO port.
  • the IO port when the high voltage transmission is turned off, the IO port can be used as a normal input and output.
  • the IO port When the input port IN1 is low and the input port IN2 is low, the IO port outputs a high level, and the input port When IN1 is high level and input port IN2 is high level, IO port outputs low level, when input port IN1 is high level and input port IN2 is low level, IO port outputs high impedance state, input port IO_IN passes IO port Input level.
  • the resistor R4 protects the input port IO_IN from static electricity, and the resistor R4 can prevent the IO port from being clamped by the power supply voltage VCC when a high voltage is applied.
  • the ESD protection module in this embodiment includes MOS transistors M14 and M15 and resistors R5 to R7, wherein the MOS transistor M14 is a PMOS transistor, and the MOS transistor M15 is an NMOS transistor.
  • the source of the MOS tube M14 is connected to the power supply voltage VCC, the gate is connected to the source, and the drain is connected to the resistor R5;
  • the drain of the MOS tube M15 is connected to the resistor R5, the source is connected to the common voltage VSS, and the gate is connected to the source;
  • the resistor R5 is located between the drain of the MOS transistor M14 and the drain of the MOS transistor M15;
  • the resistor R6 is located between the gate and the source of the MOS tube M14;
  • the resistor R7 is located between the gate and the source of the MOS tube M15;
  • the drain of the MOS tube M15 is connected to the IO port.
  • the MOS tube M14 and the MOS tube M15 in this embodiment are large-size transistors that comply with ESD rules, and are the main discharge path for static electricity.
  • R5 can prevent the IO port from being clamped by the power supply voltage VCC when a high voltage is applied to the IO port.
  • the GPIO multiplexing circuit of the present invention can realize the multiplexing of the high-voltage input pin with switch control and the GPIO port through ordinary MOS tubes and resistors under the ordinary CMOS process and no special devices, and has reliable ESD protection.

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Abstract

Disclosed is a GPIO multiplexing circuit based on high-voltage input and ESD protection. The GPIO multiplexing circuit comprises a high-voltage input module, an IO port functional module and an ESD protection module connected to an IO port, wherein the high-voltage input module is of a high-voltage transmission structure with switch control, and comprises several MOS transistors and resistors; the IO port functional module comprises several MOS transistors and resistors; and the ESD protection module comprises several MOS transistors and resistors. With the present invention, in a common CMOS process, when no special device is used, the GPIO multiplexing circuit of the present invention can realize the multiplexing of a high-voltage input pin with switch control and a GPIO port by means of common MOS transistors and resistors, and has reliable ESD protection.

Description

基于高压输入及ESD防护的GPIO复用电路GPIO multiplexing circuit based on high voltage input and ESD protection 技术领域Technical field
本发明属于集成电路技术领域，具体涉及一种基于高压输入及ESD防护的GPIO复用电路。The invention belongs to the technical field of integrated circuits, and specifically relates to a GPIO multiplexing circuit based on high voltage input and ESD protection.
背景技术Background technique
GPIO功能越来越复杂，当管脚是带开关控制的高压输入脚时，普通IO端口结构便不适用此，同时普通的ESD防护也不适用于该管脚。GPIO functions are becoming more and more complex. When the pin is a high-voltage input pin with switch control, the ordinary IO port structure is not suitable for this, and ordinary ESD protection is not suitable for this pin.
因此，针对上述技术问题，有必要提供一种基于高压输入及ESD防护的GPIO复用电路。Therefore, in view of the above technical problems, it is necessary to provide a GPIO multiplexing circuit based on high voltage input and ESD protection.
发明内容Summary of the invention
本发明的目的在于提供一种基于高压输入及ESD防护的GPIO复用电路，以实现带开关控制的高压输入脚与GPIO口的复用，且有着可靠的ESD防护。The purpose of the present invention is to provide a GPIO multiplexing circuit based on high-voltage input and ESD protection, so as to realize the multiplexing of the high-voltage input pin with switch control and the GPIO port, and has reliable ESD protection.
为了实现上述目的，本发明一实施例提供的技术方案如下：In order to achieve the foregoing objective, the technical solution provided by an embodiment of the present invention is as follows:
一种基于高压输入及ESD防护的GPIO复用电路，所述GPIO复用电路包括与IO端口相连的高压输入模块、IO端口功能模块、及ESD防护模块，所述高压输入模块为带开关控制的高压传输结构，其包括若干MOS管及电阻，IO端口功能模块包括若干MOS管及电阻，ESD防护模块包括若干MOS管及电阻。A GPIO multiplexing circuit based on high voltage input and ESD protection. The GPIO multiplexing circuit includes a high voltage input module connected to an IO port, an IO port function module, and an ESD protection module. The high voltage input module is a switch controlled The high-voltage transmission structure includes a number of MOS tubes and resistors, the IO port function module includes a number of MOS tubes and resistors, and the ESD protection module includes a number of MOS tubes and resistors.
一实施例中，所述高压输入模块包括MOS管M1～M11及电阻R1～R3，其中：In an embodiment, the high-voltage input module includes MOS transistors M1 to M11 and resistors R1 to R3, wherein:
MOS管M1、MOS管M2与IO端口相连，MOS管M3与MOS管M1相连，MOS管M4与MOS管M2相连，且MOS管M1与MOS管M4相连，MOS管M2与MOS管M3相连，MOS管M5和MOS管M6分别与MOS管M3和MOS管M4相连，MOS管M7和MOS管M8分别与使能端口VEN和MOS管M3相连，且MOS管M5和MOS管M7分别与电源电压VCC相连，MOS管M3、MOS管M4、MOS管M6、MOS管M8分别与公共电压VSS相连；MOS tube M1 and MOS tube M2 are connected to the IO port, MOS tube M3 is connected to MOS tube M1, MOS tube M4 is connected to MOS tube M2, MOS tube M1 is connected to MOS tube M4, MOS tube M2 is connected to MOS tube M3, MOS Tube M5 and MOS tube M6 are respectively connected to MOS tube M3 and MOS tube M4, MOS tube M7 and MOS tube M8 are respectively connected to enable port VEN and MOS tube M3, and MOS tube M5 and MOS tube M7 are respectively connected to power supply voltage VCC , The MOS tube M3, the MOS tube M4, the MOS tube M6, and the MOS tube M8 are respectively connected to the common voltage VSS;
MOS管M9连接于IO端口与公共电压VSS之间；The MOS tube M9 is connected between the IO port and the common voltage VSS;
MOS管M10连接于IO端口与输出端口VOUT之间；The MOS tube M10 is connected between the IO port and the output port VOUT;
MOS管M11连接于使能端口VEN与输出端口VOUT之间，且MOS管M11与公共电压VSS相连；The MOS tube M11 is connected between the enable port VEN and the output port VOUT, and the MOS tube M11 is connected with the common voltage VSS;
电阻R1连接于MOS管M1、MOS管M2和IO端口之间；The resistor R1 is connected between the MOS tube M1, the MOS tube M2 and the IO port;
电阻R2连接于MOS管M10与MOS管M2之间；The resistor R2 is connected between the MOS tube M10 and the MOS tube M2;
电阻R3连接于MOS管M11与输出端口VOUT之间。The resistor R3 is connected between the MOS tube M11 and the output port VOUT.
一实施例中，所述MOS管M1、MOS管M2、MOS管M5、MOS管M7、MOS管M10为PMOS管，MOS管M3、MOS管M4、MOS管M6、MOS管M8、MOS管M9、MOS管M11为NMOS管。In one embodiment, the MOS tube M1, MOS tube M2, MOS tube M5, MOS tube M7, and MOS tube M10 are PMOS tubes, and MOS tube M3, MOS tube M4, MOS tube M6, MOS tube M8, MOS tube M9, The MOS tube M11 is an NMOS tube.
一实施例中，所述高压输入模块中：In an embodiment, in the high-voltage input module:
MOS管M1的源极与电阻R1相连，漏极与MOS管M3的漏极和MOS管M2的栅极相连，栅极与MOS管M2的漏极和MOS管M4的漏极相连；The source of the MOS tube M1 is connected to the resistor R1, the drain is connected to the drain of the MOS tube M3 and the gate of the MOS tube M2, and the gate is connected to the drain of the MOS tube M2 and the drain of the MOS tube M4;
MOS管M2的源极与电阻R1相连，漏极与MOS管M1的栅极和MOS管M4的漏极相连，栅极与MOS管M1、MOS管M3的漏极及电阻R2相连；The source of the MOS tube M2 is connected to the resistor R1, the drain is connected to the gate of the MOS tube M1 and the drain of the MOS tube M4, and the gate is connected to the MOS tube M1, the drain of the MOS tube M3 and the resistor R2;
MOS管M3的栅极与MOS管M5、MOS管M6的栅极、MOS管M7、MOS管M8的漏极相连，源极与公共电压VSS相连，漏极与MOS管M1的漏极和MOS管M2的栅极相连；The gate of the MOS tube M3 is connected to the gate of the MOS tube M5, the gate of the MOS tube M6, the drain of the MOS tube M7, and the MOS tube M8. The source is connected to the common voltage VSS, and the drain is connected to the drain of the MOS tube M1 and the MOS tube. The gate of M2 is connected;
MOS管M4的栅极与MOS管M5和MOS管M6的漏极相连，源极与公共电压VSS相连，漏极与MOS管M2的漏极和MOS管M1的栅极相连；The gate of the MOS tube M4 is connected to the drains of the MOS tube M5 and the MOS tube M6, the source is connected to the common voltage VSS, and the drain is connected to the drain of the MOS tube M2 and the gate of the MOS tube M1;
MOS管M5的源极与电源电压VCC相连，MOS管M5的漏极与MOS管M6的漏极和MOS管M4的栅极相连，MOS管M6的源极与公共电压VSS相连，MOS管M5的栅极和MOS管M6的栅极与MOS管M3的栅极及MOS管M7和MOS管M8的漏极相连；The source of the MOS tube M5 is connected to the power supply voltage VCC, the drain of the MOS tube M5 is connected to the drain of the MOS tube M6 and the gate of the MOS tube M4, and the source of the MOS tube M6 is connected to the common voltage VSS. The gate and the gate of the MOS tube M6 are connected with the gate of the MOS tube M3 and the drains of the MOS tube M7 and the MOS tube M8;
MOS管M7的源极与电源电压VCC相连，MOS管M7的漏极与MOS管M8的漏极相连，MOS管M8的源极与公共电压VSS相连，MOS管M7的栅极和MOS管M8的栅极分别与使能端口VEN相连；The source of the MOS tube M7 is connected to the power supply voltage VCC, the drain of the MOS tube M7 is connected to the drain of the MOS tube M8, the source of the MOS tube M8 is connected to the common voltage VSS, and the gate of the MOS tube M7 is connected to the MOS tube M8. The gates are respectively connected to the enable port VEN;
MOS管M9的漏极与IO端口相连，源极与公共电压VSS相连，栅极与源极相连；The drain of the MOS tube M9 is connected to the IO port, the source is connected to the common voltage VSS, and the gate is connected to the source;
MOS管M10的源极与IO端口相连，漏极与输出端口VOUT相连，栅极与电阻R2相连，衬底与IO端口相连；The source of the MOS tube M10 is connected to the IO port, the drain is connected to the output port VOUT, the gate is connected to the resistor R2, and the substrate is connected to the IO port;
MOS管M11的栅极与使能端口VEN相连，漏极接电阻R3后与输出端口VOUT相连，源极与公共电压VSS相连；The gate of the MOS tube M11 is connected to the enable port VEN, the drain is connected to the resistor R3 and then connected to the output port VOUT, and the source is connected to the common voltage VSS;
电阻R1连接于MOS管M1的源极、MOS管M2的源极和IO端口之间；The resistor R1 is connected between the source of the MOS tube M1, the source of the MOS tube M2 and the IO port;
电阻R2连接于MOS管M10的栅极与MOS管M2的栅极之间；The resistor R2 is connected between the gate of the MOS tube M10 and the gate of the MOS tube M2;
电阻R3连接于MOS管M11的漏极与输出端口VOUT之间。The resistor R3 is connected between the drain of the MOS transistor M11 and the output port VOUT.
一实施例中，所述高压输入模块中，使能端口VEN输入低电平有效，MOS管M3打开，MOS管M2导通，MOS管M1关断，MOS管M10导通，电阻R2端电压为低，电阻R1端电压与IO端口一致，输出端口VOUT输出与IO端口接近的电压。In one embodiment, in the high-voltage input module, the enable port VEN input is active low, the MOS tube M3 is turned on, the MOS tube M2 is turned on, the MOS tube M1 is turned off, the MOS tube M10 is turned on, and the voltage at the resistor R2 is Low, the voltage at the resistor R1 terminal is consistent with the IO port, and the output port VOUT outputs a voltage close to the IO port.
一实施例中，所述IO端口功能模块包括MOS管M12、M13及电阻R4，其中：In an embodiment, the IO port function module includes MOS transistors M12, M13 and resistor R4, where:
MOS管M12的源极与电源电压VCC相连，栅极与输入端口IN1相连，漏极与电阻R4相连；The source of the MOS tube M12 is connected to the power supply voltage VCC, the gate is connected to the input port IN1, and the drain is connected to the resistor R4;
MOS管M13的漏极与电阻R4相连，源极与公共电压VSS相连，栅极与输入端口IN2相连；The drain of the MOS tube M13 is connected to the resistor R4, the source is connected to the common voltage VSS, and the gate is connected to the input port IN2;
电阻R4位于MOS管M12的漏极和MOS管M13的漏极之间；The resistor R4 is located between the drain of the MOS transistor M12 and the drain of the MOS transistor M13;
MOS管M12的漏极与输入端口IO_IN相连，MOS管M13的漏极与IO端口相连。The drain of the MOS tube M12 is connected to the input port IO_IN, and the drain of the MOS tube M13 is connected to the IO port.
一实施例中，所述MOS管M12为PMOS管，MOS管M13为NMOS管。In one embodiment, the MOS tube M12 is a PMOS tube, and the MOS tube M13 is an NMOS tube.
一实施例中，所述IO端口功能模块中，当高压传输关闭时，IO端口作为普通的输入输出，输入端口IN1为低电平、输入端口IN2为低电平时，IO端口输出高电平，输入端口IN1为高电平、输入端口IN2为高电平时，IO端口输出低电平，输入端口IN1为高电平、输入端口IN2为低电平时，IO端口输出高阻态，输入端口IO_IN通过IO端口输入电平。In one embodiment, in the IO port function module, when the high voltage transmission is turned off, the IO port is used as a normal input and output. When the input port IN1 is low and the input port IN2 is low, the IO port outputs a high level. When the input port IN1 is high level and the input port IN2 is high level, the IO port outputs low level. When the input port IN1 is high level and the input port IN2 is low level, the IO port outputs a high impedance state, and the input port IO_IN passes IO port input level.
一实施例中，所述ESD防护模块包括MOS管M14、M15及电阻R5～R7，其中：In an embodiment, the ESD protection module includes MOS transistors M14 and M15 and resistors R5 to R7, wherein:
MOS管M14的源极与电源电压VCC相连，栅极与源极相连，漏极与电阻R5相连；The source of the MOS tube M14 is connected to the power supply voltage VCC, the gate is connected to the source, and the drain is connected to the resistor R5;
MOS管M15的漏极与电阻R5相连，源极与公共电压VSS相连，栅极与源极相连；The drain of the MOS tube M15 is connected to the resistor R5, the source is connected to the common voltage VSS, and the gate is connected to the source;
电阻R5位于MOS管M14的漏极和MOS管M15的漏极之间；The resistor R5 is located between the drain of the MOS transistor M14 and the drain of the MOS transistor M15;
电阻R6位于MOS管M14的栅极和源极之间；The resistor R6 is located between the gate and the source of the MOS tube M14;
电阻R7位于MOS管M15的栅极和源极之间；The resistor R7 is located between the gate and the source of the MOS tube M15;
MOS管M15的漏极与IO端口相连。The drain of the MOS tube M15 is connected to the IO port.
一实施例中，所述MOS管M14为PMOS管，MOS管M15为NMOS管。In one embodiment, the MOS tube M14 is a PMOS tube, and the MOS tube M15 is an NMOS tube.
一实施例中，所述MOS管M14为PMOS管，MOS管M15为NMOS管。In one embodiment, the MOS tube M14 is a PMOS tube, and the MOS tube M15 is an NMOS tube.
与现有技术相比，本发明具有以下优点：Compared with the prior art, the present invention has the following advantages:
本发明GPIO复用电路在普通的CMOS工艺且不使用特殊器件下，通过普通的MOS管和电阻，即可实现带开关控制的高压输入脚与GPIO口的复用，且有着可靠的ESD防护。The GPIO multiplexing circuit of the present invention can realize the multiplexing of the high-voltage input pin with switch control and the GPIO port through ordinary MOS tubes and resistors under the ordinary CMOS process and no special devices, and has reliable ESD protection.
附图说明Description of the drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明中记载的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments described in the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work.
图1为本发明中GPIO复用电路的模块示意图；Figure 1 is a schematic diagram of a module of the GPIO multiplexing circuit in the present invention;
图2为本发明一具体实施例中高压输入模块的电路原理图；Fig. 2 is a schematic circuit diagram of a high-voltage input module in a specific embodiment of the present invention;
图3为本发明一具体实施例中IO端口功能模块的电路原理图；Fig. 3 is a schematic circuit diagram of an IO port function module in a specific embodiment of the present invention;
图4为本发明一具体实施例中ESD防护模块的电路原理图。Fig. 4 is a schematic circuit diagram of an ESD protection module in a specific embodiment of the present invention.
具体实施方式Detailed ways
以下将结合附图所示的各实施方式对本发明进行详细描述。但该等实施方式并不限制本发明，本领域的普通技术人员根据该等实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。Hereinafter, the present invention will be described in detail with reference to the embodiments shown in the drawings. However, these embodiments do not limit the present invention, and the structural, method, or functional changes made by those skilled in the art based on these embodiments are all included in the protection scope of the present invention.
参图1所示，本发明公开了一种基于高压输入及ESD防护的GPIO复用电路，GPIO复用电路包括与IO端口相连的高压输入模块、IO端口功能模块、及ESD防护模块，高压输入模块为带开关控制的高压传输结构，其包括若干MOS管及电阻，IO端口功能模块包括若干MOS管及电阻，ESD防护模块包括若干MOS管及电阻。As shown in Figure 1, the present invention discloses a GPIO multiplexing circuit based on high voltage input and ESD protection. The GPIO multiplexing circuit includes a high voltage input module connected to an IO port, an IO port function module, and an ESD protection module. The module is a high-voltage transmission structure with switch control, which includes a number of MOS tubes and resistors, the IO port function module includes a number of MOS tubes and resistors, and the ESD protection module includes a number of MOS tubes and resistors.
以下结合各模块对本发明作进一步说明。The present invention will be further described below in conjunction with each module.
高压输入模块：High voltage input module:
参图2所示，本实施例中的高压输入模块包括MOS管M1～M11及电阻R1～R3，其中，MOS管M1、MOS管M2、MOS管M5、MOS管M7、MOS管M10为PMOS管，MOS管M3、MOS管M4、MOS管M6、MOS管M8、MOS管M9、MOS管M11为NMOS管。As shown in Figure 2, the high-voltage input module in this embodiment includes MOS transistors M1 to M11 and resistors R1 to R3. Among them, MOS transistors M1, MOS transistors M2, MOS transistors M5, MOS transistors M7, and MOS transistors M10 are PMOS transistors. , MOS tube M3, MOS tube M4, MOS tube M6, MOS tube M8, MOS tube M9, MOS tube M11 are NMOS tubes.
本实施例中的MOS管M1、MOS管M2与IO端口相连，MOS管M3与MOS管M1相连，MOS管M4与MOS管M2相连，且MOS管M1与MOS管M4相连，MOS管M2与MOS管M3相连，MOS管M5和MOS管M6与MOS管M3和MOS管M4相连，MOS管M7和MOS管M8分别与使能端口VEN和MOS管M3相连，且MOS管M5和MOS管M7分别与电源电压VCC相连，MOS管M3、MOS管M4、MOS管M6、MOS管M8分别与公共电压VSS相连；In this embodiment, the MOS tube M1 and the MOS tube M2 are connected to the IO port, the MOS tube M3 is connected to the MOS tube M1, the MOS tube M4 is connected to the MOS tube M2, and the MOS tube M1 is connected to the MOS tube M4, and the MOS tube M2 is connected to the MOS tube. Tube M3 is connected, MOS tube M5 and MOS tube M6 are connected to MOS tube M3 and MOS tube M4, MOS tube M7 and MOS tube M8 are respectively connected to enable port VEN and MOS tube M3, and MOS tube M5 and MOS tube M7 are respectively connected to The power supply voltage VCC is connected, and the MOS tube M3, the MOS tube M4, the MOS tube M6, and the MOS tube M8 are respectively connected to the common voltage VSS;
MOS管M9连接于IO端口与公共电压VSS之间；The MOS tube M9 is connected between the IO port and the common voltage VSS;
MOS管M10连接于IO端口与输出端口VOUT之间；The MOS tube M10 is connected between the IO port and the output port VOUT;
MOS管M11连接于使能端口VEN与输出端口VOUT之间，且MOS管M11与公共电压VSS相连；The MOS tube M11 is connected between the enable port VEN and the output port VOUT, and the MOS tube M11 is connected with the common voltage VSS;
电阻R1连接于MOS管M1、MOS管M2和IO端口之间；The resistor R1 is connected between the MOS tube M1, the MOS tube M2 and the IO port;
电阻R2连接于MOS管M10与MOS管M2之间；The resistor R2 is connected between the MOS tube M10 and the MOS tube M2;
电阻R3连接于MOS管M11与输出端口VOUT之间。The resistor R3 is connected between the MOS tube M11 and the output port VOUT.
进一步地：further:
MOS管M1的源极与电阻R1相连，漏极与MOS管M3的漏极和MOS管M2的栅极相连，栅极与MOS管M2的漏极和MOS管M4的漏极相连；The source of the MOS tube M1 is connected to the resistor R1, the drain is connected to the drain of the MOS tube M3 and the gate of the MOS tube M2, and the gate is connected to the drain of the MOS tube M2 and the drain of the MOS tube M4;
MOS管M2的源极与电阻R1相连，漏极与MOS管M1的栅极和MOS管M4的漏极相连，栅极与MOS管M1、MOS管M3的漏极及电阻R2相连；The source of the MOS tube M2 is connected to the resistor R1, the drain is connected to the gate of the MOS tube M1 and the drain of the MOS tube M4, and the gate is connected to the MOS tube M1, the drain of the MOS tube M3 and the resistor R2;
MOS管M3的栅极与MOS管M5、MOS管M6的栅极、MOS管M7、MOS管M8的漏极相连，源极与公共电压VSS相连，漏极与MOS管M1的漏极和MOS管M2的栅极相连；The gate of the MOS tube M3 is connected to the gate of the MOS tube M5, the gate of the MOS tube M6, the drain of the MOS tube M7, and the MOS tube M8. The source is connected to the common voltage VSS, and the drain is connected to the drain of the MOS tube M1 and the MOS tube. The gate of M2 is connected;
MOS管M4的栅极与MOS管M5和MOS管M6的漏极相连，源极与公共电压VSS相连，漏极与MOS管M2的漏极和MOS管M1的栅极相连；The gate of the MOS tube M4 is connected to the drains of the MOS tube M5 and the MOS tube M6, the source is connected to the common voltage VSS, and the drain is connected to the drain of the MOS tube M2 and the gate of the MOS tube M1;
MOS管M5的源极与电源电压VCC相连，MOS管M5的漏极与MOS管 M6的漏极和MOS管M4的栅极相连，MOS管M6的源极与公共电压VSS相连，MOS管M5的栅极和MOS管M6的栅极与MOS管M3的栅极及MOS管M7和MOS管M8的漏极相连；The source of the MOS tube M5 is connected to the power supply voltage VCC, the drain of the MOS tube M5 is connected to the drain of the MOS tube M6 and the gate of the MOS tube M4, and the source of the MOS tube M6 is connected to the common voltage VSS. The gate and the gate of the MOS tube M6 are connected with the gate of the MOS tube M3 and the drains of the MOS tube M7 and the MOS tube M8;
MOS管M7的源极与电源电压VCC相连，MOS管M7的漏极与MOS管M8的漏极相连，MOS管M8的源极与公共电压VSS相连，MOS管M7的栅极和MOS管M8的栅极分别与使能端口VEN相连；The source of the MOS tube M7 is connected to the power supply voltage VCC, the drain of the MOS tube M7 is connected to the drain of the MOS tube M8, the source of the MOS tube M8 is connected to the common voltage VSS, and the gate of the MOS tube M7 is connected to the MOS tube M8. The gates are respectively connected to the enable port VEN;
MOS管M9的漏极与IO端口相连，源极与公共电压VSS相连，栅极与源极相连；The drain of the MOS tube M9 is connected to the IO port, the source is connected to the common voltage VSS, and the gate is connected to the source;
MOS管M10的源极与IO端口相连，漏极与输出端口VOUT相连，栅极与电阻R2相连，衬底与IO端口相连；The source of the MOS tube M10 is connected to the IO port, the drain is connected to the output port VOUT, the gate is connected to the resistor R2, and the substrate is connected to the IO port;
MOS管M11的栅极与使能端口VEN相连，漏极接电阻R3后与输出端口VOUT相连，源极与公共电压VSS相连；The gate of the MOS tube M11 is connected to the enable port VEN, the drain is connected to the resistor R3 and then connected to the output port VOUT, and the source is connected to the common voltage VSS;
电阻R1连接于MOS管M1的源极、MOS管M2的源极和IO端口之间；The resistor R1 is connected between the source of the MOS tube M1, the source of the MOS tube M2 and the IO port;
电阻R2连接于MOS管M10的栅极与MOS管M2的栅极之间；The resistor R2 is connected between the gate of the MOS tube M10 and the gate of the MOS tube M2;
电阻R3连接于MOS管M11的漏极与输出端口VOUT之间。The resistor R3 is connected between the drain of the MOS transistor M11 and the output port VOUT.
本实施例中的高压输入模块为带开关控制的高压传输结构，使能端口VEN输入低电平有效，MOS管M3打开，MOS管M2导通，MOS管M1关断，MOS管M10导通，电阻R2端电压为低，电阻R1端电压与IO端口一致，输出端口VOUT输出与IO端口接近的电压，不受电源电压VCC的钳位；使能端口VEN输入高电平无效，MOS管M11打开，将输出端口VOUT输出拉低为低电平。The high-voltage input module in this embodiment is a high-voltage transmission structure with switch control. The enable port VEN input is active at low level, the MOS tube M3 is turned on, the MOS tube M2 is turned on, the MOS tube M1 is turned off, and the MOS tube M10 is turned on. The voltage at the resistor R2 terminal is low, the voltage at the resistor R1 terminal is consistent with the IO port, the output port VOUT outputs a voltage close to the IO port, and is not clamped by the power supply voltage VCC; the high level of the enable port VEN input is invalid, and the MOS tube M11 is turned on , The output port VOUT output is pulled low to low level.
其中M10为大尺寸的PMOS管，符合端口ESD规则，衬底接IO端口，M9为大尺寸的ESD保护管，R1、R2、R3为ESD防护电阻，保护相关路径不为静电通路。Among them, M10 is a large-size PMOS tube, which complies with port ESD rules, and the substrate is connected to the IO port. M9 is a large-size ESD protection tube. R1, R2, and R3 are ESD protection resistors to protect related paths from electrostatic paths.
IO端口功能模块：IO port function module:
参图3所示，本实施例中的IO端口功能模块包括MOS管M12、M13及电阻R4，其中，MOS管M12为PMOS管，MOS管M13为NMOS管。As shown in FIG. 3, the IO port function module in this embodiment includes MOS transistors M12, M13, and a resistor R4. Among them, the MOS transistor M12 is a PMOS transistor, and the MOS transistor M13 is an NMOS transistor.
本实施例中的MOS管M12的源极与电源电压VCC相连，栅极与输入端口IN1相连，漏极与电阻R4相连；In this embodiment, the source of the MOS tube M12 is connected to the power supply voltage VCC, the gate is connected to the input port IN1, and the drain is connected to the resistor R4;
MOS管M13的漏极与电阻R4相连，源极与公共电压VSS相连，栅极与输入端口IN2相连；The drain of the MOS tube M13 is connected to the resistor R4, the source is connected to the common voltage VSS, and the gate is connected to the input port IN2;
电阻R4位于MOS管M12的漏极和MOS管M13的漏极之间；The resistor R4 is located between the drain of the MOS transistor M12 and the drain of the MOS transistor M13;
MOS管M12的漏极与输入端口IO_IN相连，MOS管M13的漏极与IO端口相连。The drain of the MOS tube M12 is connected to the input port IO_IN, and the drain of the MOS tube M13 is connected to the IO port.
本实施例的IO端口功能模块中，当高压传输关闭时，IO端口可以作为普通的输入输出，输入端口IN1为低电平、输入端口IN2为低电平时，IO端口输出高电平，输入端口IN1为高电平、输入端口IN2为高电平时，IO端口输出低电平，输入端口IN1为高电平、输入端口IN2为低电平时，IO端口输出高阻态，输入端口IO_IN通过IO端口输入电平。In the IO port function module of this embodiment, when the high voltage transmission is turned off, the IO port can be used as a normal input and output. When the input port IN1 is low and the input port IN2 is low, the IO port outputs a high level, and the input port When IN1 is high level and input port IN2 is high level, IO port outputs low level, when input port IN1 is high level and input port IN2 is low level, IO port outputs high impedance state, input port IO_IN passes IO port Input level.
电阻R4保护输入端口IO_IN不受静电影响，同时电阻R4能防止IO端口加高压时，不受电源电压VCC的钳位。The resistor R4 protects the input port IO_IN from static electricity, and the resistor R4 can prevent the IO port from being clamped by the power supply voltage VCC when a high voltage is applied.
ESD防护模块：ESD protection module:
参图4所示，本实施例中的ESD防护模块包括MOS管M14、M15及电阻R5～R7，其中，MOS管M14为PMOS管，MOS管M15为NMOS管。As shown in FIG. 4, the ESD protection module in this embodiment includes MOS transistors M14 and M15 and resistors R5 to R7, wherein the MOS transistor M14 is a PMOS transistor, and the MOS transistor M15 is an NMOS transistor.
本实施例中的MOS管M14的源极与电源电压VCC相连，栅极与源极相连，漏极与电阻R5相连；In this embodiment, the source of the MOS tube M14 is connected to the power supply voltage VCC, the gate is connected to the source, and the drain is connected to the resistor R5;
MOS管M15的漏极与电阻R5相连，源极与公共电压VSS相连，栅极与源极相连；The drain of the MOS tube M15 is connected to the resistor R5, the source is connected to the common voltage VSS, and the gate is connected to the source;
电阻R5位于MOS管M14的漏极和MOS管M15的漏极之间；The resistor R5 is located between the drain of the MOS transistor M14 and the drain of the MOS transistor M15;
电阻R6位于MOS管M14的栅极和源极之间；The resistor R6 is located between the gate and the source of the MOS tube M14;
电阻R7位于MOS管M15的栅极和源极之间；The resistor R7 is located between the gate and the source of the MOS tube M15;
MOS管M15的漏极与IO端口相连。The drain of the MOS tube M15 is connected to the IO port.
本实施例中的MOS管M14和MOS管M15为符合ESD规则的大尺寸晶体管，为静电的主要泄放通路，R5能防止IO端口加高压时，不受电源电压VCC的钳位。The MOS tube M14 and the MOS tube M15 in this embodiment are large-size transistors that comply with ESD rules, and are the main discharge path for static electricity. R5 can prevent the IO port from being clamped by the power supply voltage VCC when a high voltage is applied to the IO port.
由以上技术方案可以看出，本发明具有以下有益效果：It can be seen from the above technical solutions that the present invention has the following beneficial effects:
本发明GPIO复用电路在普通的CMOS工艺且不使用特殊器件下，通过普通的MOS管和电阻，即可实现带开关控制的高压输入脚与GPIO口的复用，且有着可靠的ESD防护。The GPIO multiplexing circuit of the present invention can realize the multiplexing of the high-voltage input pin with switch control and the GPIO port through ordinary MOS tubes and resistors under the ordinary CMOS process and no special devices, and has reliable ESD protection.
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description, and therefore it is intended to fall within the claims. All changes within the meaning and scope of the equivalent elements of are included in the present invention. Any reference signs in the claims should not be regarded as limiting the claims involved.
此外，应当理解，虽然本说明书按照实施例加以描述，但并非每个实施例仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施例中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。In addition, it should be understood that although this specification is described in accordance with the embodiments, not each embodiment only includes an independent technical solution. This narration in the specification is only for clarity, and those skilled in the art should regard the specification as a whole The technical solutions in the various embodiments can also be appropriately combined to form other implementations that can be understood by those skilled in the art.

Claims (10)

  1. 一种基于高压输入及ESD防护的GPIO复用电路，其特征在于，所述GPIO复用电路包括与IO端口相连的高压输入模块、IO端口功能模块、及ESD防护模块，所述高压输入模块为带开关控制的高压传输结构，其包括若干MOS管及电阻，IO端口功能模块包括若干MOS管及电阻，ESD防护模块包括若干MOS管及电阻。A GPIO multiplexing circuit based on high voltage input and ESD protection, wherein the GPIO multiplexing circuit includes a high voltage input module connected to an IO port, an IO port function module, and an ESD protection module, and the high voltage input module is The high-voltage transmission structure with switch control includes a number of MOS tubes and resistors, the IO port function module includes a number of MOS tubes and resistors, and the ESD protection module includes a number of MOS tubes and resistors.
  2. 根据权利要求1所述的基于高压输入及ESD防护的GPIO复用电路，其特征在于，所述高压输入模块包括MOS管M1～M11及电阻R1～R3，其中：The GPIO multiplexing circuit based on high voltage input and ESD protection according to claim 1, wherein the high voltage input module includes MOS transistors M1 to M11 and resistors R1 to R3, wherein:
    MOS管M1、MOS管M2与IO端口相连，MOS管M3与MOS管M1相连，MOS管M4与MOS管M2相连，且MOS管M1与MOS管M4相连，MOS管M2与MOS管M3相连，MOS管M5和MOS管M6分别与MOS管M3和MOS管M4相连，MOS管M7和MOS管M8分别与使能端口VEN和MOS管M3相连，且MOS管M5和MOS管M7分别与电源电压VCC相连，MOS管M3、MOS管M4、MOS管M6、MOS管M8分别与公共电压VSS相连；MOS tube M1 and MOS tube M2 are connected to the IO port, MOS tube M3 is connected to MOS tube M1, MOS tube M4 is connected to MOS tube M2, MOS tube M1 is connected to MOS tube M4, MOS tube M2 is connected to MOS tube M3, MOS Tube M5 and MOS tube M6 are respectively connected to MOS tube M3 and MOS tube M4, MOS tube M7 and MOS tube M8 are respectively connected to enable port VEN and MOS tube M3, and MOS tube M5 and MOS tube M7 are respectively connected to power supply voltage VCC , The MOS tube M3, the MOS tube M4, the MOS tube M6, and the MOS tube M8 are respectively connected to the common voltage VSS;
    MOS管M9连接于IO端口与公共电压VSS之间；The MOS tube M9 is connected between the IO port and the common voltage VSS;
    MOS管M10连接于IO端口与输出端口VOUT之间；The MOS tube M10 is connected between the IO port and the output port VOUT;
    MOS管M11连接于使能端口VEN与输出端口VOUT之间，且MOS管M11与公共电压VSS相连；The MOS tube M11 is connected between the enable port VEN and the output port VOUT, and the MOS tube M11 is connected with the common voltage VSS;
    电阻R1连接于MOS管M1、MOS管M2和IO端口之间；The resistor R1 is connected between the MOS tube M1, the MOS tube M2 and the IO port;
    电阻R2连接于MOS管M10与MOS管M2之间；The resistor R2 is connected between the MOS tube M10 and the MOS tube M2;
    电阻R3连接于MOS管M11与输出端口VOUT之间。The resistor R3 is connected between the MOS tube M11 and the output port VOUT.
  3. 根据权利要求2所述的基于高压输入及ESD防护的GPIO复用电路，其特征在于，所述MOS管M1、MOS管M2、MOS管M5、MOS管M7、MOS管M10为PMOS管，MOS管M3、MOS管M4、MOS管M6、MOS管M8、MOS管M9、MOS管M11为NMOS管。The GPIO multiplexing circuit based on high voltage input and ESD protection according to claim 2, wherein the MOS tube M1, MOS tube M2, MOS tube M5, MOS tube M7, and MOS tube M10 are PMOS tubes, and MOS tubes M3, MOS tube M4, MOS tube M6, MOS tube M8, MOS tube M9, and MOS tube M11 are NMOS tubes.
  4. 根据权利要求2所述的基于高压输入及ESD防护的GPIO复用电路，其特征在于，所述高压输入模块中：The GPIO multiplexing circuit based on high voltage input and ESD protection according to claim 2, wherein in the high voltage input module:
    MOS管M1的源极与电阻R1相连，漏极与MOS管M3的漏极和MOS管M2的栅极相连，栅极与MOS管M2的漏极和MOS管M4的漏极相连；The source of the MOS tube M1 is connected to the resistor R1, the drain is connected to the drain of the MOS tube M3 and the gate of the MOS tube M2, and the gate is connected to the drain of the MOS tube M2 and the drain of the MOS tube M4;
    MOS管M2的源极与电阻R1相连，漏极与MOS管M1的栅极和MOS管M4的漏极相连，栅极与MOS管M1、MOS管M3的漏极及电阻R2相连；The source of the MOS tube M2 is connected to the resistor R1, the drain is connected to the gate of the MOS tube M1 and the drain of the MOS tube M4, and the gate is connected to the MOS tube M1, the drain of the MOS tube M3 and the resistor R2;
    MOS管M3的栅极与MOS管M5、MOS管M6的栅极、MOS管M7、MOS管M8的漏极相连，源极与公共电压VSS相连，漏极与MOS管M1的漏极和MOS管M2的栅极相连；The gate of the MOS tube M3 is connected to the gate of the MOS tube M5, the gate of the MOS tube M6, the drain of the MOS tube M7, and the MOS tube M8. The source is connected to the common voltage VSS, and the drain is connected to the drain of the MOS tube M1 and the MOS tube. The gate of M2 is connected;
    MOS管M4的栅极与MOS管M5和MOS管M6的漏极相连，源极与公共电压VSS相连，漏极与MOS管M2的漏极和MOS管M1的栅极相连；The gate of the MOS tube M4 is connected to the drains of the MOS tube M5 and the MOS tube M6, the source is connected to the common voltage VSS, and the drain is connected to the drain of the MOS tube M2 and the gate of the MOS tube M1;
    MOS管M5的源极与电源电压VCC相连，MOS管M5的漏极与MOS管M6的漏极和MOS管M4的栅极相连，MOS管M6的源极与公共电压VSS相连， MOS管M5的栅极和MOS管M6的栅极与MOS管M3的栅极及MOS管M7和MOS管M8的漏极相连；The source of the MOS tube M5 is connected to the power supply voltage VCC, the drain of the MOS tube M5 is connected to the drain of the MOS tube M6 and the gate of the MOS tube M4, and the source of the MOS tube M6 is connected to the common voltage VSS. The gate and the gate of the MOS tube M6 are connected with the gate of the MOS tube M3 and the drains of the MOS tube M7 and the MOS tube M8;
    MOS管M7的源极与电源电压VCC相连，MOS管M7的漏极与MOS管M8的漏极相连，MOS管M8的源极与公共电压VSS相连，MOS管M7的栅极和MOS管M8的栅极分别与使能端口VEN相连；The source of the MOS tube M7 is connected to the power supply voltage VCC, the drain of the MOS tube M7 is connected to the drain of the MOS tube M8, the source of the MOS tube M8 is connected to the common voltage VSS, and the gate of the MOS tube M7 is connected to the MOS tube M8. The gates are respectively connected to the enable port VEN;
    MOS管M9的漏极与IO端口相连，源极与公共电压VSS相连，栅极与源极相连；The drain of the MOS tube M9 is connected to the IO port, the source is connected to the common voltage VSS, and the gate is connected to the source;
    MOS管M10的源极与IO端口相连，漏极与输出端口VOUT相连，栅极与电阻R2相连，衬底与IO端口相连；The source of the MOS tube M10 is connected to the IO port, the drain is connected to the output port VOUT, the gate is connected to the resistor R2, and the substrate is connected to the IO port;
    MOS管M11的栅极与使能端口VEN相连，漏极接电阻R3后与输出端口VOUT相连，源极与公共电压VSS相连；The gate of the MOS tube M11 is connected to the enable port VEN, the drain is connected to the resistor R3 and then connected to the output port VOUT, and the source is connected to the common voltage VSS;
    电阻R1连接于MOS管M1的源极、MOS管M2的源极和IO端口之间；The resistor R1 is connected between the source of the MOS tube M1, the source of the MOS tube M2 and the IO port;
    电阻R2连接于MOS管M10的栅极与MOS管M2的栅极之间；The resistor R2 is connected between the gate of the MOS tube M10 and the gate of the MOS tube M2;
    电阻R3连接于MOS管M11的漏极与输出端口VOUT之间。The resistor R3 is connected between the drain of the MOS transistor M11 and the output port VOUT.
  5. 根据权利要求4所述的基于高压输入及ESD防护的GPIO复用电路，其特征在于，所述高压输入模块中，使能端口VEN输入低电平有效，MOS管M3打开，MOS管M2导通，MOS管M1关断，MOS管M10导通，电阻R2端电压为低，电阻R1端电压与IO端口一致，输出端口VOUT输出与IO端口接近的电压。The GPIO multiplexing circuit based on high voltage input and ESD protection according to claim 4, characterized in that, in the high voltage input module, the enable port VEN input is active low, the MOS transistor M3 is turned on, and the MOS transistor M2 is turned on , The MOS tube M1 is turned off, the MOS tube M10 is turned on, the voltage at the resistor R2 is low, the voltage at the resistor R1 is consistent with the IO port, and the output port VOUT outputs a voltage close to the IO port.
  6. 根据权利要求1所述的基于高压输入及ESD防护的GPIO复用电路，其特征在于，所述IO端口功能模块包括MOS管M12、M13及电阻R4，其中：The GPIO multiplexing circuit based on high voltage input and ESD protection according to claim 1, wherein the IO port function module includes MOS transistors M12, M13 and resistor R4, wherein:
    MOS管M12的源极与电源电压VCC相连，栅极与输入端口IN1相连，漏极与电阻R4相连；The source of the MOS tube M12 is connected to the power supply voltage VCC, the gate is connected to the input port IN1, and the drain is connected to the resistor R4;
    MOS管M13的漏极与电阻R4相连，源极与公共电压VSS相连，栅极与输入端口IN2相连；The drain of the MOS tube M13 is connected to the resistor R4, the source is connected to the common voltage VSS, and the gate is connected to the input port IN2;
    电阻R4位于MOS管M12的漏极和MOS管M13的漏极之间；The resistor R4 is located between the drain of the MOS transistor M12 and the drain of the MOS transistor M13;
    MOS管M12的漏极与输入端口IO_IN相连，MOS管M13的漏极与IO端口相连。The drain of the MOS tube M12 is connected to the input port IO_IN, and the drain of the MOS tube M13 is connected to the IO port.
  7. 根据权利要求6所述的基于高压输入及ESD防护的GPIO复用电路，其特征在于，所述MOS管M12为PMOS管，MOS管M13为NMOS管。The GPIO multiplexing circuit based on high voltage input and ESD protection according to claim 6, wherein the MOS tube M12 is a PMOS tube, and the MOS tube M13 is an NMOS tube.
  8. 根据权利要求6所述的基于高压输入及ESD防护的GPIO复用电路，其特征在于，所述IO端口功能模块中，当高压传输关闭时，IO端口作为普通的输入输出，输入端口IN1为低电平、输入端口IN2为低电平时，IO端口输出高电平，输入端口IN1为高电平、输入端口IN2为高电平时，IO端口输出低电平，输入端口IN1为高电平、输入端口IN2为低电平时，IO端口输出高阻态，输入端口IO_IN通过IO端口输入电平。The GPIO multiplexing circuit based on high voltage input and ESD protection according to claim 6, characterized in that, in the IO port function module, when the high voltage transmission is turned off, the IO port is used as a normal input and output, and the input port IN1 is low. When the input port IN2 is low level, the IO port outputs high level, when the input port IN1 is high level, and the input port IN2 is high level, the IO port outputs low level, and the input port IN1 is high level, input When the port IN2 is low, the IO port outputs a high impedance state, and the input port IO_IN inputs the level through the IO port.
  9. 根据权利要求1所述的基于高压输入及ESD防护的GPIO复用电路，其特征在于，所述ESD防护模块包括MOS管M14、M15及电阻R5～R7，其中：The GPIO multiplexing circuit based on high voltage input and ESD protection according to claim 1, wherein the ESD protection module includes MOS transistors M14 and M15 and resistors R5 to R7, wherein:
    MOS管M14的源极与电源电压VCC相连，栅极与源极相连，漏极与电阻R5相连；The source of the MOS tube M14 is connected to the power supply voltage VCC, the gate is connected to the source, and the drain is connected to the resistor R5;
    MOS管M15的漏极与电阻R5相连，源极与公共电压VSS相连，栅极与源极相连；The drain of the MOS tube M15 is connected to the resistor R5, the source is connected to the common voltage VSS, and the gate is connected to the source;
    电阻R5位于MOS管M14的漏极和MOS管M15的漏极之间；The resistor R5 is located between the drain of the MOS transistor M14 and the drain of the MOS transistor M15;
    电阻R6位于MOS管M14的栅极和源极之间；The resistor R6 is located between the gate and the source of the MOS tube M14;
    电阻R7位于MOS管M15的栅极和源极之间；The resistor R7 is located between the gate and the source of the MOS tube M15;
    MOS管M15的漏极与IO端口相连。The drain of the MOS tube M15 is connected to the IO port.
  10. 根据权利要求9所述的基于高压输入及ESD防护的GPIO复用电路，其特征在于，所述MOS管M14为PMOS管，MOS管M15为NMOS管。The GPIO multiplexing circuit based on high voltage input and ESD protection according to claim 9, wherein the MOS tube M14 is a PMOS tube, and the MOS tube M15 is an NMOS tube.
PCT/CN2020/121865 2019-11-07 2020-10-19 Gpio multiplexing circuit based on high-voltage input and esd protection WO2021088628A1 (en)

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