KR20100002855A - Mos transistor and method for manufacturing of the same - Google Patents

Mos transistor and method for manufacturing of the same Download PDF

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Publication number
KR20100002855A
KR20100002855A KR1020080062904A KR20080062904A KR20100002855A KR 20100002855 A KR20100002855 A KR 20100002855A KR 1020080062904 A KR1020080062904 A KR 1020080062904A KR 20080062904 A KR20080062904 A KR 20080062904A KR 20100002855 A KR20100002855 A KR 20100002855A
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KR
South Korea
Prior art keywords
mos transistor
voltage terminal
metal options
adjacent
lines
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KR1020080062904A
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Korean (ko)
Inventor
박은영
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020080062904A priority Critical patent/KR20100002855A/en
Publication of KR20100002855A publication Critical patent/KR20100002855A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A MOS transistor and a method for manufacturing the same are provided to improve waste of time due to revision by varying the width of the MOS transistor arranged on a spare logic. CONSTITUTION: A plurality of PMOS transistors(20) and NMOS transistors are formed with a finger structure. A plurality of input lines(30) share each source and are commonly connected to the gates of the PMOS transistors and the NMOS transistors. A plurality of output lines(40) share each drain and are commonly connected to the drain of the PMOS transistors and the NMOS transistors. A plurality of first metal options are formed between respective input lines and selectively connect the adjacent input lines. The plurality of second metal options are formed between respective output lines and selectively connect the adjacent output lines.

Description

MOS transistor and method for manufacturing of the same

TECHNICAL FIELD The present invention relates to semiconductor design, and more particularly, to a MOS transistor having a variable width and a method of forming the same.

In general, the semiconductor device configures logic for performing various functions, and additionally configures spare logic to cope with a failure or a change in logic intended by the design.

The spare logic is composed of devices such as a PMOS transistor, an NMOS transistor, an inverter, a NAND gate, and a noble gate.

Meanwhile, according to the related art, the size of the elements constituting the spare logic is set to the sizes with the highest frequency of use in the logic configuration.

In particular, since the MOS transistor has a fixed width and cannot be adjusted, when the logic is defective or there is no MOS transistor of the desired size, a large time loss due to revision occurs, and a mask constituting the MOS transistor Since the mask must be newly manufactured, there is a problem that the mask loss increases.

The present invention provides a MOS transistor capable of varying the width of the MOS transistor disposed in the spare logic.

The present invention also provides a method of forming the MOS transistor.

The MOS transistor of the present invention includes a plurality of PMOS transistors and NMOS transistors formed of a finger structure; A plurality of input lines sharing respective sources and having common gates of adjacent PMOS transistors and the NMOS transistors; A plurality of output lines sharing respective drains and having a common connection between adjacent PMOS transistors and the drains of the NMOS transistors; A plurality of first metal options formed between each input line and selectively connecting adjacent input lines; And a plurality of second metal options formed between each output line and selectively connecting adjacent output lines.

Preferably, the apparatus further comprises a plurality of third metal options formed between each input line and the ground voltage terminal and selectively connecting the input line and the ground voltage terminal.

Here, the source of each PMOS transistor is connected to a power supply voltage terminal and the source of each NMOS transistor is preferably connected to a ground voltage terminal.

In the method of forming the MOS transistor of the present invention, a plurality of PMOS transistors and NMOS transistors having a predetermined unit width are formed in a finger structure, and the gates of the adjacent PMOS transistors and the NMOS transistors that share a source forming the finger structure are adjacent to each other. A plurality of input lines having a common connection are formed, and a plurality of output lines sharing a drain forming the finger structure and having common drains of the adjacent PMOS transistors and the NMOS transistors are formed. A plurality of first metal options for selectively connecting input lines are formed between each input line, and a plurality of second metal options for selectively connecting adjacent output lines are formed between each output line.

Preferably, a plurality of third metal options are formed between each input line and the ground voltage terminal and selectively connect the input line and the ground voltage terminal.

Preferably, the input lines and the output lines adjacent to each other are sequentially connected or separated by the first and second metal options to adjust the width of the MOS transistor.

In addition, the widths of the MOS transistors are adjusted by connecting or disconnecting the input lines and the ground voltage terminal by the third metal options in the connection state opposite to the first and second metal options.

Here, it is preferable that the source of each PMOS transistor is connected to a power supply voltage terminal and the source of each NMOS transistor is connected to a ground voltage terminal.

The present invention forms a MOS transistor disposed in the spare logic in a finger structure, and forms first metal options for selectively connecting input lines connected to a gate and second metal options for selectively connecting output lines connected to a drain. Therefore, the MOS transistors of the desired width can be provided by connecting or disconnecting them sequentially to improve the time loss caused by the revision.

In addition, since the width of the MOS transistor is controlled by the connection state of the first and second metal options, the metal option mask is rewritten if necessary to provide a MOS transistor having a desired width, thereby reducing mask fabrication time and mask fabrication cost. There is.

The present invention provides a MOS transistor and a method for forming the same, which are disposed in a spare logic provided for logic failure and logic change of a semiconductor device, and whose width can be adjusted to facilitate revision.

Referring to FIG. 1, a MOS transistor according to an exemplary embodiment of the present invention is described with reference to an NMOS transistor 10, a PMOS transistor 20, input lines 30, output lines 40, and first and first transistors. Two option lines O_11 to O_15 and O_21 to O_24.

In the NMOS transistor 10, a plurality of sources S_11 to S_16 and drains D_11 to D_15 having a predetermined unit width W1 are alternately formed and fingered, and gates G_10 to G_19 between each source and drain. ) Is formed. Here, each of the sources S_11 to S_16 is connected to the ground voltage terminal VSS.

In the PMOS transistor 20, a plurality of sources S_21 to S_26 and drains D_21 to D_25 having a predetermined unit width W1 are alternately formed and fingered, and gates G_21 to G_19 between each source and drain. ) Is formed. Here, each of the drains D_21 to D_25 is connected to the power supply voltage terminal VDD.

Each input line 30 shares the gates G_10 to G_19 that share the respective sources S_11 to S_16 of the NMOS transistor 10, and each of the sources S_21 to S_26 that corresponds to the PMOS transistor 20. Gates G_20 to G_29 are commonly connected. In this case, each input line 30 is formed to be electrically separated from gates corresponding to adjacent sources in the finger structure.

Each output line 40 connects each of the drains D_11 to D_15 of the NMOS transistor 10 and the respective drains D_21 to D_25 of the PMOS transistor 20 corresponding thereto. In this case, the finger structure is formed to be electrically separated from an adjacent drain.

Each first metal option O_11 to O_15 is formed between the input lines 30, and each second metal option O_21 to O_24 is formed between the output lines 40.

In addition, the MOS transistor further includes third metal options O_31 to O_36 which selectively connect them between each input line 30 and the ground voltage terminal VSS.

 Here, the first to third metal options O_11 to O_15, O_21 to O_24, and O_31 to O_36 are formed of an insulator that electrically removes two objects with a focused ion beam (FIB), each of which is in a closed state. Can be changed to any one of the and Open state. The closed state is a state in which adjacent lines are electrically connected, and the open state is a state in which adjacent lines are electrically separated by a metal option.

In the MOS transistor configured as shown in FIG. 1, since the unit width W1 is 1 μm and 10 transistors are fingered, the MOS transistor may be adjusted to a maximum width of 10 μm.

Specifically, a method of adjusting the width of the MOS transistor configured as shown in FIG. 1 will be described.

As described above, the first metal options O_11 to O_15 are formed between the input lines 30, and the second metal options O_21 to O_24 are formed between the output lines 40. Three metal options O_31 to O_36 are formed between the input lines 30 and the ground voltage terminal VSS.

By combining the first to third metal options (O_11 to O_15, O_21 to O_24, O_31 to O_36) as shown in the table shown in FIG. 2, the width of the MOS transistor is at most 10um at 1um, the size of the minimum unit width W1. Can be adjusted up to.

For example, in case 1 of adjusting the width of a MOS transistor to a minimum width of 1 μm, as shown in FIG. 3, both the first and second metal options O_11 to O_15 and O_21 to O_24 are opened, and the third The metal option O_31 is opened and the remaining third metal options O_32 to O_36 are closed.

That is, when both of the first and second metal options O_11 to O_15 (O_21 to O_24) are open, the input lines 30 and the output lines 40 are all electrically separated, and thus the input signal is gated. It is input through G_10 and G_20 and output through drain D_11 and D_21. The remaining gates G_11 to G_19 and G_21 to G_29 are connected to the ground voltage terminal VSS by the closed third metal options O_32 to O_36. Therefore, since the MOS transistor is composed of one transistor having a unit width, the width is adjusted to 1 um.

As another example, in case 2 of adjusting the width of the MOS transistor to 3um, as shown in FIG. 4, the first metal option O_11 and the second metal option O_21 are closed and the remaining first and second metal options ( All of the O_12 to O_15 (O_22 to O_25) are opened, the third metal options O_31 to O_32 are opened, and the remaining third metal options O_33 to O_36 are closed.

That is, when the first metal option O_11 is closed, the input lines 30 connected to the gates G_10 to G_12 (G_20 to G_22) sharing the respective sources S_11 to S_12 and S_21 to S_22 are electrically connected. When the second metal option 0_21 is closed, the output lines 40 connected to the drains D_11 to D_12 and D_21 to D_22 are in an electrically conductive state. The remaining gates G_13 to G_19 and G_23 to G_29 are connected to the ground voltage terminal VSS by the closed third metal options O_33 to O_36. Therefore, since the MOS transistor is composed of three transistors having a unit width, the width is adjusted to 3 um.

As another example, in case 6 of adjusting the width of the MOS transistor to 10 μm, as shown in FIG. 5, the first and second metal options O_11 to O_15 and O_21 to O_24 are closed and the third metal option is closed. Open all of the fields O_31 to O_36.

That is, when all of the first metal options O_11 to O_15 are closed, the input lines 30 to which the gates S_10 to S_19 and S_20 to S_29 sharing the sources S_11 to S_16 and S_21 to S26 are connected. ) Are all electrically connected, and when all of the second metal options O_21 to O_24 are closed, the output lines 40 to which the drains D_11 to D_15 and D_21 to D_25 are electrically connected. Therefore, since the MOS transistor is composed of ten transistors having a unit width, the width is adjusted to 10 um.

As described above, in the MOS transistor of the present invention, the number of the first and second metal options O_11 to O_15 and O_21 to O_24 are sequentially closed, and the third metal options O_31 to O_36 are sequentially By increasing the number of openings, the width of the MOS transistor is increased, and vice versa, the width of the MOS transistor can be adjusted by decreasing the width of the MOS transistor. The result is easier revision and improved revision time. In addition, mask fabrication by changing metal options can be used to control the width of MOS transistors, thereby improving mask fabrication time and mask fabrication cost required for logic changes.

1 is a layout diagram of a MOS transistor according to an embodiment of the present invention.

FIG. 2 is a table illustrating a combination of first and third metal options for varying the width of the MOS transistor of FIG. 1. FIG.

3 to 5 are exemplary diagrams for adjusting the width of a MOS transistor in accordance with the combination of the first and third metal options shown in the table diagram of FIG. 2.

Claims (8)

A plurality of PMOS transistors and NMOS transistors formed of a finger structure; A plurality of input lines sharing respective sources and having common gates of adjacent PMOS transistors and the NMOS transistors; A plurality of output lines sharing respective drains and having a common connection between adjacent PMOS transistors and the drains of the NMOS transistors; A plurality of first metal options formed between each input line and selectively connecting adjacent input lines; And A plurality of second metal options formed between each output line and selectively connecting adjacent output lines; MOS transistor comprising a. The method of claim 1, And a plurality of third metal options formed between each input line and a ground voltage terminal and selectively connecting the input line and the ground voltage terminal. The method of claim 1, A source of each of the PMOS transistors is connected to a power supply voltage terminal and a source of each of the NMOS transistors is connected to a ground voltage terminal. A plurality of PMOS transistors and NMOS transistors having a predetermined unit width are formed in a finger structure, A plurality of input lines are formed which share the source forming the finger structure and are connected to the gates of the adjacent PMOS transistors and the NMOS transistors in common. A plurality of output lines sharing a drain forming the finger structure and having common drains of the adjacent PMOS transistors and the NMOS transistors are formed, A plurality of first metal options for selectively connecting adjacent input lines are formed between each input line, And a plurality of second metal options for selectively connecting adjacent output lines are formed between the respective output lines. The method of claim 4, wherein And forming a plurality of third metal options formed between each input line and the ground voltage terminal and selectively connecting the input line and the ground voltage terminal. The method of claim 5, wherein And the input lines and the output lines adjacent to each other are sequentially connected or separated by the first and second metal options to adjust the width of the MOS transistor. The method of claim 6, And a width of the MOS transistor is adjusted by connecting or disconnecting the input lines and the ground voltage terminal by the third metal options in opposing states of the first and second metal options. The method of claim 4, wherein And a source of each of the PMOS transistors is connected to a power supply voltage terminal and a source of each of the NMOS transistors is connected to a ground voltage terminal.
KR1020080062904A 2008-06-30 2008-06-30 Mos transistor and method for manufacturing of the same KR20100002855A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8774880B2 (en) 2010-07-23 2014-07-08 Blackberry Limited Mobile wireless communications device with electrically conductive continuous ring and related methods
US9621694B2 (en) 2010-07-23 2017-04-11 Blackberry Limited Mobile wireless communications device with shunt component and related methods
US10063678B2 (en) 2010-07-23 2018-08-28 Blackberry Limited System for controlling current along a housing of a mobile wireless communications device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8774880B2 (en) 2010-07-23 2014-07-08 Blackberry Limited Mobile wireless communications device with electrically conductive continuous ring and related methods
US9293807B2 (en) 2010-07-23 2016-03-22 Blackberry Limited Mobile wireless communications device with electrically conductive continuous ring and related methods
US9621694B2 (en) 2010-07-23 2017-04-11 Blackberry Limited Mobile wireless communications device with shunt component and related methods
US10063678B2 (en) 2010-07-23 2018-08-28 Blackberry Limited System for controlling current along a housing of a mobile wireless communications device

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