CN107431487B - FPGA based on compact ReRAM - Google Patents

Abstract

A push-pull resistive random access memory cell circuit includes an output node, a word line, and first and second bit lines. A first resistive random access memory device is connected between the first bit line and the output node, and a second resistive random access memory device is connected between the output node and the second bit line. The first program transistor has a gate connected to a word line, a drain connected to the output node, and a source. The second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness selected to withstand programming and erasing potentials encountered during operation of the push-pull ReRAM cell circuit.

Description

FPGA based on compact ReRAM

Cross reference to related applications

This international application claims priority to U.S. patent application No.15/010,222, entitled "Compact ReRAM Based FPGA," filed on 29/1/2016; this patent application claims the benefit of U.S. provisional patent application No.62/132,333 entitled "Compact ReRAM Based FPGA" filed 3/12/2015, the entire contents of which are incorporated herein by reference in this disclosure.

Background

Push-pull resistive random access memory (ReRAM) cells, such as those disclosed in U.S. patent No.8,415,650, are attractive for use in configuration memories for configurable logic integrated circuits, such as Field Programmable Gate Arrays (FPGAs).

When designing circuits using deep sub-micron (14nM and above) transistors, any variation in transistor pitch forces designers to use large transition regions to allow for lithographic production of patterns. The transition region may range from 0.2 μm to 1 μm or more and may be a significant disadvantage when designing configurable logic integrated circuits employing ReRAM push-pull configuration memory cell circuits with compact and efficient layout.

FPGAs require mixing logic, routing switches, and programming transistors. To eliminate the transition region required by the lithographic process requirements, all of the above listed devices must have the same pitch, including the channel length pitch. Typically, this requirement is incompatible with devices operating at different voltages.

For ReRAM memory cells, the transistor devices used to program these ReRAM memory cells will be subject to higher drain and gate biases than other transistors employed in the integrated circuit, and will switch at higher gate biases during programming and operation.

Therefore, there is a need for a design of ReRAM configuration memory cells that is not associated with these drawbacks. It is an object of the present invention to provide a ReRAM push-pull configuration memory cell circuit that eliminates this transition region.

Disclosure of Invention

According to the present invention, a push-pull ReRAM cell circuit employs two programming transistors cascaded in series and having the same pitch and channel length. The switching transistors used in the push-pull ReRAM cell circuit have the same pitch and channel length as the two programming transistors in order to maintain the same pitch and channel length for both the programming device and the switching transistors used to configure and/or interconnect the logic cells.

According to the present invention, a switching transistor whose state is configured by ReRAM will use the same thickness dielectric used in the programming transistor to mitigate the elevated gate stress during programming. The use of a thicker dielectric also allows the gate of the configuration switch to be at a higher V during operation_CCAt excessive speed, thereby allowing passage through full V_CCA logic signal.

According to one aspect of the present invention, a push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node, and a second resistive random access memory device is connected between the output node and the second bit line. The first program transistor has a gate connected to a word line, a drain connected to the output node, and a source. The second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness selected to withstand programming and erasing potentials encountered during operation of the push-pull ReRAM cell circuit.

According to another aspect of the invention, at least one switching transistor has a gate connected to the output node, a drain connected to the first logic network node, and a source connected to the second logic network node. The switch transistors have the same pitch, channel length, and gate dielectric thickness as the first and second program transistors.

Drawings

These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:

FIG. 1 is a schematic diagram of a push-pull ReRAM cell in accordance with an aspect of the present invention;

FIG. 2 is a cross-sectional view of an exemplary layout of a push-pull ReRAM cell of the present invention;

fig. 3 is a top view of an exemplary layout of a push-pull ReRAM cell of the present invention.

Description of the invention

Those skilled in the art will realize that the following description of the present invention is illustrative only and is not intended to be in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.

Referring initially to fig. 1, a schematic diagram illustrates an illustrative push-pull ReRAM cell circuit 10 in accordance with an aspect of the present invention. The first ReRAM device 12 is coupled in series with the second ReRAM device 14 to form a ReRAM cell 16. A first end of the series-connected ReRAM devices 12, 14 at one terminal of the ReRAM device 12 is coupled to a first Bit Line (BL)18, while a second end of the series-connected ReRAM devices 12, 14 at one terminal of the ReRAM device 14 is coupled to a second bit line (BL _ bar) 20. The ReRAM cell 16 depicted in fig. 1 is a front-to-back ReRAM cell, useful, inter alia, for biasing the switch as shown, but those skilled in the art will appreciate that back-to-back ReRAM cells may also be used in the present invention.

As described above, the ReRAM devices 12 and 14 together comprise a push-pull ReRAM cell 16. A common output node 22 between ReRAM devices 12 and 14 is connected to the gates of one or more switching transistors. Fig. 1 shows a common output node 22 connected to the gates of two switching transistors 24a and 24 b. The switching transistor 24a is shown connected between two logic network nodes 26a and 28 a. Similarly, the switching transistor 24b is shown connected between two logic network nodes 26b and 28 b. Those skilled in the art will appreciate that logic network nodes 26a, 26b, 28a and 28b may represent logic gates or other devices in a programmable integrated circuit that are connected together by switching transistors 24a and 24b, respectively, and may also represent a circuit network in a single logic device in such an integrated circuit that defines the functionality of the logic device, or may represent wiring interconnects in a programmable integrated circuit.

Although fig. 1 shows multiple switching transistors 24a and 24b so that more than one logic circuit network may be activated by a single push-pull ReRAM cell 16, those skilled in the art will appreciate that a single switching transistor may be connected to a common output node 22.

In accordance with one aspect of the present invention, the push-pull ReRAM cell 16 is programmed using a pair of n-channel programming transistors 30 and 32 cascaded in series. An N-channel programming transistor 30 has its drain connected to the common output node 22 of the push-pull ReRAM cell 16 and its source connected to the drain of an N-channel programming transistor 32. In a practical embodiment, a single n + region serves as the source for n-channel programming transistor 30 and the drain for n-channel programming transistor 32. The source of n-channel program transistor 32 is connected to word line WLS. By connecting the two n-channel programming transistors 30 and 32 in series, both n-channel programming transistors 30 and 32 can be designed to have the same pitch and channel length as n-channel switching transistors 24a and 24 b. The same pitch and channel length for switching transistors 24a and 24b are used for logic devices in the integrated circuit.

According to another aspect of the present invention, n-channel programming transistors 30 and 32 and n-channel switching transistors 24a and 24b are fabricated with the same gate electrical connections to thickness. n-channel programming transistors 30 and 32 have gate dielectric thicknesses selected to withstand the programming and erase potentials that ReRAM push-pull memory cells will experience during operation thereof. Most integrated circuits include input/output (I/O) transistors for interfacing the integrated circuit with external components. Because these transistors interface with components that often operate at higher voltages than those typically found inside an integrated circuit, I/O transistors are typically fabricated with a greater gate dielectric thickness than other transistors used inside the integrated circuit. Therefore, it may be convenient to employ n-channel programming transistors 30 and 32 having the same gate dielectric thickness as the I/O transistors.

Using the same larger gate dielectric thickness for transistors 24a and 24b will alleviate the elevated gate stress that switching transistors 24a and 24b would otherwise experience during programming because their gates are connected to common node 22 of push-pull ReRAM memory cell 16, and this node will experience the programming voltage during erasing and programming of memory cell 16. Using a thicker dielectric for the switching transistors 24a and 24b also allows the gates of the switching transistors 24a and 24b to be at a higher value V during operation_CCOver speed, thereby allowing the switching transistors 24a and 24b to pass through full V_CCA logic signal. Alternatively, a thin gate oxide may be used for the switching transistors 24a and 24b, but care should be taken to avoid stress during program and erase operations. This can be done by raising the source/drain bias to V during programming_CCLogic to proceed.

During normal operation of the programmable integrated circuit, the bit line BL 18 is connected to the voltage source V_CCAnd BL _ bar 20 connectionTo a potential such as ground. The WLS line may be connected to ground or to a slightly positive potential (such as 0.9V) to limit leakage in n-channel programming transistors 30 and 32. The push-pull ReRAM cell 16 is programmed such that only one of the ReRAM devices 12 and 14 is on at any one time, thereby pulling either the common node 22 up to the voltage on bit line BL 18 or the common node 22 down to the voltage on bit line BL _ bar (typically ground). A push-pull ReRAM cell 16 is shown in fig. 1 in which the ReRAM device 12 is on and the ReRAM device 14 is off. The common node 22 is thus pulled up to the voltage (V) on the bit line BL 18_CC) Thereby turning on the switching transistors 24a and 24b (shown as n-channel transistors in fig. 1).

Referring now to both fig. 2 and 3, exemplary layouts of the push-pull ReRAM cells of the present invention are shown. Fig. 2 is a cross-sectional view of an exemplary layout 40 of the push-pull ReRAM cell circuit 10 of the present invention. Fig. 3 is a top view of an exemplary layout 40 of the push-pull ReRAM cell circuit 10 of the present invention. Those skilled in the art will observe that the layouts shown in fig. 2 and 3 are illustrative only and not limiting.

The push-pull ReRAM cell circuit 10 (fig. 1) is formed in a p-type substrate or well 42 in an integrated processing circuit. n + region 44 forms the drain of n-channel programming transistor 30, while n + region 46 forms the source thereof and serves as the drain of n-channel programming transistor 32. Polysilicon or metal line 48 forms the gate of n-channel program transistor 30. n + region 50 forms the source of n-channel program transistor 32, while polysilicon or metal line 52 forms the gate thereof. As shown formed from the first metal interconnect layer (M1), contacts 54 connect the polysilicon gates 48 and 52 of the n-channel program transistors 30 and 32 to the word line 34. Those skilled in the art will appreciate that p-channel transistors may also be used in other embodiments of the present invention.

The switching transistor shown in fig. 3 includes a source region 56 and a drain region 58, which are separated by a gate 60. Note that the cross-sectional view of fig. 2 is made in part through the source region of one of the switching transistors 24a and 24 b. The switching transistor may be an n-channel or p-channel device. The ReRAM device 12 is formed between metal interconnect layers on the integrated circuit (e.g., between the first and second metal layers M1 and M2). In fig. 2 and 3, ReRAM device 12 is shown formed between M1 metal segment 62 and M2 metal segment 64. ReRAM device 12 is formed on metal segment 62 and is connected to M2 metal segment 64 through contact 66. The ReRAM device 12 is connected to the bit line BL 18 through a contact 68.

Contact to the common node 22 is made through contact 72 from segment M2 to segment M1 metal segment 70. Contact 74 connects M1 metal segment 70 to the polysilicon gate 60 of the switching transistor. ReRAM device 14 is shown formed between M1 metal segment 70 and M2 metal segment forming second bit line Bl _ bar 20. Contact 76 connects the M1ReRAM device 14 to the second bit line Bl _ bar 20. Contact 78 connects M1 metal segment 70 to n + region 44 forming the drain of n-channel program transistor 30. Metal segment 80 forms word line WLS and is connected by contact 82 to n + region 50, which forms the source of program transistor 32.

The push-pull ReRAM cell 16 is programmed by turning on the desired one of the ReRAM devices 12 and 14 to either turn off or turn on the switching transistors 24a and 24 b. First, both ReRAM devices 12 and 14 are erased. Erasing a ReRAM device means turning it off so that it no longer passes current. To erase the ReRAM device 12, the bit line BL 18 is tied to a high voltage (e.g., 1.8V) and the common node 22 is tied to ground. To avoid stressing the ReRAM device 14, the second bit line Bl _ bar 20 is also grounded such that there is no potential impressed across the ReRAM device 14. To erase the ReRAM device 14, the common node 22 is tied to a high voltage (e.g., 1.8V) and the second bit line Bl _ bar 20 is tied to ground. To avoid stressing the ReRAM device 12, the bit line BL 18 is also tied high so that there is no potential impressed across the ReRAM device 12.

When both ReRAM cells 12 and 14 are erased, a selected one of the two ReRAM devices 12 and 14 is programmed. To program the ReRAM device 12, the bit line BL 18 is grounded and the common node 22 is tied to a high voltage (e.g., 1.8V). To avoid stressing the ReRAM device 14 while programming the ReRAM device 12, the second bit line Bl _ bar 20 is also tied high, so that no potential is impressed across the ReRAM device 14. To program the ReRAM device 14, the common node 22 is grounded and the second bit line Bl _ bar 20 is tied high. To avoid stressing the ReRAM device 12, the bit line BL 18 is also grounded such that no potential is impressed across the ReRAM device 12.

According to another aspect of the invention, two series-connected n-channel programming transistors 30 and 32 are coupled between common node 22 and word line WLS. The gates of n-channel transistors 30 and 32 are connected together to word line WL 34.

Although the present disclosure relates to the application of a ReRAM memory device in which logic is switched at a first voltage and the ReRAM cells are programmed and erased at a second voltage, those skilled in the art will appreciate that it is also applicable to other devices in which it is desirable to switch two different voltages in different operating modes.

Although the present invention has been discussed in considerable detail with reference to certain preferred embodiments, other embodiments are possible. Therefore, the scope of the appended claims should not be limited to the description of the preferred embodiments contained in this disclosure.

Claims (5)

1. A push-pull resistive random access memory cell circuit, comprising:

an output node;

a word line;

a first bit line;

a second bit line;

a first resistive random access memory device connected between the first bit line and the output node;

a second resistive random access memory device connected between the output node and the second bit line;

a first program transistor having a gate connected to the word line, a drain connected to the output node, and a source; and

a second program transistor having a gate connected to the word line, a drain connected to the source of the first program transistor, and a source connected to word line WLS,

wherein the first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thicknesses of the first and second programming transistors being selected to withstand programming and erase potentials encountered during operation of the push-pull resistive random access memory cell circuit.

2. The push-pull resistive random access memory cell circuit of claim 1, wherein:

the push-pull resistive random access memory cell circuit is fabricated on an integrated circuit having an input/output transistor; and

the gate dielectrics of the first and second programming transistors have the same thickness as the gate dielectric of the input/output transistor.

3. The push-pull resistive random access memory cell circuit of claim 2, further comprising:

at least one switching transistor having a gate connected to the output node, a drain connected to a first logic network node, and a source connected to a second logic network node; and

wherein the switch transistor has the same pitch, channel length, and gate dielectric thickness as the first and second program transistors.

4. The push-pull resistive random access memory cell circuit of claim 1, wherein:

the push-pull resistive random access memory cell circuit is fabricated on an integrated circuit having a logic transistor; and

the gate dielectrics of the first and second program transistors have a thickness greater than a thickness of the gate dielectric of the logic transistor.

5. The push-pull resistive random access memory cell circuit of claim 4, further comprising:

at least one switching transistor having a gate connected to the output node, a drain connected to a first logic network node, and a source connected to a second logic network node; and

wherein the switch transistor has the same pitch, channel length, and gate dielectric thickness as the first and second program transistors.